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shader: support FP64 conversions used by FighterZ (#884)
shader: support float and unsigned widening to FP64 Co-authored-by: nmzik <Nmzik@mail.ru>
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@@ -156,6 +156,8 @@ enum class Opcode {
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V_DOT2C_F32_F16,
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V_CVT_F64_I32,
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V_CVT_F32_F64,
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V_CVT_F64_F32,
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V_CVT_F64_U32,
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V_CVT_F32_I32,
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V_CVT_F32_U32,
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V_CVT_U32_F32,
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@@ -89,6 +89,8 @@ constexpr OpcodeMap VOP1_OPCODE_LIST[] = {
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{0x02u, Opcode::V_READFIRSTLANE_B32},
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{0x04u, Opcode::V_CVT_F64_I32},
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{0x0fu, Opcode::V_CVT_F32_F64},
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{0x10u, Opcode::V_CVT_F64_F32},
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{0x16u, Opcode::V_CVT_F64_U32},
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{0x2fu, Opcode::V_RCP_F64},
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{0x05u, Opcode::V_CVT_F32_I32},
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{0x06u, Opcode::V_CVT_F32_U32},
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@@ -151,6 +153,8 @@ constexpr OpcodeMap VOP3_ENCODED_VOP1_OPCODE_LIST[] = {
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{0x02u, Opcode::V_READFIRSTLANE_B32},
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{0x04u, Opcode::V_CVT_F64_I32},
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{0x0fu, Opcode::V_CVT_F32_F64},
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{0x10u, Opcode::V_CVT_F64_F32},
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{0x16u, Opcode::V_CVT_F64_U32},
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{0x2fu, Opcode::V_RCP_F64},
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{0x05u, Opcode::V_CVT_F32_I32},
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{0x06u, Opcode::V_CVT_F32_U32},
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@@ -461,6 +465,7 @@ bool IsVopcCompareExec(Opcode opcode);
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bool IsVop1FloatSourceOpcode(Opcode opcode) {
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switch (opcode) {
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case Opcode::V_CVT_F32_F64:
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case Opcode::V_CVT_F64_F32:
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case Opcode::V_RCP_F64:
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case Opcode::V_MOV_B32:
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case Opcode::V_CVT_F32_F16:
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@@ -721,6 +726,7 @@ void ApplyDppModifier(Operand& operand, uint32_t modifier, uint32_t encoding) {
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void DecodeVop1Dpp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
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uint32_t opcode, uint32_t vdst, Instruction& inst) {
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if (inst.opcode == Opcode::V_CVT_F64_I32 || inst.opcode == Opcode::V_CVT_F32_F64 ||
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inst.opcode == Opcode::V_CVT_F64_F32 || inst.opcode == Opcode::V_CVT_F64_U32 ||
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inst.opcode == Opcode::V_RCP_F64) {
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SetUnsupported(inst, Family::VOP1, opcode, "FP64 instructions do not support DPP");
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return;
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