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shader: pack 16-bit lane pairs with one bit-field insert

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This commit is contained in:
nmzik
2026-10-21 22:46:04 +02:00
parent 4a1440197f
commit 10a852c2ac
3 changed files with 9 additions and 15 deletions
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src/graphics/shader/recompiler/frontend/translate/Convert.cpp
+4 -7
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@@ -166,16 +166,13 @@ void Translator::V_CVT_PK_U8_F32(const Decoder::Instruction& inst) {
}
void Translator::V_PACK_B32_F16(const Decoder::Instruction& inst) {
const auto low = Read16LaneBits(inst.src0, false);
const auto high =
ir.ShiftLeftLogical(Read16LaneBits(inst.src1, false), IR::U32(IR::Value(16u)));
WriteOperand(DestinationOperand(inst), ir.BitwiseOr(low, high));
WriteOperand(DestinationOperand(inst),
PackU16Lanes(Read16LaneBits(inst.src0, false), Read16LaneBits(inst.src1, false)));
}
IR::U32 Translator::PackU16Lanes(IR::U32 low, IR::U32 high) {
const auto mask = IR::U32(IR::Value(0xffffu));
return ir.BitwiseOr(ir.BitwiseAnd(low, mask),
ir.ShiftLeftLogical(ir.BitwiseAnd(high, mask), IR::U32(IR::Value(16u))));
return IR::U32(
ir.Emit(IR::ValueOpcode::BitFieldInsert, {low, high, IR::Value(16u), IR::Value(16u)}));
}
} // namespace Libs::Graphics::ShaderRecompiler::Frontend