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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-21 03:16:54 +02:00
shader: add distinct mesh shader type
This commit is contained in:
nmzik
@@ -1138,12 +1138,13 @@ IR::Program TranslateProgram(const Decoder::Program& decoded, const CFG::Graph&
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return entry_ir.ISub(lhs, minimum(lhs, rhs));
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};
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const auto local = builtin(IR::StageInputKind::LocalInvocationIndex);
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const auto primitive_chunk = entry_ir.IMul(builtin(IR::StageInputKind::WorkgroupId, 0),
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u32(mesh.primitives_per_group));
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const auto group = builtin(IR::StageInputKind::WorkgroupId, 0);
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const auto primitive_chunk = mesh.fast_launch ? group :
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entry_ir.IMul(group, u32(mesh.primitives_per_group));
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const auto step = u32(mesh.InputPrimitiveStep());
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const auto size = u32(mesh.InputPrimitiveSize());
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const auto chunk = entry_ir.IMul(primitive_chunk, step);
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const auto vertices =
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const auto chunk = mesh.fast_launch ? group : entry_ir.IMul(primitive_chunk, step);
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const auto vertices = mesh.fast_launch ? u32(mesh.vertices_per_group) :
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minimum(subtract_saturate(draw(0), chunk), u32(mesh.vertices_per_group));
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const auto primitives = entry_ir.Select(
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entry_ir.ULessThan(vertices, size), u32(0),
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@@ -1164,56 +1165,64 @@ IR::Program TranslateProgram(const Decoder::Program& decoded, const CFG::Graph&
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entry_ir.BitwiseOr(wave_info, entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(
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primitive_count, u32(8)),
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vertex_count)));
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// GS adjacency addresses local ES records in LDS. Fans retain the draw's
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// center in every subgroup; strip winding follows the global primitive.
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const auto vertex = entry_ir.IMul(local, step);
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auto first = vertex;
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auto second = u32(0);
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auto third = u32(0);
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if (mesh.InputPrimitiveSize() >= 2u) {
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second = entry_ir.IAdd(vertex, u32(1));
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if (mesh.fast_launch) {
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// Fast launch broadcasts the subgroup's base vertex and instance to every lane.
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(5), entry_ir.IAdd(draw(1), group));
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entry_ir.SetVectorReg(
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static_cast<IR::VectorReg>(6),
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entry_ir.IAdd(draw(2), builtin(IR::StageInputKind::WorkgroupId, 1)));
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} else {
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// GS adjacency addresses local ES records in LDS. Fans retain the draw's
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// center in every subgroup; strip winding follows the global primitive.
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const auto vertex = entry_ir.IMul(local, step);
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auto first = vertex;
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auto second = u32(0);
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auto third = u32(0);
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if (mesh.InputPrimitiveSize() >= 2u) {
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second = entry_ir.IAdd(vertex, u32(1));
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}
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if (mesh.InputPrimitiveSize() == 3u) {
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third = entry_ir.IAdd(vertex, u32(2));
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}
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auto input_vertex = entry_ir.IAdd(chunk, local);
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if (mesh.input_primitive == static_cast<uint32_t>(Prospero::PrimitiveType::kTriFan)) {
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first = u32(0);
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input_vertex = entry_ir.Select(entry_ir.IEqual(local, u32(0)), u32(0), input_vertex);
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} else if (mesh.input_primitive == static_cast<uint32_t>(Prospero::PrimitiveType::kTriStrip)) {
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const auto parity = entry_ir.BitwiseAnd(entry_ir.IAdd(primitive_chunk, local), u32(1));
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first = entry_ir.IAdd(first, parity);
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second = entry_ir.ISub(second, parity);
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}
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(0),
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entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(first, u32(2)),
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entry_ir.ShiftLeftLogical(second, u32(18))));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(1),
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entry_ir.ShiftLeftLogical(third, u32(2)));
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const auto index_bytes = draw(3);
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const auto indexed = entry_ir.INotEqual(index_bytes, u32(0));
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const auto index_low = draw(4);
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const auto byte_offset = entry_ir.IAdd(entry_ir.BitwiseAnd(index_low, u32(3)),
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entry_ir.IMul(input_vertex, index_bytes));
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const auto index_resource = entry_ir.Emit(
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IR::ValueOpcode::GetAddressResource,
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{entry_ir.BitwiseAnd(index_low, u32(~3u)), draw(5)});
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const auto memory_index = static_cast<uint32_t>(result.memory_info.size());
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result.memory_info.push_back({.kind = IR::ResourceKind::Global});
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const auto packed_index = entry_ir.Emit(
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IR::ValueOpcode::LoadAddressU32,
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{index_resource, entry_ir.BitwiseAnd(byte_offset, u32(~3u)), u32(0),
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entry_ir.LogicalAnd(indexed, entry_ir.ULessThan(local, vertices))},
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IR::MemoryFlags {.index = memory_index});
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const auto index = IR::U32(entry_ir.Emit(
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IR::ValueOpcode::BitFieldUExtract,
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{packed_index, entry_ir.IMul(entry_ir.BitwiseAnd(byte_offset, u32(3)), u32(8)),
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entry_ir.IMul(index_bytes, u32(8))}));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(5),
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entry_ir.IAdd(draw(1), entry_ir.Select(indexed, index, input_vertex)));
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entry_ir.SetVectorReg(
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static_cast<IR::VectorReg>(8),
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entry_ir.IAdd(draw(2), builtin(IR::StageInputKind::WorkgroupId, 1)));
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}
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if (mesh.InputPrimitiveSize() == 3u) {
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third = entry_ir.IAdd(vertex, u32(2));
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}
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auto input_vertex = entry_ir.IAdd(chunk, local);
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if (mesh.input_primitive == static_cast<uint32_t>(Prospero::PrimitiveType::kTriFan)) {
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first = u32(0);
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input_vertex = entry_ir.Select(entry_ir.IEqual(local, u32(0)), u32(0), input_vertex);
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} else if (mesh.input_primitive == static_cast<uint32_t>(Prospero::PrimitiveType::kTriStrip)) {
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const auto parity = entry_ir.BitwiseAnd(entry_ir.IAdd(primitive_chunk, local), u32(1));
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first = entry_ir.IAdd(first, parity);
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second = entry_ir.ISub(second, parity);
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}
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(0),
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entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(first, u32(2)),
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entry_ir.ShiftLeftLogical(second, u32(18))));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(1),
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entry_ir.ShiftLeftLogical(third, u32(2)));
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const auto index_bytes = draw(3);
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const auto indexed = entry_ir.INotEqual(index_bytes, u32(0));
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const auto index_low = draw(4);
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const auto byte_offset = entry_ir.IAdd(entry_ir.BitwiseAnd(index_low, u32(3)),
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entry_ir.IMul(input_vertex, index_bytes));
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const auto index_resource = entry_ir.Emit(
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IR::ValueOpcode::GetAddressResource,
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{entry_ir.BitwiseAnd(index_low, u32(~3u)), draw(5)});
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const auto memory_index = static_cast<uint32_t>(result.memory_info.size());
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result.memory_info.push_back({.kind = IR::ResourceKind::Global});
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const auto packed_index = entry_ir.Emit(
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IR::ValueOpcode::LoadAddressU32,
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{index_resource, entry_ir.BitwiseAnd(byte_offset, u32(~3u)), u32(0),
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entry_ir.LogicalAnd(indexed, entry_ir.ULessThan(local, vertices))},
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IR::MemoryFlags {.index = memory_index});
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const auto index = IR::U32(entry_ir.Emit(
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IR::ValueOpcode::BitFieldUExtract,
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{packed_index, entry_ir.IMul(entry_ir.BitwiseAnd(byte_offset, u32(3)), u32(8)),
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entry_ir.IMul(index_bytes, u32(8))}));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(5),
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entry_ir.IAdd(draw(1), entry_ir.Select(indexed, index, input_vertex)));
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entry_ir.SetVectorReg(
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static_cast<IR::VectorReg>(8),
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entry_ir.IAdd(draw(2), builtin(IR::StageInputKind::WorkgroupId, 1)));
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} else if (options.stage == ShaderType::Local) {
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entry_ir.SetScalarReg(static_cast<IR::ScalarReg>(3), IR::U32(IR::Value(64u)));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(2),
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