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graphics: implement RDNA2 alignbyte shader opcode

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This commit is contained in:
nmzik
2026-08-15 08:44:20 +02:00
parent 30d57bed06
commit 13e87a8e58
9 changed files with 54 additions and 0 deletions
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tests/ShaderRecompilerComputeTests.cpp
+28
View File
@@ -11584,6 +11584,28 @@ TestCase VectorBfeI32ArithmeticShiftMasksField() {
{O::VMovB32, O::VBfeI32, O::BufferStoreDword, O::SEndpgm}};
}
TestCase VectorAlignByteUsesFiveBitByteOffset() {
using O = ShaderOpcode;
std::vector<u32> code;
AppendVMovLiteral(&code, 0, 0x11223344u);
AppendVMovLiteral(&code, 1, 0x55667788u);
constexpr u32 offsets[] = {0, 1, 3, 4, 5, 7, 8, 31};
for (u32 i = 0; i < static_cast<u32>(std::size(offsets)); i++) {
AppendVMovU32(&code, 2, offsets[i]);
AppendVop3(&code, 0x14f, 10u + i, Vgpr(0), Vgpr(1), Vgpr(2));
AppendStoreVgpr(&code, 10u + i, i);
}
AppendEnd(&code);
return {"VectorAlignByteUsesFiveBitByteOffset",
code,
{},
{0x55667788u, 0x44556677u, 0x22334455u, 0x11223344u, 0x00112233u,
0x00000011u, 0u, 0u},
{O::VMovB32, O::VAlignbyteB32, O::BufferStoreDword, O::SEndpgm}};
}
TestCase VectorCarryAndBitCountOps() {
using O = ShaderOpcode;
@@ -16901,6 +16923,7 @@ std::vector<TestCase> MakeCases() {
AddCase(VectorShiftCountsMaskLowBits);
AddCase(VectorVop3IntegerOps);
AddCase(VectorBfeI32ArithmeticShiftMasksField);
AddCase(VectorAlignByteUsesFiveBitByteOffset);
AddCase(VectorCarryAndBitCountOps);
AddCase(VectorMbcntUsesThreadMask);
AddCase(VectorAddcWritesPerLaneCarryOut);
@@ -20241,6 +20264,11 @@ int main(int argc, char **argv) {
vulkan.CheckGpuCommandLane();
return 0;
}
if (argc == 2 && std::strcmp(argv[1], "--alignbyte-only") == 0) {
VulkanHarness vulkan;
RunCase(&vulkan, VectorAlignByteUsesFiveBitByteOffset());
return 0;
}
if (argc == 2 && std::strcmp(argv[1], "--context-state-only") == 0) {
VulkanHarness vulkan;
CheckPm4PolygonOffsetRegisters(vulkan.RuntimeRenderer());
tests/shaderCfgTests.cpp
+6
View File
@@ -1461,6 +1461,8 @@ void TestNewShaderRecompilerMoreAluFamilies() {
EncodeVop3Word1(5 + 256, 6 + 256, 7 + 256),
EncodeVop3Word0(0x14e, 50),
EncodeVop3Word1(5 + 256, 6 + 256, 129),
EncodeVop3Word0(0x14f, 115),
EncodeVop3Word1(5 + 256, 6 + 256, 129),
EncodeVop3Word0(0x36d, 51),
EncodeVop3Word1(5 + 256, 6 + 256, 7 + 256),
EncodeVop3Word0(0x169, 52),
@@ -1811,6 +1813,8 @@ void TestNewShaderRecompilerMoreAluFamilies() {
"new decoder did not decode VOP3 bitfield insert-select");
Check(Common::ContainsStr(result.decoded_dump, "v_alignbit_b32 v50"),
"new decoder did not decode VOP3 alignbit");
Check(Common::ContainsStr(result.decoded_dump, "v_alignbyte_b32 v115"),
"new decoder did not decode VOP3 alignbyte");
Check(Common::ContainsStr(result.decoded_dump, "v_add3_u32 v51"),
"new decoder did not decode VOP3 add3");
Check(Common::ContainsStr(result.decoded_dump, "v_mul_lo_u32 v52, v5, v6"),
@@ -2186,6 +2190,8 @@ void TestNewShaderRecompilerMoreAluFamilies() {
"VOP3 bitfield insert-select did not lower to IR");
Check(Common::ContainsStr(result.ir_dump, "AlignBitU32 v50"),
"VOP3 alignbit did not lower to IR");
Check(Common::ContainsStr(result.ir_dump, "AlignByteU32 v115"),
"VOP3 alignbyte did not lower to IR");
Check(Common::ContainsStr(result.ir_dump, "IAdd3U32 v51"),
"VOP3 add3 did not lower to IR");
Check(Common::ContainsStr(result.ir_dump, "IMulU32 v52, v5, v6"),