mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
Initial commit
This commit is contained in:
nmzik
@@ -0,0 +1,268 @@
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#ifndef GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_COMMAND_PROCESSOR_H
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#define GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_COMMAND_PROCESSOR_H
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#include "common/assert.h"
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#include "common/threads.h"
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#include "graphics/guest_gpu/hardwareContext.h"
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#include "graphics/host_gpu/renderer/render.h"
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#include "graphics/host_gpu/renderer/renderContext.h"
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#include <array>
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#include <cstdint>
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namespace Libs::Graphics {
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class CommandProcessorGuestAccessScope;
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inline constexpr uint32_t AcquireGcrGl2Writeback = 1u << 15u;
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bool TestWaitRegMemValue(uint64_t value, uint64_t ref, uint64_t mask, uint32_t func);
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class CommandScheduler {
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public:
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static constexpr int BuffersNum = 8;
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void SetQueue(int queue) { m_queue = queue; }
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int Queue() const { return m_queue; }
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bool Active() const { return m_current >= 0 && m_current < BuffersNum; }
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void CheckActive() const { EXIT_IF(!Active()); }
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CommandBuffer* Current() const {
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CheckActive();
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EXIT_IF(m_buffers[m_current] == nullptr);
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return m_buffers[m_current];
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}
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void Init() {
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if (m_current >= 0) {
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return;
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}
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for (auto& buf: m_buffers) {
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EXIT_IF(buf != nullptr);
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buf = new CommandBuffer(m_queue);
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}
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m_current = 0;
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Current()->Begin();
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}
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void Flush() {
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SubmitCurrent();
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BeginNext();
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}
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CommandBuffer* FlushAndGetSubmitted() {
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auto* submitted = SubmitCurrent();
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BeginNext();
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return submitted;
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}
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void CopyBuffers(std::array<CommandBuffer*, BuffersNum>* out) const {
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EXIT_IF(out == nullptr);
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for (int i = 0; i < BuffersNum; i++) {
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auto* buf = m_buffers[i];
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EXIT_IF(buf == nullptr);
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(*out)[i] = buf;
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}
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}
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void WaitAll() {
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for (auto* buf: m_buffers) {
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EXIT_IF(buf == nullptr);
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buf->WaitForFenceAndReset();
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}
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}
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private:
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CommandBuffer* SubmitCurrent() {
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auto* submitted = Current();
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submitted->End();
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submitted->Execute();
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return submitted;
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}
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void BeginNext() {
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m_current = (m_current + 1) % BuffersNum;
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Current()->WaitForFenceAndReset();
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Current()->Begin();
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}
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CommandBuffer* m_buffers[BuffersNum] = {};
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int m_current = -1;
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int m_queue = -1;
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};
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class CommandProcessor {
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public:
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struct FlipInfo {
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int handle = 0;
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int index = 0;
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int flip_mode = 0;
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int64_t flip_arg = 0;
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};
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CommandProcessor() = default;
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~CommandProcessor() { KYTY_NOT_IMPLEMENTED; }
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KYTY_CLASS_NO_COPY(CommandProcessor);
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void Reset();
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void BufferInit();
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void BufferFlush();
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void BufferFlushAndWait();
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void BufferWait();
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[[nodiscard]] int BeginReadbackTransaction(bool mutex_preowned) {
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if (!mutex_preowned) {
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m_mutex.Lock();
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}
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m_scheduler.Flush();
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m_scheduler.WaitAll();
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return m_scheduler.Queue();
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}
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void EndReadbackTransaction(bool mutex_preowned) {
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if (!mutex_preowned) {
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m_mutex.Unlock();
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}
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}
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void RunLock() { m_run_mutex.Lock(); }
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void RunUnlock() { m_run_mutex.Unlock(); }
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HW::Context* GetCtx() { return &m_ctx; }
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HW::UserConfig* GetUcfg() { return &m_ucfg; }
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HW::Shader* GetShCtx() { return &m_sh_ctx; }
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void SetIndexType(uint32_t index_type_and_size);
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void SetIndexBaseAddress(uint64_t index_base_addr);
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void SetIndexBufferSize(uint32_t index_buffer_size);
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void SetDrawIndirectArgsBaseAddress(uint64_t draw_indirect_args_base_addr);
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void SetDispatchIndirectArgsBaseAddress(uint64_t dispatch_indirect_args_base_addr);
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void SetNumInstances(uint32_t num_instances);
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void DrawIndex(uint32_t index_count, const void* index_addr, uint32_t flags, uint32_t type,
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uint32_t instance_count = 0, const void* object_ids = nullptr,
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uint32_t render_target_slice_offset = 0, int32_t vertex_offset_add = 0,
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uint32_t first_instance = 0);
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void DrawIndexOffset(uint32_t index_offset, uint32_t index_count, uint32_t flags);
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void DrawIndexAuto(uint32_t index_count, uint32_t flags,
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uint32_t render_target_slice_offset = 0, uint32_t instance_count = 1,
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uint32_t first_vertex = 0, uint32_t first_instance = 0);
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void DrawIndirect(uint32_t data_offset, uint32_t draw_initiator, bool indexed);
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void DrawIndirectMulti(uint32_t data_offset, uint32_t max_count_or_count,
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const volatile uint32_t* count_addr, uint32_t stride_in_bytes,
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uint32_t draw_initiator, bool indexed);
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void WriteAtEndOfPipe32(uint32_t cache_policy, uint32_t event_write_dest,
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uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t event_write_source, void* dst_gpu_addr, uint32_t value,
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uint32_t interrupt_selector, uint32_t interrupt_context_id = 0);
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void WriteAtEndOfPipe64(uint32_t cache_policy, uint32_t event_write_dest,
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uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t event_write_source, void* dst_gpu_addr, uint64_t value,
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uint32_t interrupt_selector, uint32_t interrupt_context_id = 0);
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void Flip();
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void Flip(void* dst_gpu_addr, uint32_t value);
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void FlipWithInterrupt(uint32_t eop_event_type, uint32_t cache_action, void* dst_gpu_addr,
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uint32_t value);
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void SynchronizeGpu();
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void SynchronizeGpuRange(uint64_t vaddr, uint64_t size);
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void MemoryBarrier();
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void TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id);
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void RenderTextureBarrier(uint64_t vaddr, uint64_t size);
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void DepthStencilBarrier(uint64_t vaddr, uint64_t size);
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void DispatchDirect(uint32_t thread_group_x, uint32_t thread_group_y, uint32_t thread_group_z,
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uint32_t mode);
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void DispatchIndirect(uint32_t data_offset, uint32_t mode);
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void WaitFlipDone(uint32_t video_out_handle, uint32_t display_buffer_index);
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void TriggerEvent(uint32_t event_type, uint32_t event_index);
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void SetUserDataMarker(HW::UserSgprType type) { m_user_data_marker = type; }
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[[nodiscard]] HW::UserSgprType GetUserDataMarker() const { return m_user_data_marker; }
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void SetEmbeddedDataMarker(const uint32_t* buffer, uint32_t num_dw, uint32_t align) {}
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void PushMarker(const char* str) {}
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void PopMarker() {}
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void PrefetchL2(void* addr, uint32_t size) {}
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void ClearGds(uint64_t dw_offset, uint32_t dw_num, uint32_t clear_value);
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void ReadGds(uint32_t* dst, uint32_t dw_offset, uint32_t dw_size);
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void ResetDeCe();
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void WaitCe();
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void WaitDeDiff(uint32_t diff);
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void IncremenetDe();
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void IncremenetCe();
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void WriteConstRam(uint32_t offset, const uint32_t* src, uint32_t dw_num);
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void DumpConstRam(uint32_t* dst, uint32_t offset, uint32_t dw_num);
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template <typename T>
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void WaitRegMem(uint32_t func, const T* addr, T ref, T mask, uint32_t poll, uint32_t wait_op);
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void WriteData(uint32_t* dst, const uint32_t* src, uint32_t dw_num, uint32_t write_control);
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void DmaData(uint8_t engine, uint8_t dst_sel, uint8_t dst_cache_policy,
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uint64_t dst_address_or_offset, uint8_t src_sel, uint8_t src_cache_policy,
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uint64_t src_address_or_offset_or_immediate, uint32_t num_bytes,
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uint8_t wait_for_previous, uint8_t write_confirm, uint8_t block_engine);
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void SetPredication(uint32_t condition, uint32_t op, uint32_t wait_op,
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const volatile void* address, uint32_t count_in_dwords);
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[[nodiscard]] bool ShouldSkipPredicatedPackets() const { return m_predicate_skip; }
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void Run(uint32_t* data, uint32_t num_dw);
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void SetQueue(int queue) { m_scheduler.SetQueue(queue); }
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[[nodiscard]] int GetQueue() const { return m_scheduler.Queue(); }
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[[nodiscard]] const FlipInfo& GetFlip() const { return m_flip; }
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void SetFlip(const FlipInfo& flip) { m_flip = flip; }
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[[nodiscard]] uint64_t GetSubmitId() const { return m_submit_id; }
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void SetSubmitId(uint64_t submit_id) { m_submit_id = submit_id; }
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private:
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friend class CommandProcessorGuestAccessScope;
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struct Counter {
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Common::Mutex mutex;
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Common::CondVar cond_var;
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uint32_t value = 0;
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};
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template <typename T>
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void WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_write_dest, uint32_t eop_event_type,
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uint32_t cache_action, uint32_t event_index, uint32_t event_write_source,
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void* dst_gpu_addr, T value, uint32_t interrupt_selector,
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uint32_t interrupt_context_id);
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CommandBuffer* CurrentBuffer() { return m_scheduler.Current(); }
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void CheckBuffer() const { m_scheduler.CheckActive(); }
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GpuResourceManager* GetGpuResources() const {
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EXIT_IF(g_render_ctx == nullptr);
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return g_render_ctx->GetGpuResources();
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}
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HW::Context m_ctx;
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HW::UserConfig m_ucfg;
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HW::Shader m_sh_ctx;
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HW::UserSgprType m_user_data_marker = HW::UserSgprType::Unknown;
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uint32_t m_index_type_and_size = 0;
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uint32_t m_index_buffer_size = 0;
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uint64_t m_index_base_addr = 0;
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uint64_t m_draw_indirect_args_base_addr = 0;
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uint64_t m_dispatch_indirect_args_base_addr = 0;
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uint32_t m_num_instances = 1;
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Common::Mutex m_mutex;
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Common::Mutex m_run_mutex;
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CommandScheduler m_scheduler;
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Counter m_de_counter;
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Counter m_ce_counter;
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uint32_t m_const_ram[0x3000] = {0};
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FlipInfo m_flip;
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uint64_t m_submit_id = 0;
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bool m_predicate_skip = false;
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};
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} // namespace Libs::Graphics
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#endif // GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_COMMAND_PROCESSOR_H
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@@ -0,0 +1,260 @@
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#include "graphics/guest_gpu/command_processor/pm4Dispatch.h"
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namespace Libs::Graphics {
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hw_ctx_parser_func_t g_hw_ctx_func[Pm4::CX_NUM] = {};
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hw_ctx_indirect_func_t g_hw_ctx_indirect_func[Pm4::CX_NUM] = {};
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hw_sh_parser_func_t g_hw_sh_func[Pm4::SH_NUM] = {};
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hw_sh_indirect_func_t g_hw_sh_indirect_func[Pm4::SH_NUM] = {};
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hw_uc_parser_func_t g_hw_uc_func[Pm4::UC_NUM] = {};
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hw_uc_indirect_func_t g_hw_uc_indirect_func[Pm4::UC_NUM] = {};
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cp_op_parser_func_t g_cp_op_func[256] = {};
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cp_op_parser_func_t g_cp_op_custom_func[Pm4::R_NUM] = {};
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void GraphicsInitJmpTables() {
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for (auto& func: g_hw_ctx_func) {
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func = nullptr;
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}
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g_hw_ctx_func[Pm4::DB_RENDER_CONTROL] = HwCtxSetRenderControl;
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g_hw_ctx_func[Pm4::DB_COUNT_CONTROL] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::DB_RENDER_OVERRIDE] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::DB_RENDER_OVERRIDE2] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::DB_DFSM_CONTROL] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::DB_RMI_L2_CACHE_CONTROL] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::CB_RMI_GL2_CACHE_CONTROL] = HwCtxSetDepthMetadataRegisters;
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g_hw_ctx_func[Pm4::TA_BC_BASE_ADDR] = HwCtxSetBorderColorTableAddr;
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g_hw_ctx_func[Pm4::TA_BC_BASE_ADDR_HI] = HwCtxSetBorderColorTableAddr;
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g_hw_ctx_func[Pm4::DB_STENCIL_CLEAR] = HwCtxSetStencilClear;
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g_hw_ctx_func[Pm4::DB_DEPTH_CLEAR] = HwCtxSetDepthClear;
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g_hw_ctx_func[Pm4::PA_SC_SCREEN_SCISSOR_TL] = HwCtxSetScreenScissor;
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g_hw_ctx_func[Pm4::DB_Z_INFO] = HwCtxSetDepthRenderTarget;
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g_hw_ctx_func[Pm4::DB_STENCIL_INFO] = HwCtxSetStencilInfo;
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g_hw_ctx_func[Pm4::DB_HTILE_SURFACE] = HwCtxSetDepthHtileSurface;
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g_hw_ctx_func[Pm4::PA_SU_HARDWARE_SCREEN_OFFSET] = HwCtxSetHardwareScreenOffset;
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g_hw_ctx_func[Pm4::PA_SC_WINDOW_OFFSET] = HwCtxSetWindowOffset;
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g_hw_ctx_func[Pm4::PA_SC_WINDOW_SCISSOR_TL] = HwCtxSetWindowScissor;
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for (auto cmd_offset = Pm4::PA_SC_CLIPRECT_RULE; cmd_offset < Pm4::PA_SC_CLIPRECT_0_TL + 8u;
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cmd_offset++) {
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g_hw_ctx_func[cmd_offset] = HwCtxSetClipRect;
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}
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g_hw_ctx_func[Pm4::CB_TARGET_MASK] = HwCtxSetRenderTargetMask;
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g_hw_ctx_func[Pm4::PA_SC_GENERIC_SCISSOR_TL] = HwCtxSetGenericScissor;
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g_hw_ctx_func[Pm4::CB_BLEND_RED] = HwCtxSetBlendColor;
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g_hw_ctx_func[Pm4::CB_DCC_CONTROL] = HwCtxSetCbDccControl;
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g_hw_ctx_func[Pm4::DB_STENCIL_CONTROL] = HwCtxSetStencilControl;
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g_hw_ctx_func[Pm4::DB_STENCILREFMASK] = HwCtxSetStencilMask;
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g_hw_ctx_func[Pm4::SPI_PS_INPUT_CNTL_0] = HwCtxSetPsInput;
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g_hw_ctx_func[Pm4::SPI_TMPRING_SIZE] = HwCtxSetSpiTmpringSize;
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g_hw_ctx_func[Pm4::DB_DEPTH_CONTROL] = HwCtxSetDepthControl;
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g_hw_ctx_func[Pm4::DB_EQAA] = HwCtxSetEqaaControl;
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g_hw_ctx_func[Pm4::CB_COLOR_CONTROL] = HwCtxSetColorControl;
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g_hw_ctx_func[Pm4::DB_DEPTH_BOUNDS_MIN] = HwCtxSetDepthBounds;
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g_hw_ctx_func[Pm4::DB_DEPTH_BOUNDS_MAX] = HwCtxSetDepthBounds;
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g_hw_ctx_func[Pm4::PA_SU_POINT_SIZE] = HwCtxSetPointState;
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g_hw_ctx_func[Pm4::PA_SU_POINT_MINMAX] = HwCtxSetPointState;
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g_hw_ctx_func[Pm4::PA_CL_CLIP_CNTL] = HwCtxSetClipControl;
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g_hw_ctx_func[Pm4::PA_SU_SC_MODE_CNTL] = HwCtxSetModeControl;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_DB_FMT_CNTL] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_CLAMP] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_FRONT_SCALE] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_FRONT_OFFSET] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_BACK_SCALE] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_SU_POLY_OFFSET_BACK_OFFSET] = HwCtxSetPolyOffsetRegisters;
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g_hw_ctx_func[Pm4::PA_CL_VTE_CNTL] = HwCtxSetViewportTransformControl;
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g_hw_ctx_func[Pm4::PA_SU_LINE_CNTL] = HwCtxSetLineControl;
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g_hw_ctx_func[Pm4::PA_SC_FOV_WINDOW_LR] = HwCtxSetFovWindow;
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g_hw_ctx_func[Pm4::PA_SC_FOV_WINDOW_TB] = HwCtxSetFovWindow;
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g_hw_ctx_func[Pm4::PA_SC_MODE_CNTL_0] = HwCtxSetScanModeControl;
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g_hw_ctx_func[Pm4::PA_SC_MODE_CNTL_1] = HwCtxSetScanModeControl1;
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g_hw_ctx_func[Pm4::PA_SC_AA_CONFIG] = HwCtxSetAaConfig;
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for (auto cmd_offset = Pm4::PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0;
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cmd_offset < Pm4::PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 + 16; cmd_offset++) {
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g_hw_ctx_func[cmd_offset] = HwCtxSetAaSampleControl;
|
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}
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g_hw_ctx_func[Pm4::PA_SC_CENTROID_PRIORITY_0] = HwCtxSetCentroidPriority;
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g_hw_ctx_func[Pm4::PA_SC_CENTROID_PRIORITY_1] = HwCtxSetCentroidPriority;
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g_hw_ctx_func[Pm4::PA_SC_AA_MASK_X0Y0_X1Y0] = HwCtxSetAaMask;
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g_hw_ctx_func[Pm4::PA_SC_AA_MASK_X0Y1_X1Y1] = HwCtxSetAaMask;
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g_hw_ctx_func[Pm4::PA_SU_VTX_CNTL] = HwCtxSetVtxControl;
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||||
g_hw_ctx_func[Pm4::PS_SHADER_SAMPLE_EXCLUSION_MASK] = HwCtxSetAaMask;
|
||||
g_hw_ctx_func[Pm4::PA_SC_BINNER_CNTL_0] = HwCtxSetPaScExtendedControl;
|
||||
g_hw_ctx_func[Pm4::PA_SC_BINNER_CNTL_1] = HwCtxSetPaScExtendedControl;
|
||||
g_hw_ctx_func[Pm4::PA_SC_CONSERVATIVE_RASTERIZATION_CNTL] = HwCtxSetPaScExtendedControl;
|
||||
g_hw_ctx_func[Pm4::PA_SC_NGG_MODE_CNTL] = HwCtxSetPaScExtendedControl;
|
||||
g_hw_ctx_func[Pm4::DB_ALPHA_TO_MASK] = HwCtxSetAlphaToMask;
|
||||
g_hw_ctx_func[Pm4::VGT_DRAW_PAYLOAD_CNTL] = HwCtxSetDrawPayloadControl;
|
||||
g_hw_ctx_func[Pm4::VGT_PRIMITIVEID_RESET] = HwCtxSetPrimitiveIdReset;
|
||||
g_hw_ctx_func[Pm4::PA_CL_OBJPRIM_ID_CNTL] = HwCtxSetObjprimIdControl;
|
||||
g_hw_ctx_func[Pm4::VGT_SHADER_STAGES_EN] = HwCtxSetShaderStages;
|
||||
g_hw_ctx_func[Pm4::PA_CL_GB_VERT_CLIP_ADJ] = HwCtxSetGuardBands;
|
||||
|
||||
for (uint32_t slot = 0; slot < 8; slot++) {
|
||||
g_hw_ctx_func[Pm4::CB_COLOR0_BASE + slot * 15] = HwCtxSetRenderTarget;
|
||||
g_hw_ctx_func[Pm4::CB_COLOR0_INFO + slot * 15] = HwCtxSetColorInfo;
|
||||
|
||||
g_hw_ctx_func[Pm4::CB_BLEND0_CONTROL + slot * 1] = HwCtxSetBlendControl;
|
||||
}
|
||||
|
||||
for (uint32_t viewport = 0; viewport < 16; viewport++) {
|
||||
g_hw_ctx_func[Pm4::PA_SC_VPORT_SCISSOR_0_TL + viewport * 2] = HwCtxSetViewportScissor;
|
||||
g_hw_ctx_func[Pm4::PA_SC_VPORT_SCISSOR_0_BR + viewport * 2] = HwCtxSetViewportScissor;
|
||||
g_hw_ctx_func[Pm4::PA_SC_VPORT_ZMIN_0 + viewport * 2] = HwCtxSetViewportZ;
|
||||
g_hw_ctx_func[Pm4::PA_SC_VPORT_ZMAX_0 + viewport * 2] = HwCtxSetViewportZ;
|
||||
for (uint32_t field = 0; field < 6; field++) {
|
||||
g_hw_ctx_func[Pm4::PA_CL_VPORT_XSCALE + viewport * 6 + field] =
|
||||
HwCtxSetViewportScaleOffset;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto& func: g_hw_sh_func) {
|
||||
func = nullptr;
|
||||
}
|
||||
|
||||
for (uint32_t slot = 0; slot < 32; slot++) {
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_PS_0 + slot * 1] = HwShSetPsUserSgpr;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_GS_0 + slot * 1] = HwShSetGsUserSgpr;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_HS_0 + slot * 1] = HwShSetHsUserSgpr;
|
||||
}
|
||||
for (uint32_t slot = 0; slot < 16; slot++) {
|
||||
g_hw_sh_func[Pm4::COMPUTE_USER_DATA_0 + slot * 1] = HwShSetCsUserSgpr;
|
||||
}
|
||||
|
||||
for (uint32_t slot = 0; slot < 4; slot++) {
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_PS_0 + slot] = HwShSetPsUserAccumSgpr;
|
||||
}
|
||||
|
||||
for (uint32_t slot = 0; slot < 4; slot++) {
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_ESGS_0 + slot] = HwShSetGsUserAccumSgpr;
|
||||
}
|
||||
for (uint32_t slot = 0; slot < 4; slot++) {
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_LSHS_0 + slot] = HwShSetHsUserAccumSgpr;
|
||||
}
|
||||
|
||||
for (uint32_t slot = 0; Pm4::COMPUTE_USER_ACCUM_0 + slot < Pm4::COMPUTE_USER_DATA_0; slot++) {
|
||||
g_hw_sh_func[Pm4::COMPUTE_USER_ACCUM_0 + slot] = HwShSetCsUserAccumSgpr;
|
||||
}
|
||||
g_hw_sh_func[Pm4::COMPUTE_PGM_LO] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_PGM_HI] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_TBA_LO] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_TBA_HI] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_TMA_LO] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_TMA_HI] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC1] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC2] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_START_X] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_START_Y] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_START_Z] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_NUM_THREAD_X] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_NUM_THREAD_Y] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_NUM_THREAD_Z] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_RESOURCE_LIMITS] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE0] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE1] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_TMPRING_SIZE] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE2] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE3] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC3] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_SHADER_CHKSUM] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::COMPUTE_DISPATCH_TUNNEL] = HwShSetCsRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_TBA_LO_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_TMA_LO_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_TMA_HI_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_PS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_GS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_GS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_GS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_GS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_ESGS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_HS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_HS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_HS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_HS] = HwShIgnoreRegisters;
|
||||
g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_LSHS] = HwShIgnoreRegisters;
|
||||
|
||||
for (auto& func: g_hw_uc_func) {
|
||||
func = nullptr;
|
||||
}
|
||||
|
||||
g_hw_uc_func[Pm4::VGT_PRIMITIVE_TYPE] = HwUcSetPrimitiveType;
|
||||
g_hw_uc_func[Pm4::VGT_INDEX_TYPE] = HwUcSetIndexType;
|
||||
g_hw_uc_func[Pm4::VGT_OBJECT_ID] = HwUcSetObjectId;
|
||||
g_hw_uc_func[Pm4::TEXTURE_GRADIENT_FACTORS] = HwUcSetTextureGradientFactors;
|
||||
g_hw_uc_func[Pm4::IA_MULTI_VGT_PARAM] = HwUcSetIaMultiVgtParam;
|
||||
g_hw_uc_func[Pm4::GE_MULTI_PRIM_IB_RESET_EN] = HwUcSetMultiPrimIbReset;
|
||||
g_hw_uc_func[Pm4::TA_CS_BC_BASE_ADDR] = HwUcSetBorderColorTableAddr;
|
||||
g_hw_uc_func[Pm4::TA_CS_BC_BASE_ADDR_HI] = HwUcSetBorderColorTableAddr;
|
||||
g_hw_uc_func[Pm4::GE_INDX_OFFSET] = HwUcSetGeIndexOffset;
|
||||
g_hw_uc_func[Pm4::GDS_OA_CNTL] = HwUcSetGdsOaRegisters;
|
||||
g_hw_uc_func[Pm4::GDS_OA_COUNTER] = HwUcSetGdsOaRegisters;
|
||||
g_hw_uc_func[Pm4::GDS_OA_ADDRESS] = HwUcSetGdsOaRegisters;
|
||||
|
||||
for (auto& func: g_cp_op_func) {
|
||||
func = nullptr;
|
||||
}
|
||||
|
||||
g_cp_op_func[Pm4::IT_NOP] = CpOpNop;
|
||||
g_cp_op_func[Pm4::IT_SET_BASE] = CpOpSetBase;
|
||||
g_cp_op_func[Pm4::IT_CLEAR_STATE] = CpOpClearState;
|
||||
g_cp_op_func[Pm4::IT_INDEX_BASE] = CpOpIndexBase;
|
||||
g_cp_op_func[Pm4::IT_INDEX_BUFFER_SIZE] = CpOpIndexBufferSize;
|
||||
g_cp_op_func[Pm4::IT_DISPATCH_DIRECT] = CpOpDispatchDirect;
|
||||
g_cp_op_func[Pm4::IT_DISPATCH_INDIRECT] = CpOpDispatchIndirect;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDIRECT] = CpOpDrawIndirect;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDEX_INDIRECT] = CpOpDrawIndirect;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDIRECT_MULTI] = CpOpDrawIndirectMulti;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDEX_INDIRECT_MULTI] = CpOpDrawIndirectMulti;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDEX_2] = CpOpDrawIndex;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDEX_OFFSET_2] = CpOpDrawIndexOffset;
|
||||
g_cp_op_func[Pm4::IT_DISPATCH_DRAW_PREAMBLE] = CpOpDrawIndex;
|
||||
g_cp_op_func[Pm4::IT_PFP_SYNC_ME] = CpOpPfpSyncMe;
|
||||
g_cp_op_func[Pm4::IT_INDEX_TYPE] = CpOpIndexType;
|
||||
g_cp_op_func[Pm4::IT_NUM_INSTANCES] = CpOpNumInstances;
|
||||
g_cp_op_func[Pm4::IT_DRAW_INDEX_AUTO] = CpOpDrawIndexAuto;
|
||||
g_cp_op_func[Pm4::IT_COND_EXEC] = CpOpCondExec;
|
||||
g_cp_op_func[Pm4::IT_SET_PREDICATION] = CpOpSetPredication;
|
||||
g_cp_op_func[Pm4::IT_WRITE_DATA] = CpOpWriteData;
|
||||
g_cp_op_func[Pm4::IT_INDIRECT_BUFFER] = CpOpIndirectBuffer;
|
||||
g_cp_op_func[Pm4::IT_COPY_DATA] = CpOpCopyData;
|
||||
g_cp_op_func[Pm4::IT_EVENT_WRITE] = CpOpEventWrite;
|
||||
g_cp_op_func[Pm4::IT_EVENT_WRITE_EOP] = CpOpEventWriteEop;
|
||||
g_cp_op_func[Pm4::IT_EVENT_WRITE_EOS] = CpOpEventWriteEos;
|
||||
g_cp_op_func[Pm4::IT_DMA_DATA] = CpOpDmaData;
|
||||
g_cp_op_func[Pm4::IT_ACQUIRE_MEM] = CpOpAcquireMem;
|
||||
g_cp_op_func[Pm4::IT_SET_CONTEXT_REG] = CpOpSetContextReg;
|
||||
g_cp_op_func[Pm4::IT_SET_SH_REG] = CpOpSetShaderReg;
|
||||
g_cp_op_func[Pm4::IT_SET_UCONFIG_REG] = CpOpSetUconfigReg;
|
||||
g_cp_op_func[Pm4::IT_SET_UCONFIG_REG_INDEX] = CpOpSetUconfigReg;
|
||||
g_cp_op_func[Pm4::IT_SET_CONTEXT_REG_INDIRECT] = CpOpIndirectCxRegs;
|
||||
g_cp_op_func[Pm4::IT_SET_SH_REG_INDIRECT] = CpOpIndirectShRegs;
|
||||
g_cp_op_func[Pm4::IT_SET_UCONFIG_REG_INDIRECT] = CpOpIndirectUcRegs;
|
||||
g_cp_op_func[Pm4::IT_WRITE_CONST_RAM] = CpOpWriteConstRam;
|
||||
g_cp_op_func[Pm4::IT_DUMP_CONST_RAM] = CpOpDumpConstRam;
|
||||
g_cp_op_func[Pm4::IT_INCREMENT_CE_COUNTER] = CpOpIncrementCeCounter;
|
||||
g_cp_op_func[Pm4::IT_INCREMENT_DE_COUNTER] = CpOpIncrementDeCounter;
|
||||
g_cp_op_func[Pm4::IT_WAIT_ON_CE_COUNTER] = CpOpWaitOnCeCounter;
|
||||
g_cp_op_func[Pm4::IT_WAIT_ON_DE_COUNTER_DIFF] = CpOpWaitOnDeCounterDiff;
|
||||
g_cp_op_func[Pm4::IT_GET_LOD_STATS] = CpOpGetLodStats;
|
||||
|
||||
for (auto& func: g_cp_op_custom_func) {
|
||||
func = nullptr;
|
||||
}
|
||||
|
||||
g_cp_op_custom_func[Pm4::R_DISPATCH_RESET] = CpOpDispatchReset;
|
||||
g_cp_op_custom_func[Pm4::R_WAIT_MEM_32] = CpOpWaitRegMem32;
|
||||
g_cp_op_custom_func[Pm4::R_WAIT_FLIP_DONE] = CpOpWaitFlipDone;
|
||||
g_cp_op_custom_func[Pm4::R_PUSH_MARKER] = CpOpPushMarker;
|
||||
g_cp_op_custom_func[Pm4::R_POP_MARKER] = CpOpPopMarker;
|
||||
g_cp_op_custom_func[Pm4::R_ACQUIRE_MEM] = CpOpAcquireMem;
|
||||
g_cp_op_custom_func[Pm4::R_WAIT_MEM_64] = CpOpWaitRegMem64;
|
||||
g_cp_op_custom_func[Pm4::R_FLIP] = CpOpFlip;
|
||||
g_cp_op_custom_func[Pm4::R_RELEASE_MEM] = CpOpReleaseMem;
|
||||
|
||||
GraphicsInitJmpTablesCxIndirect();
|
||||
GraphicsInitJmpTablesShIndirect();
|
||||
GraphicsInitJmpTablesUcIndirect();
|
||||
}
|
||||
|
||||
} // namespace Libs::Graphics
|
||||
@@ -0,0 +1,171 @@
|
||||
#ifndef GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_PM4_DISPATCH_H
|
||||
#define GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_PM4_DISPATCH_H
|
||||
|
||||
#include "graphics/guest_gpu/pm4.h"
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
namespace Libs::Graphics {
|
||||
|
||||
class CommandProcessor;
|
||||
|
||||
using hw_ctx_parser_func_t = uint32_t (*)(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
using hw_uc_parser_func_t = uint32_t (*)(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
using hw_sh_parser_func_t = uint32_t (*)(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
using cp_op_parser_func_t = uint32_t (*)(CommandProcessor*, uint32_t, const uint32_t*, uint32_t,
|
||||
uint32_t);
|
||||
using hw_ctx_indirect_func_t = void (*)(CommandProcessor*, uint32_t, uint32_t);
|
||||
using hw_uc_indirect_func_t = void (*)(CommandProcessor*, uint32_t, uint32_t);
|
||||
using hw_sh_indirect_func_t = void (*)(CommandProcessor*, uint32_t, uint32_t);
|
||||
|
||||
extern hw_ctx_parser_func_t g_hw_ctx_func[Pm4::CX_NUM];
|
||||
extern hw_ctx_indirect_func_t g_hw_ctx_indirect_func[Pm4::CX_NUM];
|
||||
extern hw_sh_parser_func_t g_hw_sh_func[Pm4::SH_NUM];
|
||||
extern hw_sh_indirect_func_t g_hw_sh_indirect_func[Pm4::SH_NUM];
|
||||
extern hw_uc_parser_func_t g_hw_uc_func[Pm4::UC_NUM];
|
||||
extern hw_uc_indirect_func_t g_hw_uc_indirect_func[Pm4::UC_NUM];
|
||||
extern cp_op_parser_func_t g_cp_op_func[256];
|
||||
extern cp_op_parser_func_t g_cp_op_custom_func[Pm4::R_NUM];
|
||||
|
||||
void GraphicsInitJmpTables();
|
||||
void GraphicsInitJmpTablesCxIndirect();
|
||||
void GraphicsInitJmpTablesShIndirect();
|
||||
void GraphicsInitJmpTablesUcIndirect();
|
||||
|
||||
uint32_t HwCtxSetRenderControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthMetadataRegisters(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetBorderColorTableAddr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetStencilClear(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthClear(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetScreenScissor(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthRenderTarget(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetStencilInfo(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthHtileSurface(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetHardwareScreenOffset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetWindowOffset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetWindowScissor(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetClipRect(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetRenderTargetMask(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetGenericScissor(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetBlendColor(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetCbDccControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetStencilControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetStencilMask(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetPsInput(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetSpiTmpringSize(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetEqaaControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetColorControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDepthBounds(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetPointState(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetClipControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetModeControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetPolyOffsetRegisters(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetViewportTransformControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetLineControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetFovWindow(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetScanModeControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetScanModeControl1(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetAaConfig(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetAaSampleControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetCentroidPriority(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetAaMask(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetVtxControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetPaScExtendedControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetAlphaToMask(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetDrawPayloadControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwCtxSetPrimitiveIdReset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetObjprimIdControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetShaderStages(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetGuardBands(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetRenderTarget(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetColorInfo(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetBlendControl(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetViewportScissor(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetViewportZ(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwCtxSetViewportScaleOffset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwShSetPsUserSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetGsUserSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetHsUserSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetCsUserSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetPsUserAccumSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetGsUserAccumSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetHsUserAccumSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetCsUserAccumSgpr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShSetCsRegisters(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwShIgnoreRegisters(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetPrimitiveType(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetIndexType(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetObjectId(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetTextureGradientFactors(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwUcSetIaMultiVgtParam(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetMultiPrimIbReset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetBorderColorTableAddr(CommandProcessor*, uint32_t, uint32_t, const uint32_t*,
|
||||
uint32_t);
|
||||
uint32_t HwUcSetGeIndexOffset(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
uint32_t HwUcSetGdsOaRegisters(CommandProcessor*, uint32_t, uint32_t, const uint32_t*, uint32_t);
|
||||
|
||||
uint32_t CpOpNop(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpSetBase(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpClearState(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndexBase(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndexBufferSize(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDispatchDirect(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDispatchIndirect(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDrawIndirect(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDrawIndirectMulti(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDrawIndex(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDrawIndexOffset(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpPfpSyncMe(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndexType(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpNumInstances(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDrawIndexAuto(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpCondExec(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpSetPredication(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWriteData(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndirectBuffer(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpCopyData(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpEventWrite(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpEventWriteEop(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpEventWriteEos(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDmaData(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpAcquireMem(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpSetContextReg(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpSetShaderReg(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpSetUconfigReg(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndirectCxRegs(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndirectShRegs(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIndirectUcRegs(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWriteConstRam(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDumpConstRam(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIncrementCeCounter(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpIncrementDeCounter(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWaitOnCeCounter(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWaitOnDeCounterDiff(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpGetLodStats(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpDispatchReset(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWaitRegMem32(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWaitFlipDone(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpPushMarker(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpPopMarker(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpWaitRegMem64(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpFlip(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
uint32_t CpOpReleaseMem(CommandProcessor*, uint32_t, const uint32_t*, uint32_t, uint32_t);
|
||||
|
||||
} // namespace Libs::Graphics
|
||||
|
||||
#endif // GRAPHICS_GUEST_GPU_COMMAND_PROCESSOR_PM4_DISPATCH_H
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user