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https://github.com/KytyPS5/KytyPS5.git
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shader: lower HS neighbour LDS reads, control-point output read-back, looped HS reflection and integer partitioning
Co-authored-by: NeySlim <4509984+NeySlim@users.noreply.github.com>
This commit is contained in:
nmzik
@@ -34,8 +34,8 @@ void ReflectTessellationLayout(const Decoder::Program& program, bool local,
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using Registers = std::array<Address, IR::NumVectorRegs>;
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const auto control_points = local ? info.input_control_points : info.output_control_points;
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Registers registers {};
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registers[local ? 3u : 1u] =
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Registers entry {}, registers;
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entry[local ? 3u : 1u] =
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local ? Address {Kind::Affine, 1u, 0u} : Address {Kind::PackedControlPoint};
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const auto constant = [](uint32_t value) { return Address {Kind::Affine, 0u, value}; };
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const auto read = [&](const Operand& operand) -> Address {
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@@ -85,101 +85,115 @@ void ReflectTessellationLayout(const Decoder::Program& program, bool local,
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? value
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: Address {};
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};
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// A forward branch joins its target with the fallthrough path. Definitions that
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// differ between the paths are unknown there.
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std::unordered_map<uint32_t, Registers> joins;
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// A branch joins its target with the fallthrough path. Definitions that differ between
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// the paths are unknown there. Loop headers repeat the walk until back edges are stable.
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std::unordered_map<uint32_t, Registers> joins, loops;
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const auto merge = [](Registers& into, const Registers& from) {
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bool changed = false;
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for (uint32_t index = 0; index < into.size(); index++) {
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if (into[index] != from[index]) into[index] = {};
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if (into[index] == from[index]) continue;
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changed |= into[index] != Address {};
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into[index] = {};
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}
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return changed;
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};
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uint32_t stride = 0, patch_begin = UINT32_MAX, patch_end = 0;
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for (const auto& inst: program.instructions) {
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if (const auto join = joins.find(inst.pc); join != joins.end()) {
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merge(registers, join->second);
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joins.erase(join);
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}
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if (IsDirectBranch(inst.opcode)) {
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EXIT_NOT_IMPLEMENTED(inst.branch_target <= inst.pc);
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if (const auto [join, inserted] = joins.try_emplace(inst.branch_target, registers);
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!inserted)
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merge(join->second, registers);
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}
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const bool local_store = IsDsWriteOpcode(inst.opcode);
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const bool buffer_store = inst.opcode == Opcode::BUFFER_STORE_DWORD ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX2 ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX3 ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX4;
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const bool control_store =
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!local && buffer_store && inst.src2.kind == OperandKind::Sgpr && inst.src2.reg == 2u;
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const bool control_read =
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!local && (inst.opcode == Opcode::DS_READ_B32 || inst.opcode == Opcode::DS_READ2_B32);
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if ((local && local_store) || control_store || control_read) {
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const auto address = read(inst.src0);
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if (address.kind != Kind::Affine) {
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EXIT("%s tessellation address is not affine at pc 0x%08x\n", local ? "LS" : "HS",
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inst.pc);
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uint32_t stride = 0, patch_begin = 0, patch_end = 0;
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for (bool repeat = true; repeat;) {
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repeat = false;
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registers = entry;
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stride = 0, patch_begin = UINT32_MAX, patch_end = 0;
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for (const auto& inst: program.instructions) {
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if (const auto join = joins.find(inst.pc); join != joins.end()) {
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merge(registers, join->second);
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joins.erase(join);
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}
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if (address.coefficient != 0u) {
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const auto expected = control_read ? info.ls_stride : stride;
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EXIT_NOT_IMPLEMENTED((address.coefficient & 3u) != 0u ||
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(expected != 0u && expected != address.coefficient));
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if (!control_read) stride = address.coefficient;
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} else if (control_store) {
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// Control-point-independent HS outputs are patch constants.
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const auto begin = address.constant + inst.offset;
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patch_begin = std::min(patch_begin, begin);
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patch_end = std::max(patch_end, begin + 4u * inst.data_dwords);
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if (const auto loop = loops.find(inst.pc); loop != loops.end())
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merge(registers, loop->second);
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if (IsDirectBranch(inst.opcode)) {
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const bool back = inst.branch_target <= inst.pc;
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auto [join, inserted] =
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(back ? loops : joins).try_emplace(inst.branch_target, registers);
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const bool changed = !inserted && merge(join->second, registers);
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repeat |= back && (inserted || changed);
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}
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}
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// Store vdata is a source, despite occupying the decoder's dst field.
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if (local_store || buffer_store || inst.dst.kind != OperandKind::Vgpr) continue;
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const auto lhs = read(inst.src0);
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const auto rhs = read(inst.src1);
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const auto third = read(inst.src2);
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Address value;
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switch (inst.opcode) {
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case Opcode::V_BFE_U32:
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if (lhs.kind == Kind::PackedControlPoint && rhs.kind == Kind::Affine &&
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rhs.coefficient == 0u && third.kind == Kind::Affine &&
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third.coefficient == 0u) {
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if (rhs.constant == 8u && third.constant == 5u) value = {Kind::Affine, 1u, 0u};
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if (rhs.constant == 0u && third.constant == 8u) value = constant(0u);
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const bool local_store = IsDsWriteOpcode(inst.opcode);
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const bool buffer_store = inst.opcode == Opcode::BUFFER_STORE_DWORD ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX2 ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX3 ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX4;
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const bool control_store = !local && buffer_store &&
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inst.src2.kind == OperandKind::Sgpr && inst.src2.reg == 2u;
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if ((local && local_store) || control_store) {
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const auto address = read(inst.src0);
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if (address.kind != Kind::Affine) {
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EXIT("%s tessellation address is not affine at pc 0x%08x\n",
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local ? "LS" : "HS", inst.pc);
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}
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break;
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case Opcode::V_AND_B32:
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if ((lhs.kind == Kind::PackedControlPoint && rhs == constant(0xffu)) ||
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(rhs.kind == Kind::PackedControlPoint && lhs == constant(0xffu)))
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value = constant(0u);
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break;
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case Opcode::V_ADD_NC_U32: value = add(lhs, rhs); break;
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case Opcode::V_MUL_LO_U32: value = multiply(lhs, rhs); break;
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case Opcode::V_MUL_U32_U24: value = multiply(low24(lhs), low24(rhs)); break;
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case Opcode::V_MAD_U32_U24: value = add(multiply(low24(lhs), low24(rhs)), third); break;
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case Opcode::V_LSHL_ADD_U32:
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if (rhs.kind == Kind::Affine && rhs.coefficient == 0u && rhs.constant < 32u)
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value = add(multiply(lhs, constant(1u << rhs.constant)), third);
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break;
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case Opcode::V_LSHLREV_B32:
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if (lhs.kind == Kind::Affine && lhs.coefficient == 0u && lhs.constant < 32u)
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value = multiply(rhs, constant(1u << lhs.constant));
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break;
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case Opcode::V_SUB_NC_U32:
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if (lhs.kind == Kind::Affine && rhs.kind == Kind::Affine &&
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lhs.coefficient >= rhs.coefficient && lhs.constant >= rhs.constant)
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value = affine(lhs.coefficient - rhs.coefficient, lhs.constant - rhs.constant);
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break;
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default: break;
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if (address.coefficient != 0u) {
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EXIT_NOT_IMPLEMENTED((address.coefficient & 3u) != 0u ||
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(stride != 0u && stride != address.coefficient));
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stride = address.coefficient;
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} else if (control_store) {
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// Control-point-independent HS outputs are patch constants.
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const auto begin = address.constant + inst.offset;
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patch_begin = std::min(patch_begin, begin);
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patch_end = std::max(patch_end, begin + 4u * inst.data_dwords);
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}
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}
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// Store vdata is a source, despite occupying the decoder's dst field.
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if (local_store || buffer_store || inst.dst.kind != OperandKind::Vgpr) continue;
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const auto lhs = read(inst.src0);
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const auto rhs = read(inst.src1);
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const auto third = read(inst.src2);
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Address value;
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switch (inst.opcode) {
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case Opcode::V_BFE_U32:
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if (lhs.kind == Kind::PackedControlPoint && rhs.kind == Kind::Affine &&
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rhs.coefficient == 0u && third.kind == Kind::Affine &&
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third.coefficient == 0u) {
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if (rhs.constant == 8u && third.constant == 5u)
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value = {Kind::Affine, 1u, 0u};
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if (rhs.constant == 0u && third.constant == 8u) value = constant(0u);
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}
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break;
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case Opcode::V_AND_B32:
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if ((lhs.kind == Kind::PackedControlPoint && rhs == constant(0xffu)) ||
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(rhs.kind == Kind::PackedControlPoint && lhs == constant(0xffu)))
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value = constant(0u);
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break;
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case Opcode::V_ADD_NC_U32: value = add(lhs, rhs); break;
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case Opcode::V_MUL_LO_U32: value = multiply(lhs, rhs); break;
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case Opcode::V_MUL_U32_U24: value = multiply(low24(lhs), low24(rhs)); break;
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case Opcode::V_MAD_U32_U24:
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value = add(multiply(low24(lhs), low24(rhs)), third);
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break;
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case Opcode::V_LSHL_ADD_U32:
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if (rhs.kind == Kind::Affine && rhs.coefficient == 0u && rhs.constant < 32u)
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value = add(multiply(lhs, constant(1u << rhs.constant)), third);
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break;
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case Opcode::V_LSHLREV_B32:
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if (lhs.kind == Kind::Affine && lhs.coefficient == 0u && lhs.constant < 32u)
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value = multiply(rhs, constant(1u << lhs.constant));
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break;
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case Opcode::V_SUB_NC_U32:
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if (lhs.kind == Kind::Affine && rhs.kind == Kind::Affine &&
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lhs.coefficient >= rhs.coefficient && lhs.constant >= rhs.constant)
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value =
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affine(lhs.coefficient - rhs.coefficient, lhs.constant - rhs.constant);
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break;
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default: break;
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}
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if (inst.dst.sdwa_sel != 6u || inst.dst.op_sel || inst.dst.omod || inst.dst.clamp ||
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inst.dst.dpp)
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value = {};
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for (uint32_t index = 0;
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index < std::max(inst.data_dwords, 1u) && inst.dst.reg + index < registers.size();
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index++) {
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registers[inst.dst.reg + index] = {};
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}
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registers.at(inst.dst.reg) = value;
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}
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if (inst.dst.sdwa_sel != 6u || inst.dst.op_sel || inst.dst.omod || inst.dst.clamp ||
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inst.dst.dpp)
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value = {};
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for (uint32_t index = 0;
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index < std::max(inst.data_dwords, 1u) && inst.dst.reg + index < registers.size(); index++) {
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registers[inst.dst.reg + index] = {};
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}
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registers.at(inst.dst.reg) = value;
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}
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EXIT_NOT_IMPLEMENTED(!joins.empty() || stride == 0u);
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(local ? info.ls_stride : info.hs_stride) = stride;
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@@ -318,20 +332,22 @@ void LowerTessellationMemory(IR::Program& program, const CompileOptions& options
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kind = TessellationAttribute::Factor;
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factors += components;
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} else {
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kind = write ? TessellationAttribute::ControlOutput
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: TessellationAttribute::EvaluationInput;
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EXIT_NOT_IMPLEMENTED(write
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? options.stage != ShaderType::TessellationControl
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: options.stage != ShaderType::TessellationEvaluation);
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// After its barrier, the HS may read back outputs of other control points.
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const bool output = options.stage == ShaderType::TessellationControl;
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EXIT_NOT_IMPLEMENTED(
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!output && (write || options.stage != ShaderType::TessellationEvaluation));
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kind = output ? TessellationAttribute::ControlOutput
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: TessellationAttribute::EvaluationInput;
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if (address.IsImmediate() &&
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address.U32() >= tess.hs_stride * tess.output_control_points) {
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const auto begin = address.U32() + memory.offset;
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EXIT_NOT_IMPLEMENTED(begin < tess.patch_base ||
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begin + 4u * components >
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tess.patch_base + tess.patch_size);
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kind = write ? TessellationAttribute::PatchOutput
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: TessellationAttribute::PatchInput;
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patches += components;
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kind = output ? TessellationAttribute::PatchOutput
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: TessellationAttribute::PatchInput;
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// HS read-backs must not hide misplaced patch stores from the check below.
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if (write || !output) patches += components;
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}
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}
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} else {
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@@ -56,8 +56,10 @@ uint32_t TessellationPointer(ValueEmitContext& ctx, const IR::Inst& inst) {
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state.builder.AddFunction(spv::OpAccessChain, type, pointer, variable, attribute,
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component);
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} else {
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// An HS writes only its own control point but may read any other.
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const auto vertex =
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kind == Attribute::ControlOutput
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kind == Attribute::ControlOutput &&
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inst.GetOpcode() == IR::ValueOpcode::SetTessellationAttribute
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? EmitLaneId(state)
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: EmitBinaryU32(state, spv::OpUDiv, address, ConstantU32(state, stride));
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state.builder.AddFunction(spv::OpAccessChain, type, pointer, variable, vertex, attribute,
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@@ -126,7 +128,9 @@ void DefineTessellationInterfaces(EmitterState& state) {
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void DefineTessellationExecutionModes(EmitterState& state) {
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const auto& tess = state.input_info.vertex->tess;
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EXIT_NOT_IMPLEMENTED(tess.domain != 1u || tess.partitioning != 2u ||
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// CxVgtTfParam: triangles, integer or fractional-odd partitioning, clockwise output.
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EXIT_NOT_IMPLEMENTED(tess.domain != 1u ||
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(tess.partitioning != 0u && tess.partitioning != 2u) ||
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tess.output_topology != 2u);
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state.builder.RequireCapability(spv::CapabilityTessellation);
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if (state.program.stage == ShaderType::TessellationControl) {
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@@ -134,7 +138,9 @@ void DefineTessellationExecutionModes(EmitterState& state) {
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tess.output_control_points);
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} else {
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state.builder.AddExecutionMode(state.main_func, spv::ExecutionModeTriangles);
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state.builder.AddExecutionMode(state.main_func, spv::ExecutionModeSpacingFractionalOdd);
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state.builder.AddExecutionMode(
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state.main_func, tess.partitioning == 0u ? spv::ExecutionModeSpacingEqual
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: spv::ExecutionModeSpacingFractionalOdd);
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state.builder.AddExecutionMode(state.main_func, spv::ExecutionModeVertexOrderCw);
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}
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}
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