diff --git a/src/graphics/guest_gpu/command_processor/pm4Dispatch.cpp b/src/graphics/guest_gpu/command_processor/pm4Dispatch.cpp
index 12096d862..efb01df4c 100644
--- a/src/graphics/guest_gpu/command_processor/pm4Dispatch.cpp
+++ b/src/graphics/guest_gpu/command_processor/pm4Dispatch.cpp
@@ -23,9 +23,8 @@ constexpr auto MakeContextDispatchTable() {
 	g_hw_ctx_func[Pm4::DB_STENCIL_CLEAR]             = HwCtxSetStencilClear;
 	g_hw_ctx_func[Pm4::DB_DEPTH_CLEAR]               = HwCtxSetDepthClear;
 	g_hw_ctx_func[Pm4::PA_SC_SCREEN_SCISSOR_TL]      = HwCtxSetScreenScissor;
-	g_hw_ctx_func[Pm4::DB_Z_INFO]                    = HwCtxSetDepthRenderTarget;
 	g_hw_ctx_func[Pm4::DB_STENCIL_INFO]              = HwCtxSetStencilInfo;
-	g_hw_ctx_func[Pm4::DB_HTILE_SURFACE]             = HwCtxSetDepthHtileSurface;
+	g_hw_ctx_func[Pm4::DB_SHADING_RATE_ENCODING]     = HwCtxSetDepthShadingRateEncoding;
 	g_hw_ctx_func[Pm4::PA_SU_HARDWARE_SCREEN_OFFSET] = HwCtxSetHardwareScreenOffset;
 	g_hw_ctx_func[Pm4::PA_SC_WINDOW_OFFSET]          = HwCtxSetWindowOffset;
 	g_hw_ctx_func[Pm4::PA_SC_WINDOW_SCISSOR_TL]      = HwCtxSetWindowScissor;
@@ -75,7 +74,6 @@ constexpr auto MakeContextDispatchTable() {
 	g_hw_ctx_func[Pm4::PA_SC_BINNER_CNTL_0]                   = HwCtxSetPaScExtendedControl;
 	g_hw_ctx_func[Pm4::PA_SC_BINNER_CNTL_1]                   = HwCtxSetPaScExtendedControl;
 	g_hw_ctx_func[Pm4::PA_SC_CONSERVATIVE_RASTERIZATION_CNTL] = HwCtxSetPaScExtendedControl;
-	g_hw_ctx_func[Pm4::PA_SC_NGG_MODE_CNTL]                   = HwCtxSetPaScExtendedControl;
 	g_hw_ctx_func[Pm4::DB_ALPHA_TO_MASK]                      = HwCtxSetAlphaToMask;
 	g_hw_ctx_func[Pm4::VGT_DRAW_PAYLOAD_CNTL]                 = HwCtxSetDrawPayloadControl;
 	g_hw_ctx_func[Pm4::VGT_PRIMITIVEID_RESET]                 = HwCtxSetPrimitiveIdReset;
@@ -83,7 +81,6 @@ constexpr auto MakeContextDispatchTable() {
 	g_hw_ctx_func[Pm4::VGT_SHADER_STAGES_EN]                  = HwCtxSetShaderStages;
 
 	for (uint32_t slot = 0; slot < 8; slot++) {
-		g_hw_ctx_func[Pm4::CB_COLOR0_BASE + slot * 15] = HwCtxSetRenderTarget;
 		g_hw_ctx_func[Pm4::CB_COLOR0_INFO + slot * 15] = HwCtxSetColorInfo;
 
 		g_hw_ctx_func[Pm4::CB_BLEND0_CONTROL + slot * 1] = HwCtxSetBlendControl;
@@ -116,25 +113,21 @@ constexpr auto MakeShaderDispatchTable() {
 	}
 
 	for (uint32_t slot = 0; slot < 4; slot++) {
-		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_PS_0 + slot] = HwShSetPsUserAccumSgpr;
+		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_PS_0 + slot] = HwShIgnoreUserAccumulator;
 	}
 
 	for (uint32_t slot = 0; slot < 4; slot++) {
-		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_ESGS_0 + slot] = HwShSetGsUserAccumSgpr;
+		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_ESGS_0 + slot] = HwShIgnoreUserAccumulator;
 	}
 	for (uint32_t slot = 0; slot < 4; slot++) {
-		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_LSHS_0 + slot] = HwShSetHsUserAccumSgpr;
+		g_hw_sh_func[Pm4::SPI_SHADER_USER_ACCUM_LSHS_0 + slot] = HwShIgnoreUserAccumulator;
 	}
 
-	for (uint32_t slot = 0; Pm4::COMPUTE_USER_ACCUM_0 + slot < Pm4::COMPUTE_USER_DATA_0; slot++) {
-		g_hw_sh_func[Pm4::COMPUTE_USER_ACCUM_0 + slot] = HwShSetCsUserAccumSgpr;
+	for (uint32_t slot = 0; slot < 4; slot++) {
+		g_hw_sh_func[Pm4::COMPUTE_USER_ACCUM_0 + slot] = HwShIgnoreUserAccumulator;
 	}
 	g_hw_sh_func[Pm4::COMPUTE_PGM_LO]                  = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_PGM_HI]                  = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_TBA_LO]                  = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_TBA_HI]                  = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_TMA_LO]                  = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_TMA_HI]                  = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC1]               = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC2]               = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_START_X]                 = HwShSetCsRegisters;
@@ -144,30 +137,16 @@ constexpr auto MakeShaderDispatchTable() {
 	g_hw_sh_func[Pm4::COMPUTE_NUM_THREAD_Y]            = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_NUM_THREAD_Z]            = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_RESOURCE_LIMITS]         = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE0]      = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE1]      = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_TMPRING_SIZE]            = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE2]      = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_DESTINATION_EN_SE3]      = HwShSetCsRegisters;
 	g_hw_sh_func[Pm4::COMPUTE_PGM_RSRC3]               = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_SHADER_CHKSUM]           = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::COMPUTE_DISPATCH_TUNNEL]         = HwShSetCsRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_TBA_LO_PS]            = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_PS]         = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_PS]         = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_TMA_LO_PS]            = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_TMA_HI_PS]            = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_PS]          = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_GS]         = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_GS]         = HwShIgnoreRegisters;
+	g_hw_sh_func[Pm4::COMPUTE_PACE_ID]                 = HwShSetCsRegisters;
+	g_hw_sh_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_PS]  = HwShIgnoreRegisters;
+	g_hw_sh_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_GS]  = HwShIgnoreRegisters;
 	g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_GS] = HwShIgnoreRegisters;
 	g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_GS] = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_ESGS]        = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC3_HS]         = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_PGM_RSRC4_HS]         = HwShIgnoreRegisters;
+	g_hw_sh_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_HS]  = HwShIgnoreRegisters;
 	g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_HS] = HwShIgnoreRegisters;
 	g_hw_sh_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_HS] = HwShIgnoreRegisters;
-	g_hw_sh_func[Pm4::SPI_SHADER_REQ_CTRL_LSHS]        = HwShIgnoreRegisters;
 
 	return g_hw_sh_func;
 }
@@ -179,6 +158,7 @@ constexpr auto MakeUconfigDispatchTable() {
 	g_hw_uc_func[Pm4::VGT_INDEX_TYPE]            = HwUcSetIndexType;
 	g_hw_uc_func[Pm4::VGT_OBJECT_ID]             = HwUcSetObjectId;
 	g_hw_uc_func[Pm4::TEXTURE_GRADIENT_FACTORS]  = HwUcSetTextureGradientFactors;
+	g_hw_uc_func[Pm4::TEXTURE_GRADIENT_CONTROL]  = HwUcSetTextureGradientFactors;
 	g_hw_uc_func[Pm4::IA_MULTI_VGT_PARAM]        = HwUcSetIaMultiVgtParam;
 	g_hw_uc_func[Pm4::GE_MULTI_PRIM_IB_RESET_EN] = HwUcSetMultiPrimIbReset;
 	g_hw_uc_func[Pm4::TA_CS_BC_BASE_ADDR]        = HwUcSetBorderColorTableAddr;
diff --git a/src/graphics/guest_gpu/command_processor/pm4Dispatch.h b/src/graphics/guest_gpu/command_processor/pm4Dispatch.h
index a3596ca34..04e4f236f 100644
--- a/src/graphics/guest_gpu/command_processor/pm4Dispatch.h
+++ b/src/graphics/guest_gpu/command_processor/pm4Dispatch.h
@@ -44,11 +44,9 @@ uint32_t HwCtxSetBorderColorTableAddr(CommandProcessor&, uint32_t, uint32_t, con
 uint32_t HwCtxSetStencilClear(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetDepthClear(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetScreenScissor(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwCtxSetDepthRenderTarget(CommandProcessor&, uint32_t, uint32_t, const uint32_t*,
-                                   uint32_t);
 uint32_t HwCtxSetStencilInfo(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwCtxSetDepthHtileSurface(CommandProcessor&, uint32_t, uint32_t, const uint32_t*,
-                                   uint32_t);
+uint32_t HwCtxSetDepthShadingRateEncoding(CommandProcessor&, uint32_t, uint32_t,
+                                          const uint32_t*, uint32_t);
 uint32_t HwCtxSetHardwareScreenOffset(CommandProcessor&, uint32_t, uint32_t, const uint32_t*,
                                       uint32_t);
 uint32_t HwCtxSetWindowOffset(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
@@ -89,7 +87,6 @@ uint32_t HwCtxSetDrawPayloadControl(CommandProcessor&, uint32_t, uint32_t, const
 uint32_t HwCtxSetPrimitiveIdReset(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetObjprimIdControl(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetShaderStages(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwCtxSetRenderTarget(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetColorInfo(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetBlendControl(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwCtxSetViewportScissor(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
@@ -100,10 +97,8 @@ uint32_t HwShSetPsUserSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t
 uint32_t HwShSetGsUserSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwShSetHsUserSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwShSetCsUserSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwShSetPsUserAccumSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwShSetGsUserAccumSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwShSetHsUserAccumSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
-uint32_t HwShSetCsUserAccumSgpr(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
+uint32_t HwShIgnoreUserAccumulator(CommandProcessor&, uint32_t, uint32_t, const uint32_t*,
+                                   uint32_t);
 uint32_t HwShSetCsRegisters(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwShIgnoreRegisters(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
 uint32_t HwUcSetPrimitiveType(CommandProcessor&, uint32_t, uint32_t, const uint32_t*, uint32_t);
diff --git a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
index dae2687ed..557302d2e 100644
--- a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
+++ b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
@@ -136,6 +136,7 @@ static HW::ColorControl DecodeColorControl(uint32_t value) {
 
 static HW::DepthControl DecodeDepthControl(uint32_t value) {
 	HW::DepthControl r {};
+	EXIT_NOT_IMPLEMENTED((value & 0xc0000000u) != 0);
 
 	r.stencil_enable      = KYTY_PM4_GET(value, DB_DEPTH_CONTROL, STENCIL_ENABLE) != 0;
 	r.z_enable            = KYTY_PM4_GET(value, DB_DEPTH_CONTROL, Z_ENABLE) != 0;
@@ -145,10 +146,6 @@ static HW::DepthControl DecodeDepthControl(uint32_t value) {
 	r.backface_enable     = KYTY_PM4_GET(value, DB_DEPTH_CONTROL, BACKFACE_ENABLE) != 0;
 	r.stencilfunc         = KYTY_PM4_GET(value, DB_DEPTH_CONTROL, STENCILFUNC);
 	r.stencilfunc_bf      = KYTY_PM4_GET(value, DB_DEPTH_CONTROL, STENCILFUNC_BF);
-	r.color_writes_on_depth_fail_enable =
-	    KYTY_PM4_GET(value, DB_DEPTH_CONTROL, ENABLE_COLOR_WRITES_ON_DEPTH_FAIL) != 0;
-	r.color_writes_on_depth_pass_disable =
-	    KYTY_PM4_GET(value, DB_DEPTH_CONTROL, DISABLE_COLOR_WRITES_ON_DEPTH_PASS) != 0;
 
 	return r;
 }
@@ -183,8 +180,12 @@ static HW::RenderControl DecodeRenderControl(uint32_t value) {
 	r.stencil_compress_disable =
 	    KYTY_PM4_GET(value, DB_RENDER_CONTROL, STENCIL_COMPRESS_DISABLE) != 0;
 	r.depth_compress_disable = KYTY_PM4_GET(value, DB_RENDER_CONTROL, DEPTH_COMPRESS_DISABLE) != 0;
+	r.copy_depth_to_color = KYTY_PM4_GET(value, DB_RENDER_CONTROL, COPY_DEPTH_TO_COLOR) != 0;
+	r.copy_stencil_to_color =
+	    KYTY_PM4_GET(value, DB_RENDER_CONTROL, COPY_STENCIL_TO_COLOR) != 0;
 	r.copy_centroid          = KYTY_PM4_GET(value, DB_RENDER_CONTROL, COPY_CENTROID) != 0;
 	r.copy_sample            = KYTY_PM4_GET(value, DB_RENDER_CONTROL, COPY_SAMPLE);
+	EXIT_NOT_IMPLEMENTED(r.copy_depth_to_color || r.copy_stencil_to_color);
 
 	return r;
 }
@@ -355,8 +356,6 @@ KYTY_HW_CTX_PARSER(HwCtxSetSpiTmpringSize) {
 
 static bool HwCtxIsFakeRegister(uint32_t cmd_offset) {
 	switch (cmd_offset) {
-		case 0x18:
-		case 0x19:
 		case Pm4::CX_NOP: return true;
 		default: return false;
 	}
@@ -551,19 +550,6 @@ KYTY_HW_CTX_PARSER(HwCtxSetColorInfo) {
 	uint32_t param = (cmd_offset - Pm4::CB_COLOR0_INFO) / 15;
 
 	HW::ColorInfo r;
-
-	//	r.fmask_compression_enable = (buffer[4] & 0x4000u) != 0;
-	//	// r.fmask_compression_mode   = (buffer[4] >> 26u) & 0x3u;
-	//	r.fmask_data_compression_disable = ((buffer[4] >> 26u) & 0x1u) != 0;
-	//	r.fmask_one_frag_mode            = ((buffer[4] >> 27u) & 0x1u) != 0;
-	//	r.cmask_fast_clear_enable        = (buffer[4] & 0x2000u) != 0;
-	//	r.dcc_compression_enable         = (buffer[4] & 0x10000000u) != 0;
-	//	r.cmask_is_linear                = (buffer[4] >> 19u) & 0x1u;
-	//	r.cmask_addr_type                = (buffer[4] >> 29u) & 0x3u;
-	//	r.alt_tile_mode                  = ((buffer[4] >> 31u) & 0x1u) != 0;
-	//	r.format                         = (buffer[4] >> 2u) & 0x1fu;
-	//	r.channel_type                   = (buffer[4] >> 8u) & 0x7u;
-	//	r.channel_order                  = (buffer[4] >> 11u) & 0x3u;
 	r.format =
 	    static_cast<Prospero::ChannelLayout>(KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, FORMAT));
 	r.channel_type =
@@ -575,13 +561,10 @@ KYTY_HW_CTX_PARSER(HwCtxSetColorInfo) {
 	r.blend_clamp              = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, BLEND_CLAMP) != 0;
 	r.blend_bypass             = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, BLEND_BYPASS) != 0;
 	r.round_mode               = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, ROUND_MODE) != 0;
-	r.cmask_is_linear          = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, CMASK_IS_LINEAR);
 	r.fmask_data_compression_disable =
 	    KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, FMASK_COMPRESSION_DISABLE) != 0;
 	r.fmask_one_frag_mode = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, FMASK_COMPRESS_1FRAG_ONLY) != 0;
 	r.dcc_compression_enable = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, DCC_ENABLE) != 0;
-	r.cmask_addr_type        = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, CMASK_ADDR_TYPE);
-	r.alt_tile_mode          = KYTY_PM4_GET(buffer[0], CB_COLOR0_INFO, ALT_TILE_MODE) != 0;
 
 	cp.GetCtx().SetColorInfo(param, r);
 
@@ -606,124 +589,28 @@ KYTY_HW_CTX_PARSER(HwCtxSetDepthControl) {
 	return 1;
 }
 
-static HW::DepthRenderTargetHTileSurface ParseDepthHtileSurface(uint32_t value) {
-	HW::DepthRenderTargetHTileSurface r;
-	r.linear                  = KYTY_PM4_GET(value, DB_HTILE_SURFACE, LINEAR);
-	r.full_cache              = KYTY_PM4_GET(value, DB_HTILE_SURFACE, FULL_CACHE);
-	r.htile_uses_preload_win  = KYTY_PM4_GET(value, DB_HTILE_SURFACE, HTILE_USES_PRELOAD_WIN);
-	r.preload                 = KYTY_PM4_GET(value, DB_HTILE_SURFACE, PRELOAD);
-	r.prefetch_width          = KYTY_PM4_GET(value, DB_HTILE_SURFACE, PREFETCH_WIDTH);
-	r.prefetch_height         = KYTY_PM4_GET(value, DB_HTILE_SURFACE, PREFETCH_HEIGHT);
-	r.dst_outside_zero_to_one = KYTY_PM4_GET(value, DB_HTILE_SURFACE, DST_OUTSIDE_ZERO_TO_ONE);
-	return r;
-}
+static void HwCtxSetDepthShadingRateEncodingRegister(CommandProcessor& cp, uint32_t value) {
+	const auto shading_rate_encoding =
+	    KYTY_PM4_GET(value, DB_SHADING_RATE_ENCODING, SHADING_RATE_ENCODING);
+	EXIT_NOT_IMPLEMENTED(shading_rate_encoding > 2u);
 
-static void HwCtxSetDepthHtileSurfaceRegister(CommandProcessor& cp, uint32_t value) {
-	auto& ctx            = cp.GetCtx();
-	auto  target         = ctx.GetDepthRenderTarget();
-	target.htile_surface = ParseDepthHtileSurface(value);
+	auto& ctx                       = cp.GetCtx();
+	auto  target                    = ctx.GetDepthRenderTarget();
+	target.shading_rate_encoding    = static_cast<uint8_t>(shading_rate_encoding);
 	ctx.SetDepthRenderTarget(target);
 }
 
-KYTY_HW_CTX_PARSER(HwCtxSetDepthHtileSurface) {
+KYTY_HW_CTX_PARSER(HwCtxSetDepthShadingRateEncoding) {
 	auto num_values = KYTY_PM4_LEN(cmd_id) - 2u;
 
 	EXIT_NOT_IMPLEMENTED(num_values != 1);
-	EXIT_NOT_IMPLEMENTED(cmd_offset != Pm4::DB_HTILE_SURFACE);
+	EXIT_NOT_IMPLEMENTED(cmd_offset != Pm4::DB_SHADING_RATE_ENCODING);
 
-	HwCtxSetDepthHtileSurfaceRegister(cp, buffer[0]);
+	HwCtxSetDepthShadingRateEncodingRegister(cp, buffer[0]);
 
 	return num_values;
 }
 
-KYTY_HW_CTX_PARSER(HwCtxSetDepthRenderTarget) {
-	EXIT_NOT_IMPLEMENTED(cmd_offset != Pm4::DB_Z_INFO);
-
-	uint32_t count = 1;
-
-	if (cmd_id == 0xC0016900) {
-		cp.GetCtx().SetDepthZInfo(HW::DepthZInfo::Decode(buffer[0]));
-	} else if (cmd_id == 0xC0086900) {
-		if (dw >= 22 && buffer[8] == 0xC0016900 && buffer[9] == Pm4::DB_DEPTH_INFO &&
-		    buffer[11] == 0xC0016900 && buffer[12] == Pm4::DB_DEPTH_VIEW &&
-		    buffer[14] == 0xC0016900 && buffer[15] == Pm4::DB_HTILE_DATA_BASE &&
-		    buffer[17] == 0xC0016900 && buffer[18] == Pm4::DB_HTILE_SURFACE &&
-		    buffer[20] == 0xC0001000) {
-			count = 22;
-
-			HW::DepthRenderTarget z;
-
-			z.z_info       = HW::DepthZInfo::Decode(buffer[0]);
-			z.stencil_info = HW::DepthStencilInfo::Decode(buffer[1]);
-
-			z.z_read_base_addr        = static_cast<uint64_t>(buffer[2]) << 8u;
-			z.stencil_read_base_addr  = static_cast<uint64_t>(buffer[3]) << 8u;
-			z.z_write_base_addr       = static_cast<uint64_t>(buffer[4]) << 8u;
-			z.stencil_write_base_addr = static_cast<uint64_t>(buffer[5]) << 8u;
-
-			// DB_DEPTH_SIZE
-			z.pitch_div8_minus1  = (buffer[6] >> Pm4::DB_DEPTH_SIZE_PITCH_TILE_MAX_SHIFT) &
-			                       Pm4::DB_DEPTH_SIZE_PITCH_TILE_MAX_MASK;
-			z.height_div8_minus1 = (buffer[6] >> Pm4::DB_DEPTH_SIZE_HEIGHT_TILE_MAX_SHIFT) &
-			                       Pm4::DB_DEPTH_SIZE_HEIGHT_TILE_MAX_MASK;
-			z.pitch_height_valid = true;
-
-			// DB_DEPTH_SLICE
-			z.slice_div64_minus1 = (buffer[7] >> Pm4::DB_DEPTH_SLICE_SLICE_TILE_MAX_SHIFT) &
-			                       Pm4::DB_DEPTH_SLICE_SLICE_TILE_MAX_MASK;
-
-			z.depth_info.addr5_swizzle_mask =
-			    KYTY_PM4_GET(buffer[10], DB_DEPTH_INFO, ADDR5_SWIZZLE_MASK);
-			z.depth_info.array_mode  = (buffer[10] >> Pm4::DB_DEPTH_INFO_ARRAY_MODE_SHIFT) &
-			                           Pm4::DB_DEPTH_INFO_ARRAY_MODE_MASK;
-			z.depth_info.pipe_config = (buffer[10] >> Pm4::DB_DEPTH_INFO_PIPE_CONFIG_SHIFT) &
-			                           Pm4::DB_DEPTH_INFO_PIPE_CONFIG_MASK;
-			z.depth_info.bank_width  = (buffer[10] >> Pm4::DB_DEPTH_INFO_BANK_WIDTH_SHIFT) &
-			                           Pm4::DB_DEPTH_INFO_BANK_WIDTH_MASK;
-			z.depth_info.bank_height = (buffer[10] >> Pm4::DB_DEPTH_INFO_BANK_HEIGHT_SHIFT) &
-			                           Pm4::DB_DEPTH_INFO_BANK_HEIGHT_MASK;
-			z.depth_info.macro_tile_aspect =
-			    KYTY_PM4_GET(buffer[10], DB_DEPTH_INFO, MACRO_TILE_ASPECT);
-			z.depth_info.num_banks = (buffer[10] >> Pm4::DB_DEPTH_INFO_NUM_BANKS_SHIFT) &
-			                         Pm4::DB_DEPTH_INFO_NUM_BANKS_MASK;
-
-			// z.depth_view.slice_start = (buffer[13] >> Pm4::DB_DEPTH_VIEW_SLICE_START_SHIFT) &
-			// Pm4::DB_DEPTH_VIEW_SLICE_START_MASK; z.depth_view.slice_max   = (buffer[13] >>
-			// Pm4::DB_DEPTH_VIEW_SLICE_MAX_SHIFT) & Pm4::DB_DEPTH_VIEW_SLICE_MAX_MASK;
-
-			z.depth_view.slice_start =
-			    KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, SLICE_START) +
-			    (KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, SLICE_START_HI) << 11u);
-			z.depth_view.slice_max = KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, SLICE_MAX) +
-			                         (KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, SLICE_MAX_HI) << 11u);
-			z.depth_view.depth_write_disable =
-			    KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, Z_READ_ONLY) != 0;
-			z.depth_view.stencil_write_disable =
-			    KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, STENCIL_READ_ONLY) != 0;
-			z.depth_view.current_mip_level = KYTY_PM4_GET(buffer[13], DB_DEPTH_VIEW, MIPID);
-
-			z.htile_data_base_addr = static_cast<uint64_t>(buffer[16]) << 8u;
-
-			z.htile_surface = ParseDepthHtileSurface(buffer[19]);
-
-			if (buffer[21] != 0) {
-				// CxDepthRenderTarget stores width/height as value - 1 in register 13.
-				z.width              = ((buffer[21] >> 0u) & 0x3fffu) + 1u;
-				z.height             = ((buffer[21] >> 16u) & 0x3fffu) + 1u;
-				z.width_height_valid = true;
-			}
-
-			cp.GetCtx().SetDepthRenderTarget(z);
-		} else {
-			KYTY_NOT_IMPLEMENTED;
-		}
-	} else {
-		KYTY_NOT_IMPLEMENTED;
-	}
-
-	return count;
-}
-
 static HW::EqaaControl ParseEqaaControl(uint32_t value) {
 	HW::EqaaControl r;
 
@@ -962,181 +849,6 @@ KYTY_HW_CTX_PARSER(HwCtxSetRenderControl) {
 	return 1;
 }
 
-KYTY_HW_CTX_PARSER(HwCtxSetRenderTarget) {
-	uint32_t count = (cmd_id >> 16u) & 0x3fffu;
-	if (count < 11 || count > 14) {
-		bool handled = (count > 0);
-		for (uint32_t i = 0; i < count; i++) {
-			if (cmd_offset + i >= Pm4::CX_NUM ||
-			    g_hw_ctx_indirect_func[(cmd_offset + i) & (Pm4::CX_NUM - 1)] == nullptr) {
-				handled = false;
-				break;
-			}
-		}
-		if (handled) {
-			for (uint32_t i = 0; i < count; i++) {
-				g_hw_ctx_indirect_func[(cmd_offset + i) & (Pm4::CX_NUM - 1)](cp, cmd_offset + i,
-				                                                             buffer[i]);
-			}
-			return count;
-		}
-
-		EXIT_NOT_IMPLEMENTED(count < 11 || count > 14);
-	}
-
-	uint32_t slot = (cmd_offset - Pm4::CB_COLOR0_BASE) / 15;
-
-	auto& ctx = cp.GetCtx();
-
-	HW::ColorBase       base;
-	HW::ColorPitch      pitch;
-	HW::ColorSlice      slice;
-	HW::ColorView       view;
-	HW::ColorInfo       info;
-	HW::ColorAttrib     attrib;
-	HW::ColorDccControl dcc;
-	HW::ColorCmask      cmask;
-	HW::ColorCmaskSlice cmask_slice;
-	HW::ColorFmask      fmask;
-	HW::ColorFmaskSlice fmask_slice;
-
-	base.addr                     = static_cast<uint64_t>(buffer[0]) << 8u;
-	pitch.pitch_div8_minus1       = buffer[1] & 0x7ffu;
-	pitch.fmask_pitch_div8_minus1 = (buffer[1] >> 20u) & 0x7ffu;
-	slice.slice_div64_minus1      = buffer[2] & 0x3fffffu;
-
-	// view.base_array_slice_index     = buffer[3] & 0x7ffu;
-	// view.last_array_slice_index     = (buffer[3] >> 13u) & 0x7ffu;
-	view.base_array_slice_index = KYTY_PM4_GET(buffer[3], CB_COLOR0_VIEW, SLICE_START);
-	view.last_array_slice_index = KYTY_PM4_GET(buffer[3], CB_COLOR0_VIEW, SLICE_MAX);
-	view.current_mip_level      = KYTY_PM4_GET(buffer[3], CB_COLOR0_VIEW, MIP_LEVEL);
-
-	//	info.fmask_compression_enable = (buffer[4] & 0x4000u) != 0;
-	//
-	//	// info.fmask_compression_mode   = (buffer[4] >> 26u) & 0x3u;
-	//	info.fmask_data_compression_disable = ((buffer[4] >> 26u) & 0x1u) != 0;
-	//	info.fmask_one_frag_mode            = ((buffer[4] >> 27u) & 0x1u) != 0;
-	//
-	//	info.cmask_fast_clear_enable = (buffer[4] & 0x2000u) != 0;
-	//	info.dcc_compression_enable  = (buffer[4] & 0x10000000u) != 0;
-	//	info.cmask_is_linear         = (buffer[4] >> 19u) & 0x1u;
-	//	info.cmask_addr_type         = (buffer[4] >> 29u) & 0x3u;
-	//	info.alt_tile_mode           = ((buffer[4] >> 31u) & 0x1u) != 0;
-	//	info.format                  = (buffer[4] >> 2u) & 0x1fu;
-	//	info.channel_type            = (buffer[4] >> 8u) & 0x7u;
-	//	info.channel_order           = (buffer[4] >> 11u) & 0x3u;
-	info.format =
-	    static_cast<Prospero::ChannelLayout>(KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, FORMAT));
-	info.channel_type =
-	    static_cast<Prospero::ChannelType>(KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, NUMBER_TYPE));
-	info.channel_order =
-	    static_cast<Prospero::ChannelOrder>(KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, COMP_SWAP));
-	info.cmask_fast_clear_enable  = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, FAST_CLEAR) != 0;
-	info.fmask_compression_enable = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, COMPRESSION) != 0;
-	info.blend_clamp              = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, BLEND_CLAMP) != 0;
-	info.blend_bypass             = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, BLEND_BYPASS) != 0;
-	info.round_mode               = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, ROUND_MODE) != 0;
-	info.cmask_is_linear          = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, CMASK_IS_LINEAR);
-	info.fmask_data_compression_disable =
-	    KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, FMASK_COMPRESSION_DISABLE) != 0;
-	info.fmask_one_frag_mode =
-	    KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, FMASK_COMPRESS_1FRAG_ONLY) != 0;
-	info.dcc_compression_enable = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, DCC_ENABLE) != 0;
-	info.cmask_addr_type        = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, CMASK_ADDR_TYPE);
-	info.alt_tile_mode          = KYTY_PM4_GET(buffer[4], CB_COLOR0_INFO, ALT_TILE_MODE) != 0;
-
-	//	attrib.force_dest_alpha_to_one  = (buffer[5] & 0x20000u) != 0;
-	//	attrib.tile_mode                = buffer[5] & 0x1fu;
-	//	attrib.fmask_tile_mode          = (buffer[5] >> 5u) & 0x1fu;
-	//	attrib.num_samples              = (buffer[5] >> 12u) & 0x7u;
-	//	attrib.num_fragments            = (buffer[5] >> 15u) & 0x3u;
-	attrib.force_dest_alpha_to_one =
-	    KYTY_PM4_GET(buffer[5], CB_COLOR0_ATTRIB, FORCE_DST_ALPHA_1) != 0;
-	attrib.tile_mode =
-	    static_cast<Prospero::TileMode>(KYTY_PM4_GET(buffer[5], CB_COLOR0_ATTRIB, TILE_MODE_INDEX));
-	attrib.fmask_tile_mode = static_cast<Prospero::TileMode>(
-	    KYTY_PM4_GET(buffer[5], CB_COLOR0_ATTRIB, FMASK_TILE_MODE_INDEX));
-	attrib.num_samples   = KYTY_PM4_GET(buffer[5], CB_COLOR0_ATTRIB, NUM_SAMPLES);
-	attrib.num_fragments = KYTY_PM4_GET(buffer[5], CB_COLOR0_ATTRIB, NUM_FRAGMENTS);
-
-	//	dcc.max_uncompressed_block_size = (buffer[6] >> 2u) & 0x3u;
-	//	dcc.max_compressed_block_size   = (buffer[6] >> 5u) & 0x3u;
-	//	dcc.min_compressed_block_size   = (buffer[6] >> 4u) & 0x1u;
-	//	dcc.color_transform             = (buffer[6] >> 7u) & 0x3u;
-	//	dcc.overwrite_combiner_disable   = (buffer[6] & 0x1u) != 0;
-	//	dcc.independent_64b_blocks    = (buffer[6] & 0x200u) != 0;
-	dcc.overwrite_combiner_disable =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, OVERWRITE_COMBINER_DISABLE) != 0;
-	dcc.dcc_clear_key_enable =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, KEY_CLEAR_ENABLE) != 0;
-	dcc.max_uncompressed_block_size =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, MAX_UNCOMPRESSED_BLOCK_SIZE);
-	dcc.min_compressed_block_size =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, MIN_COMPRESSED_BLOCK_SIZE);
-	dcc.max_compressed_block_size =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, MAX_COMPRESSED_BLOCK_SIZE);
-	dcc.color_transform = KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, COLOR_TRANSFORM);
-	dcc.independent_64b_blocks =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, INDEPENDENT_64B_BLOCKS) != 0;
-	dcc.data_write_on_dcc_clear_to_reg =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, ENABLE_CONSTANT_ENCODE_REG_WRITE) != 0;
-	dcc.independent_128b_blocks =
-	    KYTY_PM4_GET(buffer[6], CB_COLOR0_DCC_CONTROL, INDEPENDENT_128B_BLOCKS) != 0;
-
-	cmask.addr               = static_cast<uint64_t>(buffer[7]) << 8u;
-	cmask_slice.slice_minus1 = buffer[8] & 0x3fffu;
-
-	fmask.addr               = static_cast<uint64_t>(buffer[9]) << 8u;
-	fmask_slice.slice_minus1 = buffer[10] & 0x3fffffu;
-
-	ctx.SetColorBase(slot, base);
-	ctx.SetColorPitch(slot, pitch);
-	ctx.SetColorSlice(slot, slice);
-	ctx.SetColorView(slot, view);
-	ctx.SetColorInfo(slot, info);
-	ctx.SetColorAttrib(slot, attrib);
-	ctx.SetColorDccControl(slot, dcc);
-	ctx.SetColorCmask(slot, cmask);
-	ctx.SetColorCmaskSlice(slot, cmask_slice);
-	ctx.SetColorFmask(slot, fmask);
-	ctx.SetColorFmaskSlice(slot, fmask_slice);
-
-	if (count > 11) {
-		HW::ColorClearWord0 clear_word0;
-
-		clear_word0.word0 = buffer[11];
-
-		ctx.SetColorClearWord0(slot, clear_word0);
-	}
-	if (count > 12) {
-		HW::ColorClearWord1 clear_word1;
-
-		clear_word1.word1 = buffer[12];
-
-		ctx.SetColorClearWord1(slot, clear_word1);
-	}
-	if (count > 13) {
-		HW::ColorDccAddr dcc_addr;
-
-		dcc_addr.addr = static_cast<uint64_t>(buffer[13]) << 8u;
-
-		ctx.SetColorDccAddr(slot, dcc_addr);
-	}
-
-	if (dw >= count + 2 && buffer[count] == 0xC0001000) {
-		HW::ColorSize size;
-
-		size.width  = (buffer[count + 1] >> 0u) & 0xffffu;
-		size.height = (buffer[count + 1] >> 16u) & 0xffffu;
-
-		ctx.SetColorSize(slot, size);
-
-		count += 2;
-	}
-
-	return count;
-}
-
 KYTY_HW_CTX_PARSER(HwCtxSetRenderTargetMask) {
 	EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0016900);
 	EXIT_NOT_IMPLEMENTED(cmd_offset != Pm4::CB_TARGET_MASK);
@@ -1281,7 +993,16 @@ static void HwShIgnoreShaderRegister([[maybe_unused]] uint32_t cmd_offset,
                                      [[maybe_unused]] uint32_t value) {}
 
 KYTY_HW_SH_PARSER(HwShIgnoreRegisters) {
-	return (cmd_id >> 16u) & 0x3fffu;
+	const auto reg_num = (cmd_id >> 16u) & 0x3fffu;
+	EXIT_NOT_IMPLEMENTED(reg_num == 0);
+
+	for (uint32_t i = 0; i < reg_num; i++) {
+		const auto offset = cmd_offset + i;
+		EXIT_NOT_IMPLEMENTED(offset >= Pm4::SH_NUM || g_hw_sh_indirect_func[offset] == nullptr);
+		g_hw_sh_indirect_func[offset](cp, offset, buffer[i]);
+	}
+
+	return reg_num;
 }
 
 static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_t value) {
@@ -1296,27 +1017,26 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_
 			cs_regs.data_addr &= 0xFFFF00FFFFFFFFFFull;
 			cs_regs.data_addr |= (static_cast<uint64_t>(value) & 0xffu) << 40u;
 			break;
-		case Pm4::COMPUTE_TBA_LO:
-		case Pm4::COMPUTE_TBA_HI:
-		case Pm4::COMPUTE_TMA_LO:
-		case Pm4::COMPUTE_TMA_HI: HwShIgnoreComputeRegister(cmd_offset, value); break;
 		case Pm4::COMPUTE_PGM_RSRC1:
 			cs_regs.vgprs =
 			    (value >> Pm4::COMPUTE_PGM_RSRC1_VGPRS_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_VGPRS_MASK;
-			cs_regs.sgprs =
-			    (value >> Pm4::COMPUTE_PGM_RSRC1_SGPRS_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_SGPRS_MASK;
+			cs_regs.priority = (value >> Pm4::COMPUTE_PGM_RSRC1_PRIORITY_SHIFT) &
+			                   Pm4::COMPUTE_PGM_RSRC1_PRIORITY_MASK;
 			cs_regs.float_mode    = (value >> Pm4::COMPUTE_PGM_RSRC1_FLOAT_MODE_SHIFT) &
 			                        Pm4::COMPUTE_PGM_RSRC1_FLOAT_MODE_MASK;
 			cs_regs.dx10_clamp    = ((value >> Pm4::COMPUTE_PGM_RSRC1_DX10_CLAMP_SHIFT) &
 			                         Pm4::COMPUTE_PGM_RSRC1_DX10_CLAMP_MASK) != 0u;
+			cs_regs.debug_mode    = ((value >> Pm4::COMPUTE_PGM_RSRC1_DEBUG_MODE_SHIFT) &
+			                         Pm4::COMPUTE_PGM_RSRC1_DEBUG_MODE_MASK) != 0u;
 			cs_regs.ieee_mode     = ((value >> Pm4::COMPUTE_PGM_RSRC1_IEEE_MODE_SHIFT) &
 			                         Pm4::COMPUTE_PGM_RSRC1_IEEE_MODE_MASK) != 0u;
 			cs_regs.fp16_overflow = ((value >> Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT) &
 			                         Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_MASK) != 0u;
-			cs_regs.bulky         = ((value >> Pm4::COMPUTE_PGM_RSRC1_BULKY_SHIFT) &
-			                         Pm4::COMPUTE_PGM_RSRC1_BULKY_MASK) != 0u;
 			cs_regs.threadgroup_configuration = ((value >> Pm4::COMPUTE_PGM_RSRC1_WGP_MODE_SHIFT) &
 			                                     Pm4::COMPUTE_PGM_RSRC1_WGP_MODE_MASK) != 0u;
+			cs_regs.require_forward_progress =
+			    ((value >> Pm4::COMPUTE_PGM_RSRC1_FWD_PROGRESS_SHIFT) &
+			     Pm4::COMPUTE_PGM_RSRC1_FWD_PROGRESS_MASK) != 0u;
 			break;
 		case Pm4::COMPUTE_PGM_RSRC2:
 			cs_regs.scratch_en     = ((value >> Pm4::COMPUTE_PGM_RSRC2_SCRATCH_EN_SHIFT) &
@@ -1336,6 +1056,11 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_
 			cs_regs.lds_size       = (value >> Pm4::COMPUTE_PGM_RSRC2_LDS_SIZE_SHIFT) &
 			                         Pm4::COMPUTE_PGM_RSRC2_LDS_SIZE_MASK;
 			break;
+		case Pm4::COMPUTE_PGM_RSRC3:
+			cs_regs.shared_vgprs =
+			    (value >> Pm4::COMPUTE_PGM_RSRC3_SHARED_VGPRS_SHIFT) &
+			    Pm4::COMPUTE_PGM_RSRC3_SHARED_VGPRS_MASK;
+			break;
 		case Pm4::COMPUTE_NUM_THREAD_X: cs_regs.num_thread_x = value; break;
 		case Pm4::COMPUTE_NUM_THREAD_Y: cs_regs.num_thread_y = value; break;
 		case Pm4::COMPUTE_NUM_THREAD_Z: cs_regs.num_thread_z = value; break;
@@ -1343,14 +1068,8 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_
 		case Pm4::COMPUTE_START_Y:
 		case Pm4::COMPUTE_START_Z:
 		case Pm4::COMPUTE_RESOURCE_LIMITS:
-		case Pm4::COMPUTE_DESTINATION_EN_SE0:
-		case Pm4::COMPUTE_DESTINATION_EN_SE1:
 		case Pm4::COMPUTE_TMPRING_SIZE:
-		case Pm4::COMPUTE_DESTINATION_EN_SE2:
-		case Pm4::COMPUTE_DESTINATION_EN_SE3:
-		case Pm4::COMPUTE_PGM_RSRC3:
-		case Pm4::COMPUTE_SHADER_CHKSUM:
-		case Pm4::COMPUTE_DISPATCH_TUNNEL: HwShIgnoreComputeRegister(cmd_offset, value); break;
+		case Pm4::COMPUTE_PACE_ID: HwShIgnoreComputeRegister(cmd_offset, value); break;
 		default:
 			EXIT("unsupported compute SH register 0x%08" PRIx32 " = 0x%08" PRIx32 "\n", cmd_offset,
 			     value);
@@ -1361,6 +1080,7 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_
 
 KYTY_HW_SH_PARSER(HwShSetCsRegisters) {
 	auto reg_num = (cmd_id >> 16u) & 0x3fffu;
+	EXIT_NOT_IMPLEMENTED(reg_num == 0);
 
 	for (uint32_t i = 0; i < reg_num; i++) {
 		HwShSetCsRegister(cp, cmd_offset + i, buffer[i]);
@@ -1369,23 +1089,11 @@ KYTY_HW_SH_PARSER(HwShSetCsRegisters) {
 	return reg_num;
 }
 
-static uint32_t UserSgprWriteNum(uint32_t slot, uint32_t reg_num, const char* stage) {
+static uint32_t UserSgprWriteNum(uint32_t slot, uint32_t reg_num, uint32_t capacity,
+                                 const char* stage) {
 	EXIT_IF(stage == nullptr);
-
-	if (slot >= HW::UserSgprInfo::SGPRS_MAX) {
-		LOGF("\t %s user sgpr write starts out of range: slot = %" PRIu32 ", reg_num = %" PRIu32
-		     "\n",
-		     stage, slot, reg_num);
-		return 0;
-	}
-
-	const auto available = static_cast<uint32_t>(HW::UserSgprInfo::SGPRS_MAX) - slot;
-	if (reg_num > available) {
-		LOGF("\t %s user sgpr write truncated: slot = %" PRIu32 ", reg_num = %" PRIu32
-		     ", available = %" PRIu32 "\n",
-		     stage, slot, reg_num, available);
-		return available;
-	}
+	EXIT_NOT_IMPLEMENTED(capacity > HW::UserSgprInfo::SGPRS_MAX || slot >= capacity ||
+	                     reg_num > capacity - slot);
 
 	return reg_num;
 }
@@ -1397,23 +1105,7 @@ KYTY_HW_SH_PARSER(HwShSetCsUserSgpr) {
 	uint32_t slot = (cmd_offset - Pm4::COMPUTE_USER_DATA_0) / 1;
 
 	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "cs");
-
-	for (uint32_t i = 0; i < write_num; i++) {
-		cp.GetShCtx().SetCsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
-	}
-	cp.SetUserDataMarker(HW::UserSgprType::Unknown);
-
-	return reg_num;
-}
-
-KYTY_HW_SH_PARSER(HwShSetCsUserAccumSgpr) {
-	EXIT_NOT_IMPLEMENTED(cmd_offset < Pm4::COMPUTE_USER_ACCUM_0);
-
-	uint32_t slot = 16u + (cmd_offset - Pm4::COMPUTE_USER_ACCUM_0);
-
-	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "cs accum");
+	auto write_num = UserSgprWriteNum(slot, reg_num, 16u, "cs");
 
 	for (uint32_t i = 0; i < write_num; i++) {
 		cp.GetShCtx().SetCsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
@@ -1430,24 +1122,7 @@ KYTY_HW_SH_PARSER(HwShSetPsUserSgpr) {
 	uint32_t slot = (cmd_offset - Pm4::SPI_SHADER_USER_DATA_PS_0) / 1;
 
 	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "ps");
-
-	for (uint32_t i = 0; i < write_num; i++) {
-		cp.GetShCtx().SetPsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
-	}
-	cp.SetUserDataMarker(HW::UserSgprType::Unknown);
-
-	return reg_num;
-}
-
-KYTY_HW_SH_PARSER(HwShSetPsUserAccumSgpr) {
-	EXIT_NOT_IMPLEMENTED(!(cmd_offset >= Pm4::SPI_SHADER_USER_ACCUM_PS_0 &&
-	                       cmd_offset <= Pm4::SPI_SHADER_USER_ACCUM_PS_3));
-
-	uint32_t slot = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_PS_0);
-
-	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "ps accum");
+	auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "ps");
 
 	for (uint32_t i = 0; i < write_num; i++) {
 		cp.GetShCtx().SetPsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
@@ -1464,24 +1139,7 @@ KYTY_HW_SH_PARSER(HwShSetGsUserSgpr) {
 	uint32_t slot = (cmd_offset - Pm4::SPI_SHADER_USER_DATA_GS_0) / 1;
 
 	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "gs");
-
-	for (uint32_t i = 0; i < write_num; i++) {
-		cp.GetShCtx().SetGsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
-	}
-	cp.SetUserDataMarker(HW::UserSgprType::Unknown);
-
-	return reg_num;
-}
-
-KYTY_HW_SH_PARSER(HwShSetGsUserAccumSgpr) {
-	EXIT_NOT_IMPLEMENTED(!(cmd_offset >= Pm4::SPI_SHADER_USER_ACCUM_ESGS_0 &&
-	                       cmd_offset <= Pm4::SPI_SHADER_USER_ACCUM_ESGS_3));
-
-	uint32_t slot = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_ESGS_0);
-
-	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "gs accum");
+	auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "gs");
 
 	for (uint32_t i = 0; i < write_num; i++) {
 		cp.GetShCtx().SetGsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
@@ -1498,7 +1156,7 @@ KYTY_HW_SH_PARSER(HwShSetHsUserSgpr) {
 	uint32_t slot = (cmd_offset - Pm4::SPI_SHADER_USER_DATA_HS_0) / 1;
 
 	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "hs");
+	auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "hs");
 
 	for (uint32_t i = 0; i < write_num; i++) {
 		cp.GetShCtx().SetHsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
@@ -1508,18 +1166,27 @@ KYTY_HW_SH_PARSER(HwShSetHsUserSgpr) {
 	return reg_num;
 }
 
-KYTY_HW_SH_PARSER(HwShSetHsUserAccumSgpr) {
-	EXIT_NOT_IMPLEMENTED(!(cmd_offset >= Pm4::SPI_SHADER_USER_ACCUM_LSHS_0 &&
-	                       cmd_offset <= Pm4::SPI_SHADER_USER_ACCUM_LSHS_3));
-	uint32_t slot = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_LSHS_0);
+static bool HwShIsUserAccumulatorRange(uint32_t first, uint32_t count, uint32_t base) {
+	return first >= base && first - base < 4u && count <= 4u - (first - base);
+}
 
-	auto reg_num   = (cmd_id >> 16u) & 0x3fffu;
-	auto write_num = UserSgprWriteNum(slot, reg_num, "hs accum");
+static void HwShIgnoreUserAccumulatorRegister([[maybe_unused]] uint32_t cmd_offset,
+                                               uint32_t value) {
+	EXIT_NOT_IMPLEMENTED((value & ~0x7fu) != 0);
+}
 
-	for (uint32_t i = 0; i < write_num; i++) {
-		cp.GetShCtx().SetHsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
+KYTY_HW_SH_PARSER(HwShIgnoreUserAccumulator) {
+	const auto reg_num = (cmd_id >> 16u) & 0x3fffu;
+	const bool valid_range =
+	    HwShIsUserAccumulatorRange(cmd_offset, reg_num, Pm4::SPI_SHADER_USER_ACCUM_PS_0) ||
+	    HwShIsUserAccumulatorRange(cmd_offset, reg_num, Pm4::SPI_SHADER_USER_ACCUM_ESGS_0) ||
+	    HwShIsUserAccumulatorRange(cmd_offset, reg_num, Pm4::SPI_SHADER_USER_ACCUM_LSHS_0) ||
+	    HwShIsUserAccumulatorRange(cmd_offset, reg_num, Pm4::COMPUTE_USER_ACCUM_0);
+	EXIT_NOT_IMPLEMENTED(reg_num == 0 || !valid_range);
+
+	for (uint32_t i = 0; i < reg_num; i++) {
+		HwShIgnoreUserAccumulatorRegister(cmd_offset + i, buffer[i]);
 	}
-	cp.SetUserDataMarker(HW::UserSgprType::Unknown);
 
 	return reg_num;
 }
@@ -1536,6 +1203,7 @@ KYTY_HW_UC_PARSER(HwUcSetPrimitiveType) {
 }
 
 KYTY_HW_UC_PARSER(HwUcSetIndexType) {
+	EXIT_NOT_IMPLEMENTED(dw < KYTY_PM4_LEN(cmd_id));
 	EXIT_NOT_IMPLEMENTED(cmd_offset != Pm4::VGT_INDEX_TYPE);
 	cp.SetIndexType(buffer[0] & 0x3u);
 
@@ -1553,6 +1221,8 @@ static void HwUcIgnoreTextureGradientFactors([[maybe_unused]] uint32_t value) {}
 
 KYTY_HW_UC_PARSER(HwUcSetTextureGradientFactors) {
 	auto num_values = KYTY_PM4_LEN(cmd_id) - 2u;
+	EXIT_NOT_IMPLEMENTED(num_values == 0 || cmd_offset < Pm4::TEXTURE_GRADIENT_FACTORS ||
+	                     cmd_offset + num_values - 1u > Pm4::TEXTURE_GRADIENT_CONTROL);
 
 	for (uint32_t i = 0; i < num_values; i++) {
 		HwUcIgnoreTextureGradientFactors(buffer[i]);
@@ -1584,6 +1254,8 @@ static void HwUcIgnoreBorderColorTableAddr([[maybe_unused]] uint32_t cmd_offset,
 
 KYTY_HW_UC_PARSER(HwUcSetBorderColorTableAddr) {
 	auto num_values = KYTY_PM4_LEN(cmd_id) - 2u;
+	EXIT_NOT_IMPLEMENTED(num_values == 0 || cmd_offset < Pm4::TA_CS_BC_BASE_ADDR ||
+	                     cmd_offset + num_values - 1u > Pm4::TA_CS_BC_BASE_ADDR_HI);
 
 	for (uint32_t i = 0; i < num_values; i++) {
 		HwUcIgnoreBorderColorTableAddr(cmd_offset + i, buffer[i]);
@@ -1633,57 +1305,6 @@ KYTY_HW_UC_PARSER(HwUcSetGdsOaRegisters) {
 	return num_values;
 }
 
-static bool HwUcIsFakeRegister(uint32_t cmd_offset) {
-	switch (cmd_offset) {
-		case Pm4::FSR_EXTEND_SUBPIXEL_ROUNDING:
-		case Pm4::FSR_ALPHA_VALUE0:
-		case Pm4::FSR_ALPHA_VALUE1:
-		case Pm4::FSR_CONTROL_POINT0:
-		case Pm4::FSR_CONTROL_POINT1:
-		case Pm4::FSR_CONTROL_POINT2:
-		case Pm4::FSR_CONTROL_POINT3:
-		case Pm4::FSR_WINDOW0:
-		case Pm4::FSR_WINDOW1:
-		case Pm4::TEXTURE_GRADIENT_CONTROL:
-		case Pm4::MEMORY_MAPPING_MASK:
-		case Pm4::UC_NOP: return true;
-		default: return false;
-	}
-}
-
-static void HwUcIgnoreFakeRegister([[maybe_unused]] uint32_t cmd_offset,
-                                   [[maybe_unused]] uint32_t value) {}
-
-static bool HwUcTrySetFakeRegister(uint32_t cmd_offset, uint32_t value) {
-	if (!HwUcIsFakeRegister(cmd_offset)) {
-		return false;
-	}
-
-	if (cmd_offset != Pm4::UC_NOP) {
-		HwUcIgnoreFakeRegister(cmd_offset, value);
-	}
-
-	return true;
-}
-
-static bool HwUcTrySetFakeRegisterRange(uint32_t cmd_offset, const uint32_t* buffer,
-                                        uint32_t num_values) {
-	if (!HwUcIsFakeRegister(cmd_offset)) {
-		return false;
-	}
-
-	for (uint32_t i = 0; i < num_values; i++) {
-		auto reg = cmd_offset + i;
-		if (!HwUcTrySetFakeRegister(reg, buffer[i])) {
-			EXIT("unsupported fake UC register range at 0x%08" PRIx32 " + %" PRIu32
-			     ", value = 0x%08" PRIx32 "\n",
-			     cmd_offset, i, buffer[i]);
-		}
-	}
-
-	return true;
-}
-
 KYTY_CP_OP_PARSER(CpOpAcquireMem) {
 	KYTY_PROFILER_FUNCTION();
 
@@ -2500,16 +2121,9 @@ KYTY_CP_OP_PARSER(CpOpIndirectUcRegs) {
 		// 	           " -> 0x%08" PRIx32 "\n",
 		// 	           raw_cmd_offset, cmd_offset);
 		// }
-		if (HwUcTrySetFakeRegister(cmd_offset, value)) {
+		if (cmd_offset == Pm4::UC_NOP) {
 			continue;
 		}
-		if (cmd_offset < Pm4::CX_NUM) {
-			auto ctx_func = g_hw_ctx_indirect_func[cmd_offset & (Pm4::CX_NUM - 1)];
-			if (ctx_func != nullptr) {
-				ctx_func(cp, cmd_offset, value);
-				continue;
-			}
-		}
 		if (cmd_offset >= Pm4::UC_NUM) {
 			EXIT("unsupported indirect UC register offset 0x%08" PRIx32 " (raw 0x%08" PRIx32
 			     "), value = 0x%08" PRIx32 "\n",
@@ -2861,7 +2475,7 @@ KYTY_CP_OP_PARSER(CpOpSetUconfigReg) {
 	// 	           "\n",
 	// 	           raw_cmd_offset, cmd_offset);
 	// }
-	if (HwUcTrySetFakeRegisterRange(cmd_offset, buffer + 1, KYTY_PM4_LEN(cmd_id) - 2u)) {
+	if (cmd_offset == Pm4::UC_NOP) {
 		return KYTY_PM4_LEN(cmd_id) - 1u;
 	}
 	if (cmd_offset >= Pm4::UC_NUM) {
@@ -3051,27 +2665,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 		};
 	}
 
-	for (auto cmd_offset = Pm4::CB_COLOR0_BASE + 1; cmd_offset <= Pm4::CB_COLOR7_BASE + 1;
-	     cmd_offset += 15) {
-		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-			uint32_t       slot = (cmd_offset - (Pm4::CB_COLOR0_BASE + 1)) / 15;
-			HW::ColorPitch pitch;
-			pitch.pitch_div8_minus1       = value & 0x7ffu;
-			pitch.fmask_pitch_div8_minus1 = (value >> 20u) & 0x7ffu;
-			cp.GetCtx().SetColorPitch(slot, pitch);
-		};
-	}
-
-	for (auto cmd_offset = Pm4::CB_COLOR0_BASE + 2; cmd_offset <= Pm4::CB_COLOR7_BASE + 2;
-	     cmd_offset += 15) {
-		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-			uint32_t       slot = (cmd_offset - (Pm4::CB_COLOR0_BASE + 2)) / 15;
-			HW::ColorSlice slice;
-			slice.slice_div64_minus1 = value & 0x3fffffu;
-			cp.GetCtx().SetColorSlice(slot, slice);
-		};
-	}
-
 	for (auto cmd_offset = Pm4::CB_COLOR0_BASE_EXT; cmd_offset <= Pm4::CB_COLOR7_BASE_EXT;
 	     cmd_offset++) {
 		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
@@ -3111,14 +2704,11 @@ void GraphicsInitJmpTablesCxIndirect() {
 			info.blend_clamp              = KYTY_PM4_GET(value, CB_COLOR0_INFO, BLEND_CLAMP) != 0;
 			info.blend_bypass             = KYTY_PM4_GET(value, CB_COLOR0_INFO, BLEND_BYPASS) != 0;
 			info.round_mode               = KYTY_PM4_GET(value, CB_COLOR0_INFO, ROUND_MODE) != 0;
-			info.cmask_is_linear          = KYTY_PM4_GET(value, CB_COLOR0_INFO, CMASK_IS_LINEAR);
 			info.fmask_data_compression_disable =
 			    KYTY_PM4_GET(value, CB_COLOR0_INFO, FMASK_COMPRESSION_DISABLE) != 0;
 			info.fmask_one_frag_mode =
 			    KYTY_PM4_GET(value, CB_COLOR0_INFO, FMASK_COMPRESS_1FRAG_ONLY) != 0;
 			info.dcc_compression_enable = KYTY_PM4_GET(value, CB_COLOR0_INFO, DCC_ENABLE) != 0;
-			info.cmask_addr_type        = KYTY_PM4_GET(value, CB_COLOR0_INFO, CMASK_ADDR_TYPE);
-			info.alt_tile_mode          = KYTY_PM4_GET(value, CB_COLOR0_INFO, ALT_TILE_MODE) != 0;
 			cp.GetCtx().SetColorInfo(slot, info);
 		};
 	}
@@ -3130,10 +2720,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 			HW::ColorAttrib attrib;
 			attrib.force_dest_alpha_to_one =
 			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB, FORCE_DST_ALPHA_1) != 0;
-			attrib.tile_mode = static_cast<Prospero::TileMode>(
-			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB, TILE_MODE_INDEX));
-			attrib.fmask_tile_mode = static_cast<Prospero::TileMode>(
-			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB, FMASK_TILE_MODE_INDEX));
 			attrib.num_samples   = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB, NUM_SAMPLES);
 			attrib.num_fragments = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB, NUM_FRAGMENTS);
 			cp.GetCtx().SetColorAttrib(slot, attrib);
@@ -3151,17 +2737,21 @@ void GraphicsInitJmpTablesCxIndirect() {
 			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, KEY_CLEAR_ENABLE) != 0;
 			dcc.max_uncompressed_block_size =
 			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, MAX_UNCOMPRESSED_BLOCK_SIZE);
-			dcc.min_compressed_block_size =
-			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, MIN_COMPRESSED_BLOCK_SIZE);
 			dcc.max_compressed_block_size =
 			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, MAX_COMPRESSED_BLOCK_SIZE);
 			dcc.color_transform = KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, COLOR_TRANSFORM);
-			dcc.independent_64b_blocks =
-			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, INDEPENDENT_64B_BLOCKS) != 0;
 			dcc.data_write_on_dcc_clear_to_reg =
 			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, ENABLE_CONSTANT_ENCODE_REG_WRITE) != 0;
-			dcc.independent_128b_blocks =
+			const bool independent_64b =
+			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, INDEPENDENT_64B_BLOCKS) != 0;
+			const bool independent_128b =
 			    KYTY_PM4_GET(value, CB_COLOR0_DCC_CONTROL, INDEPENDENT_128B_BLOCKS) != 0;
+			EXIT_NOT_IMPLEMENTED(independent_64b && independent_128b);
+			dcc.independent_block_size =
+			    independent_64b
+			        ? HW::ColorDccControl::IndependentBlockSize::Bytes64
+			        : independent_128b ? HW::ColorDccControl::IndependentBlockSize::Bytes128
+			                           : HW::ColorDccControl::IndependentBlockSize::Disabled;
 			cp.GetCtx().SetColorDccControl(slot, dcc);
 		};
 	}
@@ -3177,16 +2767,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 		};
 	}
 
-	for (auto cmd_offset = Pm4::CB_COLOR0_CMASK + 1; cmd_offset <= Pm4::CB_COLOR7_BASE + 8;
-	     cmd_offset += 15) {
-		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-			uint32_t            slot = (cmd_offset - (Pm4::CB_COLOR0_CMASK + 1)) / 15;
-			HW::ColorCmaskSlice cmask_slice;
-			cmask_slice.slice_minus1 = value & 0x3fffu;
-			cp.GetCtx().SetColorCmaskSlice(slot, cmask_slice);
-		};
-	}
-
 	for (auto cmd_offset = Pm4::CB_COLOR0_CMASK_BASE_EXT;
 	     cmd_offset <= Pm4::CB_COLOR7_CMASK_BASE_EXT; cmd_offset++) {
 		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
@@ -3209,16 +2789,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 		};
 	}
 
-	for (auto cmd_offset = Pm4::CB_COLOR0_FMASK + 1; cmd_offset <= Pm4::CB_COLOR7_BASE + 10;
-	     cmd_offset += 15) {
-		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-			uint32_t            slot = (cmd_offset - (Pm4::CB_COLOR0_FMASK + 1)) / 15;
-			HW::ColorFmaskSlice fmask_slice;
-			fmask_slice.slice_minus1 = value & 0x3fffffu;
-			cp.GetCtx().SetColorFmaskSlice(slot, fmask_slice);
-		};
-	}
-
 	for (auto cmd_offset = Pm4::CB_COLOR0_FMASK_BASE_EXT;
 	     cmd_offset <= Pm4::CB_COLOR7_FMASK_BASE_EXT; cmd_offset++) {
 		g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
@@ -3292,9 +2862,15 @@ void GraphicsInitJmpTablesCxIndirect() {
 			attrib3.depth     = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, MIP0_DEPTH);
 			attrib3.tile_mode = static_cast<Prospero::TileMode>(
 			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, COLOR_SW_MODE));
-			attrib3.dimension          = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, RESOURCE_TYPE);
-			attrib3.cmask_pipe_aligned = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, CMASK_PIPE_ALIGNED);
-			attrib3.dcc_pipe_aligned   = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, DCC_PIPE_ALIGNED);
+			attrib3.dimension = KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, RESOURCE_TYPE);
+			const bool cmask_pipe_aligned =
+			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, CMASK_PIPE_ALIGNED) != 0;
+			const bool dcc_pipe_aligned =
+			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, DCC_PIPE_ALIGNED) != 0;
+			EXIT_NOT_IMPLEMENTED(cmask_pipe_aligned != dcc_pipe_aligned);
+			attrib3.metadata_pipe_aligned = cmask_pipe_aligned;
+			attrib3.write_vrs_rate_hint_to_cmask =
+			    KYTY_PM4_GET(value, CB_COLOR0_ATTRIB3, WRITE_VRS_RATE_HINT_TO_CMASK) != 0;
 			cp.GetCtx().SetColorAttrib3(slot, attrib3);
 		};
 	}
@@ -3722,23 +3298,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 		cp.GetCtx().SetDepthZInfo(HW::DepthZInfo::Decode(value));
 	};
 
-	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_INFO] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-		auto z                          = cp.GetCtx().GetDepthRenderTarget();
-		z.depth_info.addr5_swizzle_mask = KYTY_PM4_GET(value, DB_DEPTH_INFO, ADDR5_SWIZZLE_MASK);
-		z.depth_info.array_mode =
-		    (value >> Pm4::DB_DEPTH_INFO_ARRAY_MODE_SHIFT) & Pm4::DB_DEPTH_INFO_ARRAY_MODE_MASK;
-		z.depth_info.pipe_config =
-		    (value >> Pm4::DB_DEPTH_INFO_PIPE_CONFIG_SHIFT) & Pm4::DB_DEPTH_INFO_PIPE_CONFIG_MASK;
-		z.depth_info.bank_width =
-		    (value >> Pm4::DB_DEPTH_INFO_BANK_WIDTH_SHIFT) & Pm4::DB_DEPTH_INFO_BANK_WIDTH_MASK;
-		z.depth_info.bank_height =
-		    (value >> Pm4::DB_DEPTH_INFO_BANK_HEIGHT_SHIFT) & Pm4::DB_DEPTH_INFO_BANK_HEIGHT_MASK;
-		z.depth_info.macro_tile_aspect = KYTY_PM4_GET(value, DB_DEPTH_INFO, MACRO_TILE_ASPECT);
-		z.depth_info.num_banks =
-		    (value >> Pm4::DB_DEPTH_INFO_NUM_BANKS_SHIFT) & Pm4::DB_DEPTH_INFO_NUM_BANKS_MASK;
-		cp.GetCtx().SetDepthRenderTarget(z);
-	};
-
 	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_BOUNDS_MIN] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
 		HwCtxSetDepthBoundsRegister(cp, cmd_offset, value);
 	};
@@ -3820,8 +3379,8 @@ void GraphicsInitJmpTablesCxIndirect() {
 		cp.GetCtx().SetDepthHTileDataBase(base);
 	};
 
-	g_hw_ctx_indirect_func[Pm4::DB_HTILE_SURFACE] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-		HwCtxSetDepthHtileSurfaceRegister(cp, value);
+	g_hw_ctx_indirect_func[Pm4::DB_SHADING_RATE_ENCODING] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
+		HwCtxSetDepthShadingRateEncodingRegister(cp, value);
 	};
 
 	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_VIEW] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
@@ -3843,19 +3402,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 		r.valid = true;
 		cp.GetCtx().SetDepthDepthSizeXY(r);
 	};
-	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_SIZE] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-		auto target               = cp.GetCtx().GetDepthRenderTarget();
-		target.pitch_div8_minus1  = KYTY_PM4_GET(value, DB_DEPTH_SIZE, PITCH_TILE_MAX);
-		target.height_div8_minus1 = KYTY_PM4_GET(value, DB_DEPTH_SIZE, HEIGHT_TILE_MAX);
-		target.pitch_height_valid = true;
-		cp.GetCtx().SetDepthRenderTarget(target);
-	};
-	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_SLICE] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-		auto target               = cp.GetCtx().GetDepthRenderTarget();
-		target.slice_div64_minus1 = KYTY_PM4_GET(value, DB_DEPTH_SLICE, SLICE_TILE_MAX);
-		cp.GetCtx().SetDepthRenderTarget(target);
-	};
-
 	g_hw_ctx_indirect_func[Pm4::DB_DEPTH_CLEAR] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
 		cp.GetCtx().SetDepthClearValue(*reinterpret_cast<const float*>(&value));
 	};
@@ -3970,9 +3516,6 @@ void GraphicsInitJmpTablesCxIndirect() {
 	};
 	g_hw_ctx_indirect_func[Pm4::PA_SC_CONSERVATIVE_RASTERIZATION_CNTL] =
 	    [](KYTY_HW_CTX_INDIRECT_ARGS) { HwCtxIgnorePaScExtendedControl(cmd_offset, value); };
-	g_hw_ctx_indirect_func[Pm4::PA_SC_NGG_MODE_CNTL] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
-		HwCtxIgnorePaScExtendedControl(cmd_offset, value);
-	};
 	g_hw_ctx_indirect_func[Pm4::DB_ALPHA_TO_MASK] = [](KYTY_HW_CTX_INDIRECT_ARGS) {
 		HwCtxIgnoreAlphaToMaskRegister(value);
 	};
@@ -4000,18 +3543,6 @@ void GraphicsInitJmpTablesShIndirect() {
 	g_hw_sh_indirect_func[Pm4::COMPUTE_PGM_HI] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_TBA_LO] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_TBA_HI] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_TMA_LO] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_TMA_HI] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
 	g_hw_sh_indirect_func[Pm4::COMPUTE_PGM_RSRC1] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
@@ -4039,28 +3570,13 @@ void GraphicsInitJmpTablesShIndirect() {
 	g_hw_sh_indirect_func[Pm4::COMPUTE_RESOURCE_LIMITS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_DESTINATION_EN_SE0] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_DESTINATION_EN_SE1] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
 	g_hw_sh_indirect_func[Pm4::COMPUTE_TMPRING_SIZE] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_DESTINATION_EN_SE2] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_DESTINATION_EN_SE3] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
 	g_hw_sh_indirect_func[Pm4::COMPUTE_PGM_RSRC3] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_SHADER_CHKSUM] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShSetCsRegister(cp, cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::COMPUTE_DISPATCH_TUNNEL] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::COMPUTE_PACE_ID] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShSetCsRegister(cp, cmd_offset, value);
 	};
 
@@ -4071,11 +3587,9 @@ void GraphicsInitJmpTablesShIndirect() {
 			cp.SetUserDataMarker(HW::UserSgprType::Unknown);
 		};
 	}
-	for (uint32_t slot = 0; Pm4::COMPUTE_USER_ACCUM_0 + slot < Pm4::COMPUTE_USER_DATA_0; slot++) {
+	for (uint32_t slot = 0; slot < 4; slot++) {
 		g_hw_sh_indirect_func[Pm4::COMPUTE_USER_ACCUM_0 + slot] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-			auto sgpr = 16u + (cmd_offset - Pm4::COMPUTE_USER_ACCUM_0);
-			cp.GetShCtx().SetCsUserSgpr(sgpr, value, cp.GetUserDataMarker());
-			cp.SetUserDataMarker(HW::UserSgprType::Unknown);
+			HwShIgnoreUserAccumulatorRegister(cmd_offset, value);
 		};
 	}
 	for (uint32_t slot = 0; slot < 32; slot++) {
@@ -4101,45 +3615,27 @@ void GraphicsInitJmpTablesShIndirect() {
 	for (uint32_t slot = 0; slot < 4; slot++) {
 		g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_ACCUM_PS_0 + slot] =
 		    [](KYTY_HW_SH_INDIRECT_ARGS) {
-			    auto sgpr = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_PS_0);
-			    cp.GetShCtx().SetPsUserSgpr(sgpr, value, cp.GetUserDataMarker());
-			    cp.SetUserDataMarker(HW::UserSgprType::Unknown);
+			    HwShIgnoreUserAccumulatorRegister(cmd_offset, value);
 		    };
 		g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_ACCUM_ESGS_0 + slot] =
 		    [](KYTY_HW_SH_INDIRECT_ARGS) {
-			    auto sgpr = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_ESGS_0);
-			    cp.GetShCtx().SetGsUserSgpr(sgpr, value, cp.GetUserDataMarker());
-			    cp.SetUserDataMarker(HW::UserSgprType::Unknown);
+			    HwShIgnoreUserAccumulatorRegister(cmd_offset, value);
 		    };
 		g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_ACCUM_LSHS_0 + slot] =
 		    [](KYTY_HW_SH_INDIRECT_ARGS) {
-			    auto sgpr = 16u + (cmd_offset - Pm4::SPI_SHADER_USER_ACCUM_LSHS_0);
-			    cp.GetShCtx().SetHsUserSgpr(sgpr, value, cp.GetUserDataMarker());
-			    cp.SetUserDataMarker(HW::UserSgprType::Unknown);
+			    HwShIgnoreUserAccumulatorRegister(cmd_offset, value);
 		    };
 	}
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_TBA_LO_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PACE_ID_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC3_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC4_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PACE_ID_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_TMA_LO_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_TMA_HI_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_REQ_CTRL_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC4_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC3_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
@@ -4148,13 +3644,7 @@ void GraphicsInitJmpTablesShIndirect() {
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_REQ_CTRL_ESGS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC4_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC3_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
+	g_hw_sh_indirect_func[Pm4::SPI_GRAPHICS_SHADER_CONTROL_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_ADDR_LO_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
@@ -4163,9 +3653,6 @@ void GraphicsInitJmpTablesShIndirect() {
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_ADDR_HI_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HwShIgnoreShaderRegister(cmd_offset, value);
 	};
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_REQ_CTRL_LSHS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HwShIgnoreShaderRegister(cmd_offset, value);
-	};
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_LO_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		auto base = cp.GetShCtx().GetVs().hs_regs.data_addr;
 		base &= 0xFFFFFF00000000FFull;
@@ -4180,10 +3667,6 @@ void GraphicsInitJmpTablesShIndirect() {
 		cp.GetShCtx().SetHsShaderBase(base);
 	};
 
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_CHKSUM_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		cp.GetShCtx().SetHsShaderChksum(value);
-	};
-
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC1_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HW::HsShaderResource1 r1;
 		r1.vgprs      = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, VGPRS);
@@ -4224,32 +3707,6 @@ void GraphicsInitJmpTablesShIndirect() {
 		cp.GetShCtx().SetLsShaderBase(base);
 	};
 
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC1_LS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HW::VsShaderResource1 r1;
-		r1.vgprs                = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, VGPRS);
-		r1.sgprs                = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, SGPRS);
-		r1.priority             = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, PRIORITY);
-		r1.float_mode           = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FLOAT_MODE);
-		r1.dx10_clamp           = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, DX10_CLAMP) != 0;
-		r1.ieee_mode            = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, IEEE_MODE) != 0;
-		r1.vgpr_component_count = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, VGPR_COMP_CNT);
-		r1.cu_group_enable = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, CU_GROUP_ENABLE) != 0;
-		r1.require_forward_progress =
-		    KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FWD_PROGRESS) != 0;
-		r1.fp16_overflow = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FP16_OVFL) != 0;
-		cp.GetShCtx().SetLsShaderResource1(r1);
-	};
-
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC2_LS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		HW::VsShaderResource2 r2;
-		r2.scratch_en        = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SCRATCH_EN) != 0;
-		r2.user_sgpr         = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, USER_SGPR) +
-		                       (KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, USER_SGPR_MSB) << 5u);
-		r2.offchip_lds       = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, OC_LDS_EN) != 0;
-		r2.streamout_enabled = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SO_EN) != 0;
-		r2.shared_vgprs      = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SHARED_VGPR_CNT);
-		cp.GetShCtx().SetLsShaderResource2(r2);
-	};
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_LO_ES] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		auto base = cp.GetShCtx().GetVs().es_regs.data_addr;
 		base &= 0xFFFFFF00000000FFull;
@@ -4278,14 +3735,9 @@ void GraphicsInitJmpTablesShIndirect() {
 		cp.GetShCtx().SetGsShaderBase(base);
 	};
 
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_CHKSUM_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		cp.GetShCtx().SetGsShaderChksum(value);
-	};
-
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC1_GS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HW::GsShaderResource1 r1;
 		r1.vgprs           = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, VGPRS);
-		r1.sgprs           = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, SGPRS);
 		r1.priority        = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, PRIORITY);
 		r1.float_mode      = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, FLOAT_MODE);
 		r1.dx10_clamp      = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, DX10_CLAMP) != 0;
@@ -4326,14 +3778,9 @@ void GraphicsInitJmpTablesShIndirect() {
 		cp.GetShCtx().SetPsShaderBase(base);
 	};
 
-	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_CHKSUM_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
-		cp.GetShCtx().SetPsShaderChksum(value);
-	};
-
 	g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC1_PS] = [](KYTY_HW_SH_INDIRECT_ARGS) {
 		HW::PsShaderResource1 r1;
 		r1.vgprs            = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_PS, VGPRS);
-		r1.sgprs            = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_PS, SGPRS);
 		r1.priority         = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_PS, PRIORITY);
 		r1.float_mode       = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_PS, FLOAT_MODE);
 		r1.dx10_clamp       = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_PS, DX10_CLAMP) != 0;
@@ -4371,12 +3818,6 @@ void GraphicsInitJmpTablesUcIndirect() {
 		r.vertex_group_size    = KYTY_PM4_GET(value, GE_CNTL, VERT_GRP_SIZE);
 		cp.GetUcfg().SetGeControl(r);
 	};
-	g_hw_uc_indirect_func[Pm4::GE_PC_ALLOC] = [](KYTY_HW_UC_INDIRECT_ARGS) {
-		(void)cp;
-		(void)cmd_offset;
-		(void)value;
-	};
-
 	g_hw_uc_indirect_func[Pm4::GE_USER_VGPR_EN] = [](KYTY_HW_UC_INDIRECT_ARGS) {
 		HW::GeUserVgprEn r;
 		r.vgpr1 = KYTY_PM4_GET(value, GE_USER_VGPR_EN, EN_USER_VGPR1) != 0;
@@ -4398,6 +3839,9 @@ void GraphicsInitJmpTablesUcIndirect() {
 	g_hw_uc_indirect_func[Pm4::TEXTURE_GRADIENT_FACTORS] = [](KYTY_HW_UC_INDIRECT_ARGS) {
 		HwUcIgnoreTextureGradientFactors(value);
 	};
+	g_hw_uc_indirect_func[Pm4::TEXTURE_GRADIENT_CONTROL] = [](KYTY_HW_UC_INDIRECT_ARGS) {
+		HwUcIgnoreTextureGradientFactors(value);
+	};
 	g_hw_uc_indirect_func[Pm4::IA_MULTI_VGT_PARAM] = [](KYTY_HW_UC_INDIRECT_ARGS) {
 		HwUcIgnoreIaMultiVgtParam(value);
 	};
diff --git a/src/graphics/guest_gpu/hardwareContext.h b/src/graphics/guest_gpu/hardwareContext.h
index e1a2f974d..5a5f2ffa5 100644
--- a/src/graphics/guest_gpu/hardwareContext.h
+++ b/src/graphics/guest_gpu/hardwareContext.h
@@ -11,15 +11,6 @@ struct ColorBase {
 	uint64_t addr = 0;
 };
 
-struct ColorPitch {
-	uint32_t pitch_div8_minus1       = 0;
-	uint32_t fmask_pitch_div8_minus1 = 0;
-};
-
-struct ColorSlice {
-	uint32_t slice_div64_minus1 = 0;
-};
-
 struct ColorView {
 	uint32_t base_array_slice_index = 0;
 	uint32_t last_array_slice_index = 0;
@@ -36,20 +27,15 @@ struct ColorInfo {
 	bool                    blend_clamp                    = false;
 	bool                    blend_bypass                   = false;
 	bool                    round_mode                     = false;
-	uint32_t                cmask_is_linear                = 0;
-	uint32_t                cmask_addr_type                = 0;
-	bool                    alt_tile_mode                  = false;
 	Prospero::ChannelLayout format                         = Prospero::ChannelLayout::kInvalid;
 	Prospero::ChannelType   channel_type                   = Prospero::ChannelType::kUNorm;
 	Prospero::ChannelOrder  channel_order                  = Prospero::ChannelOrder::kStandard;
 };
 
 struct ColorAttrib {
-	bool               force_dest_alpha_to_one = false;
-	Prospero::TileMode tile_mode               = Prospero::TileMode::kLinear;
-	Prospero::TileMode fmask_tile_mode         = Prospero::TileMode::kLinear;
-	uint32_t           num_samples             = 0;
-	uint32_t           num_fragments           = 0;
+	bool     force_dest_alpha_to_one = false;
+	uint32_t num_samples             = 0;
+	uint32_t num_fragments           = 0;
 };
 
 struct ColorAttrib2 {
@@ -59,41 +45,33 @@ struct ColorAttrib2 {
 };
 
 struct ColorAttrib3 {
-	uint32_t           depth              = 0;
-	Prospero::TileMode tile_mode          = Prospero::TileMode::kLinear;
-	uint32_t           dimension          = 0;
-	bool               cmask_pipe_aligned = false;
-	bool               dcc_pipe_aligned   = false;
+	uint32_t           depth                        = 0;
+	Prospero::TileMode tile_mode                    = Prospero::TileMode::kRenderTarget;
+	uint32_t           dimension                    = 0;
+	bool               metadata_pipe_aligned        = false;
+	bool               write_vrs_rate_hint_to_cmask = false;
 };
 
 struct ColorDccControl {
-	uint32_t max_uncompressed_block_size    = 0;
-	uint32_t max_compressed_block_size      = 0;
-	uint32_t min_compressed_block_size      = 0;
-	uint32_t color_transform                = 0;
-	bool     dcc_clear_key_enable           = false;
-	bool     overwrite_combiner_disable     = false;
-	bool     independent_64b_blocks         = false;
-	bool     independent_128b_blocks        = false;
-	bool     data_write_on_dcc_clear_to_reg = false;
+	enum class IndependentBlockSize : uint8_t { Disabled, Bytes64, Bytes128 };
+
+	uint32_t             max_uncompressed_block_size    = 2;
+	uint32_t             max_compressed_block_size      = 2;
+	uint32_t             color_transform                = 0;
+	bool                 dcc_clear_key_enable           = false;
+	bool                 overwrite_combiner_disable     = false;
+	IndependentBlockSize independent_block_size         = IndependentBlockSize::Disabled;
+	bool                 data_write_on_dcc_clear_to_reg = false;
 };
 
 struct ColorCmask {
 	uint64_t addr = 0;
 };
 
-struct ColorCmaskSlice {
-	uint32_t slice_minus1 = 0;
-};
-
 struct ColorFmask {
 	uint64_t addr = 0;
 };
 
-struct ColorFmaskSlice {
-	uint32_t slice_minus1 = 0;
-};
-
 struct ColorClearWord0 {
 	uint32_t word0 = 0;
 };
@@ -106,15 +84,8 @@ struct ColorDccAddr {
 	uint64_t addr = 0;
 };
 
-struct ColorSize {
-	uint32_t width  = 0;
-	uint32_t height = 0;
-};
-
 struct RenderTarget {
 	ColorBase       base;
-	ColorPitch      pitch;
-	ColorSlice      slice;
 	ColorView       view;
 	ColorInfo       info;
 	ColorAttrib     attrib;
@@ -122,13 +93,10 @@ struct RenderTarget {
 	ColorAttrib3    attrib3;
 	ColorDccControl dcc;
 	ColorCmask      cmask;
-	ColorCmaskSlice cmask_slice;
 	ColorFmask      fmask;
-	ColorFmaskSlice fmask_slice;
 	ColorClearWord0 clear_word0;
 	ColorClearWord1 clear_word1;
 	ColorDccAddr    dcc_addr;
-	ColorSize       size;
 };
 
 struct DepthZInfo {
@@ -136,7 +104,7 @@ struct DepthZInfo {
 	uint32_t                                    num_samples = 0;
 	Prospero::TextureCompatiblePlaneCompression texture_compatibility =
 	    Prospero::TextureCompatiblePlaneCompression::kDisable;
-	Prospero::ZCompareBase z_compare_base     = Prospero::ZCompareBase::kZMin;
+	Prospero::ZCompareBase z_compare_base     = Prospero::ZCompareBase::kZMax;
 	bool                   htile_acceleration = false;
 	bool                   expclear_enabled   = false;
 	bool                   partially_resident = false;
@@ -171,7 +139,7 @@ struct DepthStencilInfo {
 	Prospero::TextureCompatibleStencil texture_compatibility =
 	    Prospero::TextureCompatibleStencil::kDisable;
 	bool expclear_enabled       = false;
-	bool htile_stencil_disabled = false;
+	bool htile_stencil_disabled = true;
 	bool partially_resident     = false;
 
 	[[nodiscard]] static DepthStencilInfo Decode(uint32_t value) {
@@ -194,16 +162,6 @@ struct DepthStencilInfo {
 	}
 };
 
-struct DepthRenderTargetDepthInfo {
-	uint32_t addr5_swizzle_mask = 0;
-	uint32_t array_mode         = 0;
-	uint32_t pipe_config        = 0;
-	uint32_t bank_width         = 0;
-	uint32_t bank_height        = 0;
-	uint32_t macro_tile_aspect  = 0;
-	uint32_t num_banks          = 0;
-};
-
 struct DepthDepthView {
 	uint32_t slice_start           = 0;
 	uint32_t slice_max             = 0;
@@ -218,36 +176,18 @@ struct DepthDepthSizeXY {
 	bool     valid = false;
 };
 
-struct DepthRenderTargetHTileSurface {
-	uint32_t linear                  = 0;
-	uint32_t full_cache              = 0;
-	uint32_t htile_uses_preload_win  = 0;
-	uint32_t preload                 = 0;
-	uint32_t prefetch_width          = 0;
-	uint32_t prefetch_height         = 0;
-	uint32_t dst_outside_zero_to_one = 0;
-};
-
 struct DepthRenderTarget {
-	DepthZInfo                    z_info;
-	DepthStencilInfo              stencil_info;
-	DepthDepthView                depth_view;
-	DepthDepthSizeXY              size;
-	DepthRenderTargetDepthInfo    depth_info;
-	DepthRenderTargetHTileSurface htile_surface;
+	DepthZInfo       z_info;
+	DepthStencilInfo stencil_info;
+	DepthDepthView   depth_view;
+	DepthDepthSizeXY size;
 
 	uint64_t z_read_base_addr        = 0;
 	uint64_t stencil_read_base_addr  = 0;
 	uint64_t z_write_base_addr       = 0;
 	uint64_t stencil_write_base_addr = 0;
-	uint32_t pitch_div8_minus1       = 0;
-	uint32_t height_div8_minus1      = 0;
-	bool     pitch_height_valid      = false;
-	uint32_t slice_div64_minus1      = 0;
 	uint64_t htile_data_base_addr    = 0;
-	uint32_t width                   = 0;
-	uint32_t height                  = 0;
-	bool     width_height_valid      = false;
+	uint8_t  shading_rate_encoding   = 0;
 };
 
 struct RenderControl {
@@ -256,6 +196,8 @@ struct RenderControl {
 	bool    resummarize_enable       = false;
 	bool    stencil_compress_disable = false;
 	bool    depth_compress_disable   = false;
+	bool    copy_depth_to_color      = false;
+	bool    copy_stencil_to_color    = false;
 	bool    copy_centroid            = false;
 	uint8_t copy_sample              = 0;
 };
@@ -299,16 +241,14 @@ struct ClipControl {
 };
 
 struct DepthControl {
-	bool    stencil_enable                     = false;
-	bool    z_enable                           = false;
-	bool    z_write_enable                     = false;
-	bool    depth_bounds_enable                = false;
-	uint8_t zfunc                              = 0;
-	bool    backface_enable                    = false;
-	uint8_t stencilfunc                        = 0;
-	uint8_t stencilfunc_bf                     = 0;
-	bool    color_writes_on_depth_fail_enable  = false;
-	bool    color_writes_on_depth_pass_disable = false;
+	bool    stencil_enable      = false;
+	bool    z_enable            = false;
+	bool    z_write_enable      = false;
+	bool    depth_bounds_enable = false;
+	uint8_t zfunc               = 0;
+	bool    backface_enable     = false;
+	uint8_t stencilfunc         = 0;
+	uint8_t stencilfunc_bf      = 0;
 };
 
 struct StencilControl {
@@ -468,27 +408,6 @@ struct ScreenViewport {
 	bool     clip_rect_window_offset_enable[4]    = {};
 };
 
-struct VsShaderResource1 {
-	uint8_t vgprs                    = 0;
-	uint8_t sgprs                    = 0;
-	uint8_t priority                 = 0;
-	uint8_t float_mode               = 0;
-	bool    dx10_clamp               = false;
-	bool    ieee_mode                = false;
-	uint8_t vgpr_component_count     = 0;
-	bool    cu_group_enable          = false;
-	bool    require_forward_progress = false;
-	bool    fp16_overflow            = false;
-};
-
-struct VsShaderResource2 {
-	bool    scratch_en        = false;
-	uint8_t user_sgpr         = 0;
-	bool    offchip_lds       = false;
-	bool    streamout_enabled = false;
-	uint8_t shared_vgprs      = 0;
-};
-
 struct HsShaderResource1 {
 	uint8_t vgprs                     = 0;
 	uint8_t priority                  = 0;
@@ -511,7 +430,6 @@ struct HsShaderResource2 {
 
 struct PsShaderResource1 {
 	uint8_t vgprs                    = 0;
-	uint8_t sgprs                    = 0;
 	uint8_t priority                 = 0;
 	uint8_t float_mode               = 0;
 	bool    dx10_clamp               = false;
@@ -535,7 +453,6 @@ struct PsStageRegisters {
 	uint64_t          data_addr = 0;
 	PsShaderResource1 rsrc1;
 	PsShaderResource2 rsrc2;
-	uint64_t          chksum = 0;
 };
 
 struct CsStageRegisters {
@@ -545,12 +462,13 @@ struct CsStageRegisters {
 	uint32_t num_thread_y              = 0;
 	uint32_t num_thread_z              = 0;
 	uint8_t  vgprs                     = 0;
-	uint8_t  sgprs                     = 0;
+	uint8_t  priority                  = 0;
 	uint8_t  float_mode                = 0;
 	bool     dx10_clamp                = false;
+	bool     debug_mode                = false;
 	bool     ieee_mode                 = false;
+	bool     require_forward_progress  = false;
 	bool     fp16_overflow             = false;
-	bool     bulky                     = false;
 	bool     threadgroup_configuration = false;
 	uint8_t  wave_size                 = 64;
 	bool     scratch_en                = false;
@@ -561,6 +479,7 @@ struct CsStageRegisters {
 	bool     tg_size_en                = false;
 	uint8_t  tidig_comp_cnt            = 0;
 	uint16_t lds_size                  = 0;
+	uint8_t  shared_vgprs              = 0;
 };
 
 struct EsStageRegisters {
@@ -568,21 +487,17 @@ struct EsStageRegisters {
 };
 
 struct LsStageRegisters {
-	uint64_t          data_addr = 0;
-	VsShaderResource1 rsrc1;
-	VsShaderResource2 rsrc2;
+	uint64_t data_addr = 0;
 };
 
 struct HsStageRegisters {
 	uint64_t          data_addr = 0;
 	HsShaderResource1 rsrc1;
 	HsShaderResource2 rsrc2;
-	uint64_t          chksum = 0;
 };
 
 struct GsShaderResource1 {
 	uint8_t vgprs                     = 0;
-	uint8_t sgprs                     = 0;
 	uint8_t priority                  = 0;
 	uint8_t float_mode                = 0;
 	bool    dx10_clamp                = false;
@@ -608,7 +523,6 @@ struct GsStageRegisters {
 	uint64_t          data_addr = 0;
 	GsShaderResource1 rsrc1;
 	GsShaderResource2 rsrc2;
-	uint64_t          chksum = 0;
 };
 
 struct ShaderRegisters {
@@ -664,8 +578,7 @@ struct ShaderRegisters {
 enum class UserSgprType { Unknown, Region, Vsharp };
 
 struct UserSgprInfo {
-	// Changed from 16 to 64
-	static constexpr int SGPRS_MAX = 64;
+	static constexpr int SGPRS_MAX = 32;
 
 	uint32_t     value[SGPRS_MAX] = {0};
 	UserSgprType type[SGPRS_MAX]  = {};
@@ -712,12 +625,6 @@ public:
 	void Reset() { *this = Context(); }
 
 	void SetColorBase(uint32_t slot, const ColorBase& base) { m_render_targets[slot].base = base; }
-	void SetColorPitch(uint32_t slot, const ColorPitch& pitch) {
-		m_render_targets[slot].pitch = pitch;
-	}
-	void SetColorSlice(uint32_t slot, const ColorSlice& slice) {
-		m_render_targets[slot].slice = slice;
-	}
 	void SetColorView(uint32_t slot, const ColorView& view) { m_render_targets[slot].view = view; }
 	void SetColorInfo(uint32_t slot, const ColorInfo& info) { m_render_targets[slot].info = info; }
 	void SetColorAttrib(uint32_t slot, const ColorAttrib& attrib) {
@@ -735,15 +642,9 @@ public:
 	void SetColorCmask(uint32_t slot, const ColorCmask& cmask) {
 		m_render_targets[slot].cmask = cmask;
 	}
-	void SetColorCmaskSlice(uint32_t slot, const ColorCmaskSlice& cmask_slice) {
-		m_render_targets[slot].cmask_slice = cmask_slice;
-	}
 	void SetColorFmask(uint32_t slot, const ColorFmask& fmask) {
 		m_render_targets[slot].fmask = fmask;
 	}
-	void SetColorFmaskSlice(uint32_t slot, const ColorFmaskSlice& fmask_slice) {
-		m_render_targets[slot].fmask_slice = fmask_slice;
-	}
 	void SetColorClearWord0(uint32_t slot, const ColorClearWord0& clear_word0) {
 		m_render_targets[slot].clear_word0 = clear_word0;
 	}
@@ -753,7 +654,6 @@ public:
 	void SetColorDccAddr(uint32_t slot, const ColorDccAddr& dcc_addr) {
 		m_render_targets[slot].dcc_addr = dcc_addr;
 	}
-	void SetColorSize(uint32_t slot, const ColorSize& size) { m_render_targets[slot].size = size; }
 	[[nodiscard]] const RenderTarget& GetRenderTarget(uint32_t slot) const {
 		return m_render_targets[slot];
 	}
@@ -1072,21 +972,16 @@ public:
 
 	void SetEsShaderBase(uint64_t addr) { m_vs.es_regs.data_addr = addr; }
 	void SetLsShaderBase(uint64_t addr) { m_vs.ls_regs.data_addr = addr; }
-	void SetLsShaderResource1(const VsShaderResource1& rsrc1) { m_vs.ls_regs.rsrc1 = rsrc1; }
-	void SetLsShaderResource2(const VsShaderResource2& rsrc2) { m_vs.ls_regs.rsrc2 = rsrc2; }
 	void SetHsShaderBase(uint64_t addr) { m_vs.hs_regs.data_addr = addr; }
 	void SetHsShaderResource1(const HsShaderResource1& rsrc1) { m_vs.hs_regs.rsrc1 = rsrc1; }
 	void SetHsShaderResource2(const HsShaderResource2& rsrc2) { m_vs.hs_regs.rsrc2 = rsrc2; }
-	void SetHsShaderChksum(uint32_t value) { m_vs.hs_regs.chksum = value; }
 	void SetGsShaderBase(uint64_t addr) { m_vs.gs_regs.data_addr = addr; }
 	void SetGsShaderResource1(const GsShaderResource1& rsrc1) { m_vs.gs_regs.rsrc1 = rsrc1; }
 	void SetGsShaderResource2(const GsShaderResource2& rsrc2) { m_vs.gs_regs.rsrc2 = rsrc2; }
-	void SetGsShaderChksum(uint32_t value) { m_vs.gs_regs.chksum = value; }
 
 	void SetPsShaderBase(uint64_t addr) { m_ps.ps_regs.data_addr = addr; }
 	void SetPsShaderResource1(const PsShaderResource1& rsrc1) { m_ps.ps_regs.rsrc1 = rsrc1; }
 	void SetPsShaderResource2(const PsShaderResource2& rsrc2) { m_ps.ps_regs.rsrc2 = rsrc2; }
-	void SetPsShaderChksum(uint32_t value) { m_ps.ps_regs.chksum = value; }
 
 	void SetCsShader(const CsStageRegisters& cs_regs) { m_cs.cs_regs = cs_regs; }
 	void SetCsWaveSize(uint8_t wave_size) { m_cs.cs_regs.wave_size = wave_size; }
diff --git a/src/graphics/guest_gpu/pm4.h b/src/graphics/guest_gpu/pm4.h
index 16e0e5276..7cce9ff63 100644
--- a/src/graphics/guest_gpu/pm4.h
+++ b/src/graphics/guest_gpu/pm4.h
@@ -98,6 +98,10 @@ constexpr uint32_t DB_RENDER_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT       = 0;
 constexpr uint32_t DB_RENDER_CONTROL_DEPTH_CLEAR_ENABLE_MASK        = 0x1;
 constexpr uint32_t DB_RENDER_CONTROL_STENCIL_CLEAR_ENABLE_SHIFT     = 1;
 constexpr uint32_t DB_RENDER_CONTROL_STENCIL_CLEAR_ENABLE_MASK      = 0x1;
+constexpr uint32_t DB_RENDER_CONTROL_COPY_DEPTH_TO_COLOR_SHIFT      = 2;
+constexpr uint32_t DB_RENDER_CONTROL_COPY_DEPTH_TO_COLOR_MASK       = 0x1;
+constexpr uint32_t DB_RENDER_CONTROL_COPY_STENCIL_TO_COLOR_SHIFT    = 3;
+constexpr uint32_t DB_RENDER_CONTROL_COPY_STENCIL_TO_COLOR_MASK     = 0x1;
 constexpr uint32_t DB_RENDER_CONTROL_RESUMMARIZE_ENABLE_SHIFT       = 4;
 constexpr uint32_t DB_RENDER_CONTROL_RESUMMARIZE_ENABLE_MASK        = 0x1;
 constexpr uint32_t DB_RENDER_CONTROL_STENCIL_COMPRESS_DISABLE_SHIFT = 5;
@@ -163,22 +167,6 @@ constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK  = 0xFFFF;
 
 constexpr uint32_t DB_DFSM_CONTROL = 0xE;
 
-constexpr uint32_t DB_DEPTH_INFO                          = 0xF;
-constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_SHIFT = 0;
-constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_MASK  = 0xF;
-constexpr uint32_t DB_DEPTH_INFO_ARRAY_MODE_SHIFT         = 4;
-constexpr uint32_t DB_DEPTH_INFO_ARRAY_MODE_MASK          = 0xF;
-constexpr uint32_t DB_DEPTH_INFO_PIPE_CONFIG_SHIFT        = 8;
-constexpr uint32_t DB_DEPTH_INFO_PIPE_CONFIG_MASK         = 0x1F;
-constexpr uint32_t DB_DEPTH_INFO_BANK_WIDTH_SHIFT         = 13;
-constexpr uint32_t DB_DEPTH_INFO_BANK_WIDTH_MASK          = 0x3;
-constexpr uint32_t DB_DEPTH_INFO_BANK_HEIGHT_SHIFT        = 15;
-constexpr uint32_t DB_DEPTH_INFO_BANK_HEIGHT_MASK         = 0x3;
-constexpr uint32_t DB_DEPTH_INFO_MACRO_TILE_ASPECT_SHIFT  = 17;
-constexpr uint32_t DB_DEPTH_INFO_MACRO_TILE_ASPECT_MASK   = 0x3;
-constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_SHIFT          = 19;
-constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_MASK           = 0x3;
-
 constexpr uint32_t DB_Z_INFO                               = 0x10;
 constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT                  = 0;
 constexpr uint32_t DB_Z_INFO_FORMAT_MASK                   = 0x3;
@@ -222,16 +210,6 @@ constexpr uint32_t DB_STENCIL_READ_BASE  = 0x13;
 constexpr uint32_t DB_Z_WRITE_BASE       = 0x14;
 constexpr uint32_t DB_STENCIL_WRITE_BASE = 0x15;
 
-constexpr uint32_t DB_DEPTH_SIZE                       = 0x16;
-constexpr uint32_t DB_DEPTH_SIZE_PITCH_TILE_MAX_SHIFT  = 0;
-constexpr uint32_t DB_DEPTH_SIZE_PITCH_TILE_MAX_MASK   = 0x7FF;
-constexpr uint32_t DB_DEPTH_SIZE_HEIGHT_TILE_MAX_SHIFT = 11;
-constexpr uint32_t DB_DEPTH_SIZE_HEIGHT_TILE_MAX_MASK  = 0x7FF;
-
-constexpr uint32_t DB_DEPTH_SLICE                      = 0x17;
-constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_SHIFT = 0;
-constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_MASK  = 0x3FFFFF;
-
 constexpr uint32_t DB_Z_READ_BASE_HI                  = 0x1A;
 constexpr uint32_t DB_STENCIL_READ_BASE_HI            = 0x1B;
 constexpr uint32_t DB_Z_WRITE_BASE_HI                 = 0x1C;
@@ -424,11 +402,6 @@ constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT                        = 8
 constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK                         = 0x7;
 constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT                     = 20;
 constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK                      = 0x7;
-constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_SHIFT  = 30;
-constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK   = 0x1;
-constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_SHIFT = 31;
-constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK  = 0x1;
-
 constexpr uint32_t DB_EQAA                                  = 0x201;
 constexpr uint32_t DB_EQAA_MAX_ANCHOR_SAMPLES_SHIFT         = 0;
 constexpr uint32_t DB_EQAA_MAX_ANCHOR_SAMPLES_MASK          = 0x7;
@@ -560,21 +533,9 @@ constexpr uint32_t VGT_DRAW_PAYLOAD_CNTL  = 0x2A6;
 constexpr uint32_t VGT_ESGS_RING_ITEMSIZE = 0x2AB;
 constexpr uint32_t VGT_REUSE_OFF          = 0x2AD;
 
-constexpr uint32_t DB_HTILE_SURFACE                               = 0x2AF;
-constexpr uint32_t DB_HTILE_SURFACE_LINEAR_SHIFT                  = 0;
-constexpr uint32_t DB_HTILE_SURFACE_LINEAR_MASK                   = 0x1;
-constexpr uint32_t DB_HTILE_SURFACE_FULL_CACHE_SHIFT              = 1;
-constexpr uint32_t DB_HTILE_SURFACE_FULL_CACHE_MASK               = 0x1;
-constexpr uint32_t DB_HTILE_SURFACE_HTILE_USES_PRELOAD_WIN_SHIFT  = 2;
-constexpr uint32_t DB_HTILE_SURFACE_HTILE_USES_PRELOAD_WIN_MASK   = 0x1;
-constexpr uint32_t DB_HTILE_SURFACE_PRELOAD_SHIFT                 = 3;
-constexpr uint32_t DB_HTILE_SURFACE_PRELOAD_MASK                  = 0x1;
-constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_WIDTH_SHIFT          = 4;
-constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_WIDTH_MASK           = 0x3F;
-constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_HEIGHT_SHIFT         = 10;
-constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_HEIGHT_MASK          = 0x3F;
-constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_SHIFT = 16;
-constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_MASK  = 0x1;
+constexpr uint32_t DB_SHADING_RATE_ENCODING                             = 0x2AF;
+constexpr uint32_t DB_SHADING_RATE_ENCODING_SHADING_RATE_ENCODING_SHIFT = 19;
+constexpr uint32_t DB_SHADING_RATE_ENCODING_SHADING_RATE_ENCODING_MASK  = 0x3;
 
 constexpr uint32_t DB_SRESULTS_COMPARE_STATE0                          = 0x2B0;
 constexpr uint32_t DB_SRESULTS_COMPARE_STATE1                          = 0x2B1;
@@ -621,7 +582,6 @@ constexpr uint32_t PA_SC_SHADER_CONTROL                  = 0x310;
 constexpr uint32_t PA_SC_BINNER_CNTL_0                   = 0x311;
 constexpr uint32_t PA_SC_BINNER_CNTL_1                   = 0x312;
 constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
-constexpr uint32_t PA_SC_NGG_MODE_CNTL                   = 0x314;
 constexpr uint32_t CB_COLOR0_BASE                        = 0x318;
 
 constexpr uint32_t CB_COLOR0_VIEW                   = 0x31B;
@@ -649,24 +609,13 @@ constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_SHIFT              = 16;
 constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_MASK               = 0x1;
 constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_SHIFT                = 18;
 constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_MASK                 = 0x1;
-constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_SHIFT           = 19;
-constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_MASK            = 0x1;
 constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_SHIFT = 26;
 constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_MASK  = 0x1;
 constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_SHIFT = 27;
 constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_MASK  = 0x1;
 constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_SHIFT                = 28;
 constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_MASK                 = 0x1;
-constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_SHIFT           = 29;
-constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_MASK            = 0x3;
-constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_SHIFT             = 31;
-constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_MASK              = 0x1;
-
 constexpr uint32_t CB_COLOR0_ATTRIB                             = 0x31D;
-constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_SHIFT       = 0;
-constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_MASK        = 0x1F;
-constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_SHIFT = 5;
-constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_MASK  = 0x1F;
 constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_SHIFT           = 12;
 constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_MASK            = 0x7;
 constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_SHIFT         = 15;
@@ -681,8 +630,6 @@ constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_SHIFT
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_MASK                  = 0x1;
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_SHIFT      = 2;
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_MASK       = 0x3;
-constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_SHIFT        = 4;
-constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_MASK         = 0x1;
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_SHIFT        = 5;
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_MASK         = 0x3;
 constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_SHIFT                  = 7;
@@ -739,31 +686,25 @@ constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_SHIFT = 26;
 constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_MASK  = 0x1;
 constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_SHIFT   = 30;
 constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_MASK    = 0x1;
+constexpr uint32_t CB_COLOR0_ATTRIB3_WRITE_VRS_RATE_HINT_TO_CMASK_SHIFT = 31;
+constexpr uint32_t CB_COLOR0_ATTRIB3_WRITE_VRS_RATE_HINT_TO_CMASK_MASK  = 0x1;
 
 constexpr uint32_t CB_COLOR7_ATTRIB3 = 0x3BF;
 
-/* Fake codes. Don't exist on real HW */
-
-constexpr uint32_t CX_NOP = 0x800003FF;
+constexpr uint32_t CX_NOP = 0xDB;
 
 constexpr uint32_t CX_NUM = 0x3FF + 1;
 
 /* Shader registers */
 
-constexpr uint32_t SPI_SHADER_TBA_LO_PS     = 0x0;
-constexpr uint32_t SPI_SHADER_PGM_RSRC4_PS  = 0x1;
-constexpr uint32_t SPI_SHADER_TMA_LO_PS     = 0x2;
-constexpr uint32_t SPI_SHADER_TMA_HI_PS     = 0x3;
-constexpr uint32_t SPI_SHADER_PGM_CHKSUM_PS = 0x6;
-constexpr uint32_t SPI_SHADER_PGM_RSRC3_PS  = 0x7;
-constexpr uint32_t SPI_SHADER_PGM_LO_PS     = 0x8;
-constexpr uint32_t SPI_SHADER_PGM_HI_PS     = 0x9;
+constexpr uint32_t SPI_SHADER_PACE_ID_PS            = 0x6;
+constexpr uint32_t SPI_GRAPHICS_SHADER_CONTROL_PS    = 0x7;
+constexpr uint32_t SPI_SHADER_PGM_LO_PS              = 0x8;
+constexpr uint32_t SPI_SHADER_PGM_HI_PS              = 0x9;
 
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS                        = 0xA;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT            = 0;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK             = 0x3F;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT            = 6;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK             = 0xF;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_SHIFT         = 10;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_MASK          = 0x3;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_SHIFT       = 12;
@@ -800,14 +741,11 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK         = 0xF;
 constexpr uint32_t SPI_SHADER_USER_DATA_PS_0  = 0xC;
 constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
 constexpr uint32_t SPI_SHADER_USER_DATA_PS_31 = 0x2B;
-constexpr uint32_t SPI_SHADER_REQ_CTRL_PS     = 0x30;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_3 = 0x35;
 
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_SHIFT           = 0;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_MASK            = 0x3F;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_SHIFT           = 6;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_MASK            = 0xF;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_SHIFT        = 10;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_MASK         = 0x3;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_SHIFT      = 12;
@@ -838,19 +776,20 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_MASK    = 0x1;
 constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_SHIFT = 28;
 constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_MASK  = 0xF;
 
-constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS        = 0x80;
+constexpr uint32_t SPI_SHADER_PACE_ID_GS           = 0x80;
+// AGC compiler records use this numeric tag as opaque metadata. It is not a shader checksum
+// register and intentionally has no checksum-state consumer in HardwareContext.
+constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS        = SPI_SHADER_PACE_ID_GS;
 constexpr uint32_t SPI_SHADER_PGM_RSRC4_GS         = 0x81;
 constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_GS = 0x82;
 constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
-constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS         = 0x87;
+constexpr uint32_t SPI_GRAPHICS_SHADER_CONTROL_GS  = 0x87;
 constexpr uint32_t SPI_SHADER_PGM_LO_GS            = 0x88;
 constexpr uint32_t SPI_SHADER_PGM_HI_GS            = 0x89;
 
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS                        = 0x8A;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_SHIFT            = 0;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_MASK             = 0x3F;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_SHIFT            = 6;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_MASK             = 0xF;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_SHIFT         = 10;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_MASK          = 0x3;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_SHIFT       = 12;
@@ -891,22 +830,15 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_MASK   = 0xF;
 constexpr uint32_t SPI_SHADER_USER_DATA_GS_0                      = 0x8C;
 constexpr uint32_t SPI_SHADER_USER_DATA_GS_15                     = 0x9B;
 constexpr uint32_t SPI_SHADER_USER_DATA_GS_31                     = 0xAB;
-constexpr uint32_t SPI_SHADER_REQ_CTRL_ESGS                       = 0xB0;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0                   = 0xB2;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_3                   = 0xB5;
-constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES_GS                     = 0xBC;
 constexpr uint32_t SPI_SHADER_PGM_LO_ES                           = 0xC8;
 constexpr uint32_t SPI_SHADER_PGM_HI_ES                           = 0xC9;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_ES                        = 0xCA;
-constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES                        = 0xCB;
-constexpr uint32_t SPI_SHADER_USER_DATA_ES_0                      = 0xCC;
-constexpr uint32_t SPI_SHADER_USER_DATA_ES_15                     = 0xDB;
-constexpr uint32_t SPI_SHADER_USER_DATA_ES_31                     = 0xEB;
+// Retained only as an opaque AGC compiler-record tag; 0x100 is not a PS5 SH register.
 constexpr uint32_t SPI_SHADER_PGM_CHKSUM_HS                       = 0x100;
-constexpr uint32_t SPI_SHADER_PGM_RSRC4_HS                        = 0x101;
 constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_HS                = 0x102;
 constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_HS                = 0x103;
-constexpr uint32_t SPI_SHADER_PGM_RSRC3_HS                        = 0x107;
+constexpr uint32_t SPI_GRAPHICS_SHADER_CONTROL_HS                 = 0x107;
 constexpr uint32_t SPI_SHADER_PGM_LO_HS                           = 0x108;
 constexpr uint32_t SPI_SHADER_PGM_HI_HS                           = 0x109;
 constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS                        = 0x10A;
@@ -944,13 +876,10 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_SHARED_VGPR_CNT_MASK   = 0xF;
 constexpr uint32_t SPI_SHADER_USER_DATA_HS_0                      = 0x10C;
 constexpr uint32_t SPI_SHADER_USER_DATA_HS_15                     = 0x11B;
 constexpr uint32_t SPI_SHADER_USER_DATA_HS_31                     = 0x12B;
-constexpr uint32_t SPI_SHADER_REQ_CTRL_LSHS                       = 0x130;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_0                   = 0x132;
 constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_3                   = 0x135;
 constexpr uint32_t SPI_SHADER_PGM_LO_LS                           = 0x148;
 constexpr uint32_t SPI_SHADER_PGM_HI_LS                           = 0x149;
-constexpr uint32_t SPI_SHADER_PGM_RSRC1_LS                        = 0x14A;
-constexpr uint32_t SPI_SHADER_PGM_RSRC2_LS                        = 0x14B;
 constexpr uint32_t COMPUTE_START_X                                = 0x204;
 constexpr uint32_t COMPUTE_START_Y                                = 0x205;
 constexpr uint32_t COMPUTE_START_Z                                = 0x206;
@@ -959,28 +888,26 @@ constexpr uint32_t COMPUTE_NUM_THREAD_Y                           = 0x208;
 constexpr uint32_t COMPUTE_NUM_THREAD_Z                           = 0x209;
 constexpr uint32_t COMPUTE_PGM_LO                                 = 0x20C;
 constexpr uint32_t COMPUTE_PGM_HI                                 = 0x20D;
-constexpr uint32_t COMPUTE_TBA_LO                                 = 0x20E;
-constexpr uint32_t COMPUTE_TBA_HI                                 = 0x20F;
-constexpr uint32_t COMPUTE_TMA_LO                                 = 0x210;
-constexpr uint32_t COMPUTE_TMA_HI                                 = 0x211;
 
 constexpr uint32_t COMPUTE_PGM_RSRC1                  = 0x212;
 constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT      = 0;
 constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_MASK       = 0x3F;
-constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_SHIFT      = 6;
-constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_MASK       = 0xF;
+constexpr uint32_t COMPUTE_PGM_RSRC1_PRIORITY_SHIFT   = 10;
+constexpr uint32_t COMPUTE_PGM_RSRC1_PRIORITY_MASK    = 0x3;
 constexpr uint32_t COMPUTE_PGM_RSRC1_FLOAT_MODE_SHIFT = 12;
 constexpr uint32_t COMPUTE_PGM_RSRC1_FLOAT_MODE_MASK  = 0xFF;
 constexpr uint32_t COMPUTE_PGM_RSRC1_DX10_CLAMP_SHIFT = 21;
 constexpr uint32_t COMPUTE_PGM_RSRC1_DX10_CLAMP_MASK  = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_DEBUG_MODE_SHIFT = 22;
+constexpr uint32_t COMPUTE_PGM_RSRC1_DEBUG_MODE_MASK  = 0x1;
 constexpr uint32_t COMPUTE_PGM_RSRC1_IEEE_MODE_SHIFT  = 23;
 constexpr uint32_t COMPUTE_PGM_RSRC1_IEEE_MODE_MASK   = 0x1;
-constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_SHIFT      = 24;
-constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_MASK       = 0x1;
 constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT  = 26;
 constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_MASK   = 0x1;
 constexpr uint32_t COMPUTE_PGM_RSRC1_WGP_MODE_SHIFT   = 29;
 constexpr uint32_t COMPUTE_PGM_RSRC1_WGP_MODE_MASK    = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FWD_PROGRESS_SHIFT = 31;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FWD_PROGRESS_MASK  = 0x1;
 
 constexpr uint32_t COMPUTE_DISPATCH_INITIATOR_CS_W32_EN_SHIFT = 15;
 constexpr uint32_t COMPUTE_DISPATCH_INITIATOR_CS_W32_EN_MASK  = 0x1;
@@ -1011,21 +938,16 @@ constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_SHIFT       = 15;
 constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_MASK        = 0x1FF;
 
 constexpr uint32_t COMPUTE_RESOURCE_LIMITS    = 0x215;
-constexpr uint32_t COMPUTE_DESTINATION_EN_SE0 = 0x216;
-constexpr uint32_t COMPUTE_DESTINATION_EN_SE1 = 0x217;
 constexpr uint32_t COMPUTE_TMPRING_SIZE       = 0x218;
-constexpr uint32_t COMPUTE_DESTINATION_EN_SE2 = 0x219;
-constexpr uint32_t COMPUTE_DESTINATION_EN_SE3 = 0x21A;
 constexpr uint32_t COMPUTE_USER_ACCUM_0       = 0x224;
 constexpr uint32_t COMPUTE_PGM_RSRC3          = 0x228;
-constexpr uint32_t COMPUTE_SHADER_CHKSUM      = 0x22A;
+constexpr uint32_t COMPUTE_PGM_RSRC3_SHARED_VGPRS_SHIFT = 0;
+constexpr uint32_t COMPUTE_PGM_RSRC3_SHARED_VGPRS_MASK  = 0xF;
+constexpr uint32_t COMPUTE_PACE_ID             = 0x22A;
 constexpr uint32_t COMPUTE_USER_DATA_0        = 0x240;
 constexpr uint32_t COMPUTE_USER_DATA_15       = 0x24F;
-constexpr uint32_t COMPUTE_DISPATCH_TUNNEL    = 0x27D;
 
-/* Fake codes. Don't exist on real HW */
-
-constexpr uint32_t SH_NOP = 0x800002FF;
+constexpr uint32_t SH_NOP = 0x280;
 
 constexpr uint32_t SH_NUM = 0x2FF + 1;
 
@@ -1042,6 +964,7 @@ constexpr uint32_t GE_INDX_OFFSET            = 0x24A;
 constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
 constexpr uint32_t VGT_HS_OFFCHIP_PARAM      = 0x24F;
 constexpr uint32_t VGT_TF_MEMORY_BASE        = 0x250;
+constexpr uint32_t IA_MULTI_VGT_PARAM        = 0x258;
 
 constexpr uint32_t GE_CNTL                     = 0x25B;
 constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_SHIFT = 0;
@@ -1063,28 +986,15 @@ constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_MASK  = 0x1;
 constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_SHIFT = 2;
 constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_MASK  = 0x1;
 
-constexpr uint32_t IA_MULTI_VGT_PARAM       = 0x258;
 constexpr uint32_t TA_CS_BC_BASE_ADDR       = 0x380;
 constexpr uint32_t TA_CS_BC_BASE_ADDR_HI    = 0x381;
-constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
+constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x383;
+constexpr uint32_t TEXTURE_GRADIENT_CONTROL = 0x384;
 constexpr uint32_t GDS_OA_CNTL              = 0x41D;
 constexpr uint32_t GDS_OA_COUNTER           = 0x41E;
 constexpr uint32_t GDS_OA_ADDRESS           = 0x41F;
 
-/* Fake codes. Don't exist on real HW */
-
-constexpr uint32_t FSR_EXTEND_SUBPIXEL_ROUNDING = 0x80003FF4;
-constexpr uint32_t FSR_ALPHA_VALUE0             = 0x80003FF5;
-constexpr uint32_t FSR_ALPHA_VALUE1             = 0x80003FF6;
-constexpr uint32_t FSR_CONTROL_POINT0           = 0x80003FF7;
-constexpr uint32_t FSR_CONTROL_POINT1           = 0x80003FF8;
-constexpr uint32_t FSR_CONTROL_POINT2           = 0x80003FF9;
-constexpr uint32_t FSR_CONTROL_POINT3           = 0x80003FFA;
-constexpr uint32_t FSR_WINDOW0                  = 0x80003FFB;
-constexpr uint32_t FSR_WINDOW1                  = 0x80003FFC;
-constexpr uint32_t TEXTURE_GRADIENT_CONTROL     = 0x80003FFD;
-constexpr uint32_t MEMORY_MAPPING_MASK          = 0x80003FFE;
-constexpr uint32_t UC_NOP                       = 0x80003FFF;
+constexpr uint32_t UC_NOP = 0xA2;
 
 constexpr uint32_t UC_NUM = 0x3FFF + 1;
 
diff --git a/src/graphics/host_gpu/renderer/colorRenderTarget.cpp b/src/graphics/host_gpu/renderer/colorRenderTarget.cpp
index 8aa19abea..65b5ef738 100644
--- a/src/graphics/host_gpu/renderer/colorRenderTarget.cpp
+++ b/src/graphics/host_gpu/renderer/colorRenderTarget.cpp
@@ -204,13 +204,11 @@ void RenderExecutor::ResolveRenderColorTarget(uint64_t submit_id, CommandBuffer&
 	if (texture_tile &&
 	    (!TileGetTextureBlockLayout(transfer_format, rt.attrib3.tile_mode, volume,
 	                                texture_tile_layout) ||
-	     rt.pitch.pitch_div8_minus1 != 0 ||
 	     (rt.base.addr & (texture_tile_layout.block.block_size - 1u)) != 0 ||
 	     rt.info.fmask_compression_enable || rt.info.fmask_data_compression_disable ||
 	     rt.info.fmask_one_frag_mode || rt.info.cmask_fast_clear_enable ||
-	     rt.info.dcc_compression_enable || rt.info.cmask_is_linear != 0 ||
-	     rt.info.cmask_addr_type != 0 || rt.info.alt_tile_mode || rt.cmask.addr != 0 ||
-	     rt.fmask.addr != 0 || rt.dcc_addr.addr != 0 || rt.dcc.data_write_on_dcc_clear_to_reg)) {
+	     rt.info.dcc_compression_enable || rt.cmask.addr != 0 || rt.fmask.addr != 0 ||
+	     rt.dcc_addr.addr != 0 || rt.dcc.data_write_on_dcc_clear_to_reg)) {
 		EXIT("unsupported texture-tiled render target: addr=0x%016" PRIx64 " tile=%u"
 		     " dimension=%u depth=%u levels=%u layer=%u/%u samples=%u fragments=%u bpe=%u"
 		     " cmask=0x%016" PRIx64 " fmask=0x%016" PRIx64 " dcc=0x%016" PRIx64 "\n",
@@ -226,9 +224,7 @@ void RenderExecutor::ResolveRenderColorTarget(uint64_t submit_id, CommandBuffer&
 		     " layer=%u/%u\n",
 		     rt.attrib3.dimension, rt.attrib3.depth, view.base_layer, view.image_layers);
 	}
-	if (rt.pitch.pitch_div8_minus1 != 0) {
-		pitch = (rt.pitch.pitch_div8_minus1 + 1u) << 3u;
-	} else if (tile) {
+	if (tile) {
 		if (volume) {
 			pitch = TileGetTexturePitch(transfer_format, width, rt.attrib3.tile_mode);
 		} else if (texture_tile) {
@@ -294,12 +290,6 @@ void RenderExecutor::ResolveRenderColorTarget(uint64_t submit_id, CommandBuffer&
 		mip_sizes[0]  = {static_cast<uint32_t>(size), 0, 0, 0, 0, 0};
 		mip_padded[0] = {pitch, height};
 	}
-	if (rt.slice.slice_div64_minus1 != 0 &&
-	    (static_cast<uint64_t>(rt.slice.slice_div64_minus1) + 1u) * 64u != size) {
-		EXIT("render-target slice span mismatch: encoded=0x%016" PRIx64 " derived=0x%016" PRIx64
-		     "\n",
-		     (static_cast<uint64_t>(rt.slice.slice_div64_minus1) + 1u) * 64u, size);
-	}
 	if (size == 0 || (!volume && size > UINT64_MAX / view.image_layers)) {
 		EXIT("render-target memory footprint is invalid\n");
 	}
diff --git a/src/graphics/host_gpu/renderer/debug.cpp b/src/graphics/host_gpu/renderer/debug.cpp
index aa325a178..3c907d232 100644
--- a/src/graphics/host_gpu/renderer/debug.cpp
+++ b/src/graphics/host_gpu/renderer/debug.cpp
@@ -97,17 +97,11 @@ void sh_print(const char* func, const HW::Shader& /*uc*/) {
 
 std::vector<std::string> rt_print(const char* func, const HW::RenderTarget& rt) {
 	std::vector<std::string> dst;
-	dst.reserve(53);
+	dst.reserve(40);
 
 	dst.push_back(fmt::format("{}\n", func));
 
 	dst.push_back(fmt::format("\t base.addr                       = 0x{:016x}\n", rt.base.addr));
-	dst.push_back(
-	    fmt::format("\t pitch.pitch_div8_minus1         = 0x{:08x}\n", rt.pitch.pitch_div8_minus1));
-	dst.push_back(fmt::format("\t pitch.fmask_pitch_div8_minus1   = 0x{:08x}\n",
-	                          rt.pitch.fmask_pitch_div8_minus1));
-	dst.push_back(fmt::format("\t slice.slice_div64_minus1        = 0x{:08x}\n",
-	                          rt.slice.slice_div64_minus1));
 	dst.push_back(fmt::format("\t view.base_array_slice_index     = 0x{:08x}\n",
 	                          rt.view.base_array_slice_index));
 	dst.push_back(fmt::format("\t view.last_array_slice_index     = 0x{:08x}\n",
@@ -128,12 +122,6 @@ std::vector<std::string> rt_print(const char* func, const HW::RenderTarget& rt)
 	                          rt.info.cmask_fast_clear_enable ? "true" : "false"));
 	dst.push_back(fmt::format("\t info.dcc_compression_enable     = {}\n",
 	                          rt.info.dcc_compression_enable ? "true" : "false"));
-	dst.push_back(
-	    fmt::format("\t info.cmask_is_linear            = 0x{:08x}\n", rt.info.cmask_is_linear));
-	dst.push_back(
-	    fmt::format("\t info.cmask_addr_type            = 0x{:08x}\n", rt.info.cmask_addr_type));
-	dst.push_back(fmt::format("\t info.alt_tile_mode              = {}\n",
-	                          rt.info.alt_tile_mode ? "true" : "false"));
 	dst.push_back(fmt::format("\t info.format                     = 0x{:08x}\n",
 	                          static_cast<uint32_t>(rt.info.format)));
 	dst.push_back(fmt::format("\t info.channel_type               = 0x{:08x}\n",
@@ -148,10 +136,6 @@ std::vector<std::string> rt_print(const char* func, const HW::RenderTarget& rt)
 	                          rt.info.round_mode ? "true" : "false"));
 	dst.push_back(fmt::format("\t attrib.force_dest_alpha_to_one  = {}\n",
 	                          rt.attrib.force_dest_alpha_to_one ? "true" : "false"));
-	dst.push_back(fmt::format("\t attrib.tile_mode                = 0x{:08x}\n",
-	                          static_cast<uint32_t>(rt.attrib.tile_mode)));
-	dst.push_back(fmt::format("\t attrib.fmask_tile_mode          = 0x{:08x}\n",
-	                          static_cast<uint32_t>(rt.attrib.fmask_tile_mode)));
 	dst.push_back(
 	    fmt::format("\t attrib.num_samples              = 0x{:08x}\n", rt.attrib.num_samples));
 	dst.push_back(
@@ -166,42 +150,32 @@ std::vector<std::string> rt_print(const char* func, const HW::RenderTarget& rt)
 	                          static_cast<uint32_t>(rt.attrib3.tile_mode)));
 	dst.push_back(
 	    fmt::format("\t attrib3.dimension               = 0x{:08x}\n", rt.attrib3.dimension));
-	dst.push_back(fmt::format("\t attrib3.cmask_pipe_aligned      = {}\n",
-	                          rt.attrib3.cmask_pipe_aligned ? "true" : "false"));
-	dst.push_back(fmt::format("\t attrib3.dcc_pipe_aligned        = {}\n",
-	                          rt.attrib3.dcc_pipe_aligned ? "true" : "false"));
+	dst.push_back(fmt::format("\t attrib3.metadata_pipe_aligned   = {}\n",
+	                          rt.attrib3.metadata_pipe_aligned ? "true" : "false"));
+	dst.push_back(fmt::format("\t attrib3.write_vrs_rate_hint_to_cmask = {}\n",
+	                          rt.attrib3.write_vrs_rate_hint_to_cmask ? "true" : "false"));
 	dst.push_back(fmt::format("\t dcc.max_uncompressed_block_size = 0x{:08x}\n",
 	                          rt.dcc.max_uncompressed_block_size));
 	dst.push_back(fmt::format("\t dcc.max_compressed_block_size   = 0x{:08x}\n",
 	                          rt.dcc.max_compressed_block_size));
-	dst.push_back(fmt::format("\t dcc.min_compressed_block_size   = 0x{:08x}\n",
-	                          rt.dcc.min_compressed_block_size));
 	dst.push_back(
 	    fmt::format("\t dcc.color_transform             = 0x{:08x}\n", rt.dcc.color_transform));
 	dst.push_back(fmt::format("\t dcc.overwrite_combiner_disable  = {}\n",
 	                          rt.dcc.overwrite_combiner_disable ? "true" : "false"));
-	dst.push_back(fmt::format("\t dcc.independent_64b_blocks      = {}\n",
-	                          rt.dcc.independent_64b_blocks ? "true" : "false"));
-	dst.push_back(fmt::format("\t dcc.independent_128b_blocks     = {}\n",
-	                          rt.dcc.independent_128b_blocks ? "true" : "false"));
+	dst.push_back(fmt::format("\t dcc.independent_block_size      = 0x{:02x}\n",
+	                          static_cast<uint8_t>(rt.dcc.independent_block_size)));
 	dst.push_back(fmt::format("\t data_write_on_dcc_clear_to_reg  = {}\n",
 	                          rt.dcc.data_write_on_dcc_clear_to_reg ? "true" : "false"));
 	dst.push_back(fmt::format("\t dcc.dcc_clear_key_enable        = {}\n",
 	                          rt.dcc.dcc_clear_key_enable ? "true" : "false"));
 	dst.push_back(fmt::format("\t cmask.addr                      = 0x{:016x}\n", rt.cmask.addr));
-	dst.push_back(fmt::format("\t cmask_slice.slice_minus1        = 0x{:08x}\n",
-	                          rt.cmask_slice.slice_minus1));
 	dst.push_back(fmt::format("\t fmask.addr                      = 0x{:016x}\n", rt.fmask.addr));
-	dst.push_back(fmt::format("\t fmask_slice.slice_minus1        = 0x{:08x}\n",
-	                          rt.fmask_slice.slice_minus1));
 	dst.push_back(
 	    fmt::format("\t clear_word0.word0               = 0x{:08x}\n", rt.clear_word0.word0));
 	dst.push_back(
 	    fmt::format("\t clear_word1.word1               = 0x{:08x}\n", rt.clear_word1.word1));
 	dst.push_back(
 	    fmt::format("\t dcc_addr.addr                   = 0x{:016x}\n", rt.dcc_addr.addr));
-	dst.push_back(fmt::format("\t size.width                      = 0x{:08x}\n", rt.size.width));
-	dst.push_back(fmt::format("\t size.height                     = 0x{:08x}\n", rt.size.height));
 
 	return dst;
 }
@@ -231,13 +205,8 @@ static bool RenderIsColorDimension(uint32_t dimension) {
 // NOLINTNEXTLINE(readability-function-cognitive-complexity)
 static void RtCheck(const HW::RenderTarget& rt) {
 	if (rt.base.addr != 0) {
-		// bool render_to_texture = (rt.attrib.tile_mode == 0x0d);
 		//  EXIT_NOT_IMPLEMENTED(rt.base_addr == 0);
 
-		EXIT_NOT_IMPLEMENTED(rt.pitch.pitch_div8_minus1 != 0);
-		EXIT_NOT_IMPLEMENTED(rt.pitch.fmask_pitch_div8_minus1 != 0);
-		EXIT_NOT_IMPLEMENTED(rt.slice.slice_div64_minus1 != 0);
-
 		EXIT_NOT_IMPLEMENTED(rt.view.base_array_slice_index > rt.view.last_array_slice_index);
 		if (rt.view.base_array_slice_index != 0x00000000 ||
 		    rt.view.last_array_slice_index != 0x00000000) {
@@ -281,22 +250,6 @@ static void RtCheck(const HW::RenderTarget& rt) {
 				logged = true;
 			}
 		}
-		if (rt.info.cmask_is_linear != 0x00000000 || rt.info.cmask_addr_type != 0x00000000) {
-			static bool logged = false;
-			if (!logged) {
-				LOGF("RenderTarget: temporary: ignoring PS5 CMASK metadata fields "
-				     "is_linear=%u addr_type=%u\n",
-				     rt.info.cmask_is_linear, rt.info.cmask_addr_type);
-				logged = true;
-			}
-		}
-		if (rt.info.alt_tile_mode) {
-			static bool logged = false;
-			if (!logged) {
-				LOGF("RenderTarget: temporary: ignoring alternate tile mode flag\n");
-				logged = true;
-			}
-		}
 		if (rt.info.blend_bypass) {
 			static bool logged = false;
 			if (!logged) {
@@ -323,8 +276,6 @@ static void RtCheck(const HW::RenderTarget& rt) {
 				logged = true;
 			}
 		}
-		// EXIT_NOT_IMPLEMENTED(rt.tile_mode != 0x0000000a);
-		// EXIT_NOT_IMPLEMENTED(rt.fmask_tile_mode != 0x0000000a);
 		if (rt.attrib.num_samples != 0x00000000 || rt.attrib.num_fragments != 0x00000000) {
 			static bool logged = false;
 			if (!logged) {
@@ -359,34 +310,22 @@ static void RtCheck(const HW::RenderTarget& rt) {
 		if (!RenderIsColorDimension(rt.attrib3.dimension)) {
 			EXIT("unknown PS5 render-target dimension: 0x%08" PRIx32 "\n", rt.attrib3.dimension);
 		}
-		if (!rt.attrib3.cmask_pipe_aligned) {
+		if (!rt.attrib3.metadata_pipe_aligned) {
 			static bool logged = false;
 			if (!logged) {
-				LOGF("RenderTarget: temporary: accepting unaligned PS5 CMASK pipe flag\n");
-				logged = true;
-			}
-		}
-		if (!rt.attrib3.dcc_pipe_aligned) {
-			static bool logged = false;
-			if (!logged) {
-				LOGF("RenderTarget: temporary: accepting unaligned PS5 DCC pipe flag\n");
+				LOGF("RenderTarget: temporary: accepting unaligned PS5 metadata pipe flag\n");
 				logged = true;
 			}
 		}
+		EXIT_NOT_IMPLEMENTED(rt.attrib3.write_vrs_rate_hint_to_cmask);
 
 		// EXIT_NOT_IMPLEMENTED(rt.dcc_max_uncompressed_block_size != 0x00000002);
 		// EXIT_NOT_IMPLEMENTED(rt.dcc.max_compressed_block_size != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(rt.dcc.min_compressed_block_size != 0x00000000);
 		// EXIT_NOT_IMPLEMENTED(rt.dcc.color_transform != 0x00000000);
 		EXIT_NOT_IMPLEMENTED(rt.dcc.overwrite_combiner_disable != false);
-		// EXIT_NOT_IMPLEMENTED(rt.dcc.force_independent_blocks != false);
-		// EXIT_NOT_IMPLEMENTED(rt.dcc.independent_128b_blocks != false);
 		// EXIT_NOT_IMPLEMENTED(rt.dcc.data_write_on_dcc_clear_to_reg != false);
 		EXIT_NOT_IMPLEMENTED(rt.dcc.dcc_clear_key_enable != false);
-		if (rt.cmask.addr != 0x0000000000000000 || rt.cmask_slice.slice_minus1 != 0x00000000 ||
-		    rt.fmask.addr != 0x0000000000000000 ||
-		    (rt.fmask_slice.slice_minus1 != 0x00000000 &&
-		     rt.fmask_slice.slice_minus1 != rt.slice.slice_div64_minus1) ||
+		if (rt.cmask.addr != 0x0000000000000000 || rt.fmask.addr != 0x0000000000000000 ||
 		    rt.dcc_addr.addr != 0x0000000000000000) {
 			static bool logged = false;
 			if (!logged) {
@@ -396,9 +335,6 @@ static void RtCheck(const HW::RenderTarget& rt) {
 				logged = true;
 			}
 		}
-
-		EXIT_NOT_IMPLEMENTED(rt.size.width != 0);
-		EXIT_NOT_IMPLEMENTED(rt.size.height != 0);
 	}
 }
 
@@ -418,37 +354,20 @@ static void ZPrint(const char* func, const HW::DepthRenderTarget& z) {
 	     "\t stencil_info.htile_stencil_disabled   = %s\n"
 	     "\t stencil_info.expclear_enabled         = %s\n"
 	     "\t stencil_info.partially_resident       = %s\n"
-	     "\t depth_info.addr5_swizzle_mask         = 0x%08" PRIx32 "\n"
-	     "\t depth_info.array_mode                 = 0x%08" PRIx32 "\n"
-	     "\t depth_info.pipe_config                = 0x%08" PRIx32 "\n"
-	     "\t depth_info.bank_width                 = 0x%08" PRIx32 "\n"
-	     "\t depth_info.bank_height                = 0x%08" PRIx32 "\n"
-	     "\t depth_info.macro_tile_aspect          = 0x%08" PRIx32 "\n"
-	     "\t depth_info.num_banks                  = 0x%08" PRIx32 "\n"
 	     "\t depth_view.slice_start                = 0x%08" PRIx32 "\n"
 	     "\t depth_view.slice_max                  = 0x%08" PRIx32 "\n"
 	     "\t depth_view.current_mip_level          = 0x%02" PRIx8 "\n"
 	     "\t depth_view.depth_write_disable        = %s\n"
 	     "\t depth_view.stencil_write_disable      = %s\n"
-	     "\t htile_surface.linear                  = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.full_cache              = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.htile_uses_preload_win  = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.preload                 = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.prefetch_width          = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.prefetch_height         = 0x%08" PRIx32 "\n"
-	     "\t htile_surface.dst_outside_zero_to_one = 0x%08" PRIx32 "\n"
 	     "\t z_read_base_addr                      = 0x%016" PRIx64 "\n"
 	     "\t stencil_read_base_addr                = 0x%016" PRIx64 "\n"
 	     "\t z_write_base_addr                     = 0x%016" PRIx64 "\n"
 	     "\t stencil_write_base_addr               = 0x%016" PRIx64 "\n"
-	     "\t pitch_div8_minus1                     = 0x%08" PRIx32 "\n"
-	     "\t height_div8_minus1                    = 0x%08" PRIx32 "\n"
-	     "\t slice_div64_minus1                    = 0x%08" PRIx32 "\n"
 	     "\t htile_data_base_addr                  = 0x%016" PRIx64 "\n"
-	     "\t width                                 = 0x%08" PRIx32 "\n"
-	     "\t height                                = 0x%08" PRIx32 "\n"
+	     "\t shading_rate_encoding                 = 0x%02" PRIx8 "\n"
 	     "\t size.x_max                            = 0x%04" PRIx16 "\n"
-	     "\t size.y_max                            = 0x%04" PRIx16 "\n",
+	     "\t size.y_max                            = 0x%04" PRIx16 "\n"
+	     "\t size.valid                            = %s\n",
 	     static_cast<uint32_t>(z.z_info.format), z.z_info.num_samples,
 	     static_cast<uint32_t>(z.z_info.texture_compatibility),
 	     z.z_info.htile_acceleration ? "true" : "false",
@@ -459,30 +378,27 @@ static void ZPrint(const char* func, const HW::DepthRenderTarget& z) {
 	     static_cast<uint32_t>(z.stencil_info.texture_compatibility),
 	     z.stencil_info.htile_stencil_disabled ? "true" : "false",
 	     z.stencil_info.expclear_enabled ? "true" : "false",
-	     z.stencil_info.partially_resident ? "true" : "false", z.depth_info.addr5_swizzle_mask,
-	     z.depth_info.array_mode, z.depth_info.pipe_config, z.depth_info.bank_width,
-	     z.depth_info.bank_height, z.depth_info.macro_tile_aspect, z.depth_info.num_banks,
-	     z.depth_view.slice_start, z.depth_view.slice_max, z.depth_view.current_mip_level,
+	     z.stencil_info.partially_resident ? "true" : "false", z.depth_view.slice_start,
+	     z.depth_view.slice_max, z.depth_view.current_mip_level,
 	     z.depth_view.depth_write_disable ? "true" : "false",
-	     z.depth_view.stencil_write_disable ? "true" : "false", z.htile_surface.linear,
-	     z.htile_surface.full_cache, z.htile_surface.htile_uses_preload_win,
-	     z.htile_surface.preload, z.htile_surface.prefetch_width, z.htile_surface.prefetch_height,
-	     z.htile_surface.dst_outside_zero_to_one, z.z_read_base_addr, z.stencil_read_base_addr,
-	     z.z_write_base_addr, z.stencil_write_base_addr, z.pitch_div8_minus1, z.height_div8_minus1,
-	     z.slice_div64_minus1, z.htile_data_base_addr, z.width, z.height, z.size.x_max,
-	     z.size.y_max);
+	     z.depth_view.stencil_write_disable ? "true" : "false", z.z_read_base_addr,
+	     z.stencil_read_base_addr, z.z_write_base_addr, z.stencil_write_base_addr,
+	     z.htile_data_base_addr, z.shading_rate_encoding, z.size.x_max, z.size.y_max,
+	     z.size.valid ? "true" : "false");
 }
 
 // NOLINTNEXTLINE(readability-function-cognitive-complexity)
 static void ZCheck(const HW::DepthRenderTarget& z, const HW::DepthControl& dc,
                    const HW::RenderControl& rc) {
-	const bool depth_active =
-	    dc.z_enable || dc.z_write_enable || dc.depth_bounds_enable || rc.depth_clear_enable;
-	const bool stencil_active = dc.stencil_enable || rc.stencil_clear_enable;
+	const bool depth_active = dc.z_enable || dc.z_write_enable || dc.depth_bounds_enable ||
+	                          rc.depth_clear_enable || rc.copy_depth_to_color;
+	const bool stencil_active =
+	    dc.stencil_enable || rc.stencil_clear_enable || rc.copy_stencil_to_color;
 	if (!depth_active && !stencil_active) {
 		return;
 	}
 
+	EXIT_NOT_IMPLEMENTED(rc.copy_depth_to_color || rc.copy_stencil_to_color);
 	EXIT_NOT_IMPLEMENTED(!z.z_info.HasValidTextureCompatibility());
 	EXIT_NOT_IMPLEMENTED(!z.stencil_info.HasValidTextureCompatibility());
 	if (z.z_info.format == Prospero::DepthFormat::kInvalid) {
@@ -519,21 +435,7 @@ static void ZCheck(const HW::DepthRenderTarget& z, const HW::DepthControl& dc,
 
 	if (z.z_info.format != Prospero::DepthFormat::kInvalid ||
 	    z.stencil_info.format != Prospero::StencilFormat::kInvalid) {
-
-		EXIT_NOT_IMPLEMENTED(z.depth_info.addr5_swizzle_mask != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.array_mode != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.pipe_config != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.bank_width != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.bank_height != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.macro_tile_aspect != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.depth_info.num_banks != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.linear != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.full_cache != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.htile_uses_preload_win != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.preload != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.prefetch_width != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.prefetch_height != 0x00000000);
-		EXIT_NOT_IMPLEMENTED(z.htile_surface.dst_outside_zero_to_one != 0x00000000);
+		EXIT_NOT_IMPLEMENTED(z.shading_rate_encoding != 0);
 
 		if (z.depth_view.current_mip_level != 0x00000000) {
 			static std::atomic<uint32_t> log_count {0};
@@ -555,23 +457,8 @@ static void ZCheck(const HW::DepthRenderTarget& z, const HW::DepthControl& dc,
 		EXIT_NOT_IMPLEMENTED(!z.depth_view.stencil_write_disable &&
 		                     z.stencil_read_base_addr != z.stencil_write_base_addr);
 		EXIT_NOT_IMPLEMENTED(!z.depth_view.depth_write_disable && z.z_write_base_addr == 0);
-		// EXIT_NOT_IMPLEMENTED(z.pitch_div8_minus1 != 0x000000ff);
-		// EXIT_NOT_IMPLEMENTED(z.height_div8_minus1 != 0x0000008f);
-		// EXIT_NOT_IMPLEMENTED(z.slice_div64_minus1 != 0x00008fff);
 		// EXIT_NOT_IMPLEMENTED(z.htile_data_base_addr == 0);
-		// EXIT_NOT_IMPLEMENTED(z.width != 0x00000780);
-		// EXIT_NOT_IMPLEMENTED(z.height != 0x00000438);
-
-		EXIT_NOT_IMPLEMENTED(z.width != 0);
-		EXIT_NOT_IMPLEMENTED(z.height != 0);
-		if (z.size.x_max == 0 || z.size.y_max == 0) {
-			static std::atomic<uint32_t> log_count {0};
-			if (log_count.fetch_add(1) < 16) {
-				LOGF("DepthTarget: temporary: inferring PS5 default depth extent x_max=0x%04" PRIx16
-				     ", y_max=0x%04" PRIx16 "\n",
-				     z.size.x_max, z.size.y_max);
-			}
-		}
+		EXIT_NOT_IMPLEMENTED(!z.size.valid);
 	}
 }
 
@@ -754,8 +641,6 @@ static void DPrint(const char* func, const HW::DepthControl& c, const HW::Stenci
 	     "\t backface_enable      = %s\n"
 	     "\t stencilfunc          = %" PRIu8 "\n"
 	     "\t stencilfunc_bf       = %" PRIu8 "\n"
-	     "\t color_writes_on_depth_fail_enable  = %s\n"
-	     "\t color_writes_on_depth_pass_disable = %s\n"
 	     "\t stencil_fail         = %" PRIu8 "\n"
 	     "\t stencil_zpass        = %" PRIu8 "\n"
 	     "\t stencil_zfail        = %" PRIu8 "\n"
@@ -772,12 +657,11 @@ static void DPrint(const char* func, const HW::DepthControl& c, const HW::Stenci
 	     "\t stencil_opval_bf     = %" PRIu8 "\n",
 	     c.stencil_enable ? "true" : "false", c.z_enable ? "true" : "false",
 	     c.z_write_enable ? "true" : "false", c.depth_bounds_enable ? "true" : "false", c.zfunc,
-	     c.backface_enable ? "true" : "false", c.stencilfunc, c.stencilfunc_bf,
-	     c.color_writes_on_depth_fail_enable ? "true" : "false",
-	     c.color_writes_on_depth_pass_disable ? "true" : "false", s.stencil_fail, s.stencil_zpass,
-	     s.stencil_zfail, s.stencil_fail_bf, s.stencil_zpass_bf, s.stencil_zfail_bf,
-	     sm.stencil_testval, sm.stencil_mask, sm.stencil_writemask, sm.stencil_opval,
-	     sm.stencil_testval_bf, sm.stencil_mask_bf, sm.stencil_writemask_bf, sm.stencil_opval_bf);
+	     c.backface_enable ? "true" : "false", c.stencilfunc, c.stencilfunc_bf, s.stencil_fail,
+	     s.stencil_zpass, s.stencil_zfail, s.stencil_fail_bf, s.stencil_zpass_bf,
+	     s.stencil_zfail_bf, sm.stencil_testval, sm.stencil_mask, sm.stencil_writemask,
+	     sm.stencil_opval, sm.stencil_testval_bf, sm.stencil_mask_bf, sm.stencil_writemask_bf,
+	     sm.stencil_opval_bf);
 }
 
 static void DCheck(const HW::DepthControl& c, const HW::StencilControl& s,
@@ -789,8 +673,6 @@ static void DCheck(const HW::DepthControl& c, const HW::StencilControl& s,
 	// Back-face stencil state is handled separately when enabled.
 	// EXIT_NOT_IMPLEMENTED(c.stencilfunc != 0);
 	// EXIT_NOT_IMPLEMENTED(c.stencilfunc_bf != 0);
-	EXIT_NOT_IMPLEMENTED(c.color_writes_on_depth_fail_enable != false);
-	EXIT_NOT_IMPLEMENTED(c.color_writes_on_depth_pass_disable != false);
 	// EXIT_NOT_IMPLEMENTED(s.stencil_fail != 0);
 	// EXIT_NOT_IMPLEMENTED(s.stencil_zpass != 0);
 	// EXIT_NOT_IMPLEMENTED(s.stencil_zfail != 0);
diff --git a/src/graphics/host_gpu/renderer/depthRenderTarget.cpp b/src/graphics/host_gpu/renderer/depthRenderTarget.cpp
index e541b9f58..5351ca103 100644
--- a/src/graphics/host_gpu/renderer/depthRenderTarget.cpp
+++ b/src/graphics/host_gpu/renderer/depthRenderTarget.cpp
@@ -108,9 +108,10 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 	const auto& sc          = hw.GetStencilControl();
 	const auto& sm          = hw.GetStencilMask();
 	const bool  has_stencil = z.stencil_info.format != Prospero::StencilFormat::kInvalid;
-	const bool  depth_active =
-	    dc.z_enable || dc.z_write_enable || dc.depth_bounds_enable || rc.depth_clear_enable;
-	const bool stencil_active = has_stencil && (dc.stencil_enable || rc.stencil_clear_enable);
+	const bool depth_active = dc.z_enable || dc.z_write_enable || dc.depth_bounds_enable ||
+	                          rc.depth_clear_enable || rc.copy_depth_to_color;
+	const bool stencil_active =
+	    has_stencil && (dc.stencil_enable || rc.stencil_clear_enable || rc.copy_stencil_to_color);
 	if (!depth_active && !stencil_active) {
 		return;
 	}
@@ -127,22 +128,14 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 	    !z.stencil_info.expclear_enabled && !z.stencil_info.partially_resident &&
 	    z.depth_view.slice_start == 0 && z.depth_view.slice_max == 0 &&
 	    z.depth_view.current_mip_level == 0 && !z.depth_view.depth_write_disable &&
-	    !z.depth_view.stencil_write_disable && z.depth_info.addr5_swizzle_mask == 0 &&
-	    z.depth_info.array_mode == 0 && z.depth_info.pipe_config == 0 &&
-	    z.depth_info.bank_width == 0 && z.depth_info.bank_height == 0 &&
-	    z.depth_info.macro_tile_aspect == 0 && z.depth_info.num_banks == 0 &&
-	    z.htile_surface.linear == 0 && z.htile_surface.full_cache == 0 &&
-	    z.htile_surface.htile_uses_preload_win == 0 && z.htile_surface.preload == 0 &&
-	    z.htile_surface.prefetch_width == 0 && z.htile_surface.prefetch_height == 0 &&
-	    z.htile_surface.dst_outside_zero_to_one == 0 && z.z_read_base_addr == 0 &&
-	    z.z_write_base_addr == 0 && z.stencil_read_base_addr == 0 &&
-	    z.stencil_write_base_addr == 0 && z.htile_data_base_addr == 0 &&
+	    !z.depth_view.stencil_write_disable && z.z_read_base_addr == 0 && z.z_write_base_addr == 0 &&
+	    z.stencil_read_base_addr == 0 && z.stencil_write_base_addr == 0 &&
+	    z.htile_data_base_addr == 0 &&
 	    // DB_DEPTH_SIZE_XY is independent state and may remain programmed after the attachment
 	    // formats and addresses are unbound. A zero encoding is the valid 1x1 value, so its
 	    // presence alone must not manufacture a depth attachment.
-	    !z.z_info.htile_acceleration && !z.width_height_valid && !z.pitch_height_valid &&
-	    z.size.x_max == 0 && z.size.y_max == 0 && z.pitch_div8_minus1 == 0 &&
-	    z.height_div8_minus1 == 0 && z.slice_div64_minus1 == 0 && z.width == 0 && z.height == 0;
+	    !z.z_info.htile_acceleration && z.shading_rate_encoding == 0 && z.size.x_max == 0 &&
+	    z.size.y_max == 0;
 	if (attachment_unbound) {
 		static std::atomic_bool logged = false;
 		if (!logged.exchange(true, std::memory_order_relaxed)) {
@@ -165,17 +158,12 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 			DepthFatal("invalid depth view: base=%u last=%u", z.depth_view.slice_start,
 			           z.depth_view.slice_max);
 	}
-	if (rc.copy_centroid || rc.copy_sample != 0 || z.z_info.expclear_enabled ||
+	if (rc.copy_depth_to_color || rc.copy_stencil_to_color || rc.copy_centroid ||
+	    rc.copy_sample != 0 || z.z_info.expclear_enabled ||
 	    z.stencil_info.expclear_enabled || z.z_info.partially_resident ||
 	    z.stencil_info.partially_resident || z.z_info.max_mip_level != 0 ||
-	    z.depth_view.current_mip_level != 0 || z.depth_info.addr5_swizzle_mask != 0 ||
-	    z.depth_info.array_mode != 0 || z.depth_info.pipe_config != 0 ||
-	    z.depth_info.bank_width != 0 || z.depth_info.bank_height != 0 ||
-	    z.depth_info.macro_tile_aspect != 0 || z.depth_info.num_banks != 0 ||
-	    z.htile_surface.linear != 0 || z.htile_surface.full_cache != 0 ||
-	    z.htile_surface.htile_uses_preload_win != 0 || z.htile_surface.preload != 0 ||
-	    z.htile_surface.prefetch_width != 0 || z.htile_surface.prefetch_height != 0 ||
-	    z.htile_surface.dst_outside_zero_to_one != 0 || z.z_read_base_addr == 0 ||
+	    z.depth_view.current_mip_level != 0 || z.shading_rate_encoding != 0 ||
+	    z.z_read_base_addr == 0 ||
 	    (!z.depth_view.depth_write_disable && z.z_write_base_addr != z.z_read_base_addr) ||
 	    (z.z_read_base_addr & 0xffffu) != 0 ||
 	    dc.zfunc > static_cast<uint8_t>(vk::CompareOp::eAlways)) {
@@ -203,18 +191,13 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 			DepthFatal("HTile clear tracking supports at most 32 slices");
 		}
 	}
-	const bool size_xy_valid = z.size.valid;
-	const bool wh_valid      = z.width_height_valid && z.width != 0 && z.height != 0;
-	if (!size_xy_valid && !wh_valid) {
+	if (!z.size.valid) {
 		DepthFatal("missing depth extent");
 	}
-	const uint32_t width  = size_xy_valid ? static_cast<uint32_t>(z.size.x_max) + 1u : z.width;
-	const uint32_t height = size_xy_valid ? static_cast<uint32_t>(z.size.y_max) + 1u : z.height;
-	if (width > 16384 || height > 16384 ||
-	    (size_xy_valid && wh_valid && (width != z.width || height != z.height)) ||
-	    (!z.pitch_height_valid &&
-	     (z.pitch_div8_minus1 != 0 || z.height_div8_minus1 != 0 || z.slice_div64_minus1 != 0))) {
-		DepthFatal("inconsistent depth extent or encoded layout");
+	const uint32_t width  = static_cast<uint32_t>(z.size.x_max) + 1u;
+	const uint32_t height = static_cast<uint32_t>(z.size.y_max) + 1u;
+	if (width > 16384 || height > 16384) {
+		DepthFatal("invalid depth extent");
 	}
 	const auto* policy = FindDepthFormatPolicy(z.z_info.format);
 	if (policy == nullptr) {
@@ -229,11 +212,6 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 	const auto     guest_format = policy->guest_format;
 	const uint32_t bytes        = policy->bytes_per_element;
 	const auto     pitch        = TileGetDepthPitch(width, bytes, z.z_info.num_samples);
-	if (z.pitch_height_valid && ((static_cast<uint64_t>(z.pitch_div8_minus1) + 1u) * 8u != pitch ||
-	                             (static_cast<uint64_t>(z.height_div8_minus1) + 1u) * 8u !=
-	                                 ((static_cast<uint64_t>(height) + 7u) & ~7ull))) {
-		DepthFatal("encoded depth pitch or height mismatch");
-	}
 	TileSizeAlign depth_size {};
 	TileSizeAlign stencil_size {};
 	TileSizeAlign htile_size {};
@@ -244,14 +222,6 @@ void RenderExecutor::ResolveRenderDepthTarget(uint64_t submit_id, CommandBuffer&
 	    (has_htile != (htile_size.align == 32768 && htile_size.size != 0))) {
 		DepthFatal("unsupported depth/stencil/HTile footprint");
 	}
-	if (z.pitch_height_valid &&
-	    (static_cast<uint64_t>(z.slice_div64_minus1) + 1u) * 64u != depth_size.size) {
-		DepthFatal("depth footprint mismatch: extent=%ux%u pitch=%u expected=0x%016" PRIx64
-		           " align=0x%016" PRIx64 " encoded_valid=%u encoded=0x%016" PRIx64,
-		           width, height, pitch, depth_size.size, depth_size.align,
-		           z.pitch_height_valid ? 1u : 0u,
-		           (static_cast<uint64_t>(z.slice_div64_minus1) + 1u) * 64u);
-	}
 	if (depth_size.size > UINT64_MAX / view.image_layers ||
 	    stencil_size.size > UINT64_MAX / view.image_layers ||
 	    htile_size.size > UINT64_MAX / view.image_layers) {
diff --git a/src/graphics/host_gpu/renderer/renderDraw.cpp b/src/graphics/host_gpu/renderer/renderDraw.cpp
index 78ec7cd39..feb966a6a 100644
--- a/src/graphics/host_gpu/renderer/renderDraw.cpp
+++ b/src/graphics/host_gpu/renderer/renderDraw.cpp
@@ -411,7 +411,7 @@ static void SetGraphicsDynamicParams(const CommandBuffer& buffer, vk::CommandBuf
 static bool DrawHasValidVertexShader(const HW::Shader& sh_ctx) {
 
 	const auto& vs = sh_ctx.GetVs();
-	return vs.gs_regs.chksum != 0 && ShaderAddressValid(vs.es_regs.data_addr);
+	return ShaderAddressValid(vs.es_regs.data_addr);
 }
 
 static bool PixelShaderHasDepthOrCoverageSideEffects(const HW::ShaderRegisters& sh_regs) {
@@ -443,7 +443,6 @@ static bool ShouldSkipGeShader(const CommandBuffer& buffer) {
 	};
 
 	const bool ps5_ngg_vertex_path = stages == 0x02002000 && vertex_info.es_regs.data_addr != 0 &&
-	                                 vertex_info.gs_regs.chksum != 0 &&
 	                                 sh_regs.m_vgtGsMaxVertOut == 0x00000000 &&
 	                                 is_known_gs_out_prim_type(sh_regs.m_vgtGsOutPrimType);
 
@@ -1450,7 +1449,7 @@ void RenderExecutor::DrawAuto(uint64_t submit_id, CommandBuffer& buffer, uint32_
 		if (graphics_debug_dump_enabled()) {
 			LOGF("DrawIndexAuto: skipping rect-list draw with no VS param exports and PS inputs: "
 			     "ps_inputs=%u ps=0x%016" PRIx64 " es=0x%016" PRIx64 " gs=0x%016" PRIx64 "\n",
-			     state.ps_input_info.input_num, sh_ctx.GetPs().ps_regs.chksum,
+			     state.ps_input_info.input_num, sh_ctx.GetPs().ps_regs.data_addr,
 			     sh_ctx.GetVs().es_regs.data_addr, sh_ctx.GetVs().gs_regs.data_addr);
 		}
 		ResetBindings();
diff --git a/src/graphics/shader/shader.cpp b/src/graphics/shader/shader.cpp
index 2648cabe4..0c5c89ec9 100644
--- a/src/graphics/shader/shader.cpp
+++ b/src/graphics/shader/shader.cpp
@@ -173,6 +173,11 @@ static const ShaderBinaryInfo* GetBinaryInfo(const uint32_t* code) {
 	return nullptr;
 }
 
+static uint64_t GetDeclaredShaderHash(uint64_t shader_addr) {
+	const auto* header = GetBinaryInfo(reinterpret_cast<const uint32_t*>(shader_addr));
+	return header != nullptr ? (static_cast<uint64_t>(header->hash1) << 32u) | header->hash0 : 0;
+}
+
 static ShaderParams GetShaderParams(uint64_t shader_addr, const char* label, uint64_t declared_hash,
 	                                std::span<const uint32_t> user_data,
 	                                const ShaderMappedData& data) {
@@ -210,7 +215,6 @@ static void vs_check(const HW::VertexShaderInfo& vs, const HW::ShaderRegisters&
 	};
 	const bool ps5_ngg_passthrough_triangle_path =
 	    vs.es_regs.data_addr != 0 && vs.gs_regs.data_addr == vs.es_regs.data_addr &&
-	    vs.gs_regs.chksum != 0 &&
 	    sh.m_geNggSubgrpCntl == 0x00000001 && sh.m_vgtGsMaxVertOut == 0x00000003 &&
 	    sh.m_vgtGsOutPrimType == 0x00000002 && sh.m_geMaxOutputPerSubgroup <= 0x000000c0;
 
@@ -275,7 +279,6 @@ static void ps_check(const HW::PsStageRegisters& ps, const HW::ShaderRegisters&
 	// EXIT_NOT_IMPLEMENTED(ps.m_spiShaderPgmRsrc1Ps != 0x002c0000);
 	// EXIT_NOT_IMPLEMENTED(ps.m_spiShaderPgmRsrc2Ps != 0x00000000);
 	// EXIT_NOT_IMPLEMENTED(ps.vgprs != 0x00 && ps.vgprs != 0x01);
-	// EXIT_NOT_IMPLEMENTED(ps.sgprs != 0x00 && ps.sgprs != 0x01);
 	EXIT_NOT_IMPLEMENTED(ps.rsrc1.priority != 0);
 	EXIT_NOT_IMPLEMENTED(ps.rsrc1.float_mode != 192);
 	EXIT_NOT_IMPLEMENTED(ps.rsrc1.dx10_clamp != true);
@@ -365,8 +368,10 @@ static void cs_check(const HW::CsStageRegisters& cs, const HW::ShaderRegisters&
 	// EXIT_NOT_IMPLEMENTED(cs.num_thread_y != 0x00000001);
 	// EXIT_NOT_IMPLEMENTED(cs.num_thread_z != 0x00000001);
 	// EXIT_NOT_IMPLEMENTED(cs.vgprs != 0x00 && cs.vgprs != 0x01);
-	// EXIT_NOT_IMPLEMENTED(cs.sgprs != 0x01 && cs.sgprs != 0x02);
-	EXIT_NOT_IMPLEMENTED(cs.bulky != 0x00);
+	EXIT_NOT_IMPLEMENTED(cs.priority != 0x00);
+	EXIT_NOT_IMPLEMENTED(cs.debug_mode != false);
+	EXIT_NOT_IMPLEMENTED(cs.require_forward_progress != false);
+	EXIT_NOT_IMPLEMENTED(cs.shared_vgprs != 0x00);
 	EXIT_NOT_IMPLEMENTED(cs.scratch_en != 0x00);
 	// EXIT_NOT_IMPLEMENTED(cs.user_sgpr != 0x0c);
 	if (cs.tgid_x_en == 0x00) {
@@ -689,7 +694,7 @@ static bool ShaderGetStaticInputInfoVS(const HW::VertexShaderInfo& regs,
 	info.export_count      = static_cast<int>(sh.GetExportCount());
 	info.pa_cl_vs_out_cntl = sh.m_paClVsOutCntl;
 
-	EXIT_NOT_IMPLEMENTED(regs.es_regs.data_addr == 0 || regs.gs_regs.chksum == 0);
+	EXIT_NOT_IMPLEMENTED(regs.es_regs.data_addr == 0);
 
 	uint64_t                shader_addr   = regs.es_regs.data_addr;
 	const HW::UserSgprInfo& user_sgpr     = regs.gs_user_sgpr;
@@ -698,8 +703,8 @@ static bool ShaderGetStaticInputInfoVS(const HW::VertexShaderInfo& regs,
 
 	if (data.user_data == nullptr) {
 		LOGF("ShaderGetInputInfoVS(): no AGC user data for shader=0x%016" PRIx64 " es=0x%016" PRIx64
-		     " gs=0x%016" PRIx64 " chksum=0x%016" PRIx64 " user_sgpr_num=%u\n",
-		     shader_addr, regs.es_regs.data_addr, regs.gs_regs.data_addr, regs.gs_regs.chksum,
+		     " gs=0x%016" PRIx64 " user_sgpr_num=%u\n",
+		     shader_addr, regs.es_regs.data_addr, regs.gs_regs.data_addr,
 		     static_cast<uint32_t>(user_sgpr_num));
 	}
 	ShaderVertexMetadata metadata;
@@ -979,7 +984,7 @@ ShaderParams PrepareProgram(const HW::VertexShaderInfo& regs, const HW::ShaderRe
 		EXIT("failed to prepare vertex shader program\n");
 	}
 	return GetShaderParams(
-	    regs.es_regs.data_addr, "ShaderRecompiler VS", regs.gs_regs.chksum,
+	    regs.es_regs.data_addr, "ShaderRecompiler VS", GetDeclaredShaderHash(regs.es_regs.data_addr),
 	    std::span<const uint32_t>(regs.gs_user_sgpr.value, regs.gs_regs.rsrc2.user_sgpr), data);
 }
 
@@ -991,7 +996,7 @@ ShaderParams PrepareProgram(
 	const auto data = ShaderGetMappedData(regs.ps_regs.data_addr, "ShaderGetInputInfoPS():");
 	ShaderGetStaticInputInfoPS(regs, sh, vs_info, target_export_mapping, data, ps_info);
 	return GetShaderParams(
-	    regs.ps_regs.data_addr, "ShaderRecompiler PS", regs.ps_regs.chksum,
+	    regs.ps_regs.data_addr, "ShaderRecompiler PS", GetDeclaredShaderHash(regs.ps_regs.data_addr),
 	    std::span<const uint32_t>(regs.ps_user_sgpr.value, regs.ps_regs.rsrc2.user_sgpr), data);
 }
 
@@ -999,11 +1004,8 @@ ShaderParams PrepareProgram(const HW::ComputeShaderInfo& regs, const HW::ShaderR
                             ShaderComputeInputInfo& info) {
 	const auto data = ShaderGetMappedData(regs.cs_regs.data_addr, "ShaderGetInputInfoCS():");
 	ShaderGetStaticInputInfoCS(regs, sh, data, info);
-	const auto* header = GetBinaryInfo(reinterpret_cast<const uint32_t*>(regs.cs_regs.data_addr));
-	const auto declared_hash =
-	    header != nullptr ? (static_cast<uint64_t>(header->hash1) << 32u) | header->hash0 : 0;
 	return GetShaderParams(
-	    regs.cs_regs.data_addr, "ShaderRecompiler CS", declared_hash,
+	    regs.cs_regs.data_addr, "ShaderRecompiler CS", GetDeclaredShaderHash(regs.cs_regs.data_addr),
 	    std::span<const uint32_t>(regs.cs_user_sgpr.value, regs.cs_regs.user_sgpr), data);
 }
 
diff --git a/tests/ShaderRecompilerComputeTests.cpp b/tests/ShaderRecompilerComputeTests.cpp
index 00db9091c..774038e12 100644
--- a/tests/ShaderRecompilerComputeTests.cpp
+++ b/tests/ShaderRecompilerComputeTests.cpp
@@ -7060,8 +7060,7 @@ public:
       registers.SetColorAttrib3(0,
                                 {.tile_mode = Prospero::TileMode::kRenderTarget,
                                  .dimension = 0,
-                                 .cmask_pipe_aligned = true,
-                                 .dcc_pipe_aligned = true});
+                                 .metadata_pipe_aligned = true});
       registers.SetRenderTargetMask(0x0f);
       scheduler.Begin(registers, user_config, shaders);
 
@@ -7094,7 +7093,7 @@ public:
                   rendering.width == width && rendering.height == height &&
                   rendering.num_layers == 1 &&
                   rendering.num_color_attachments == 1,
-              "SDK dimension=0 did not create a 512x1 Vulkan attachment");
+              "dimension=0 did not create a 512x1 Vulkan attachment");
 
       RenderExecutorTestAccess::ResetBindings(executor);
       resources.UnmapMemory(base, allocation_size);
@@ -7153,8 +7152,7 @@ public:
                                 {.depth = 31,
                                  .tile_mode = Prospero::TileMode::kRenderTarget,
                                  .dimension = 2,
-                                 .cmask_pipe_aligned = true,
-                                 .dcc_pipe_aligned = true});
+                                 .metadata_pipe_aligned = true});
       constexpr uint64_t dcc_address = base + allocation_size - 0x1000;
       registers.SetColorDccAddr(0, {.addr = dcc_address});
       registers.SetColorClearWord0(0, {.word0 = 0});
@@ -7198,7 +7196,7 @@ public:
               static_cast<bool>(image.backing.flags &
                                 vk::ImageCreateFlagBits::e2DArrayCompatible) &&
               image.usage.render_target && image.IsGpuModified(),
-          "dimension=2/depth=31 did not create the SDK-defined 32x32x32 "
+          "dimension=2/depth=31 did not create the expected 32x32x32 "
           "backing and 2D "
           "attachment slice");
 
@@ -7367,8 +7365,7 @@ public:
       registers.SetColorAttrib2(0, {.height = 255, .width = 255});
       registers.SetColorAttrib3(0, {.tile_mode = tile_case.tile,
                                     .dimension = 1,
-                                    .cmask_pipe_aligned = true,
-                                    .dcc_pipe_aligned = true});
+                                    .metadata_pipe_aligned = true});
       registers.SetRenderTargetMask(0x0f);
       scheduler.Begin(registers, user_config, shaders);
 
@@ -7477,8 +7474,7 @@ public:
       registers.SetColorAttrib2(0, {.height = 63, .width = 63});
       registers.SetColorAttrib3(0, {.tile_mode = Prospero::TileMode::kDepth,
                                     .dimension = 1,
-                                    .cmask_pipe_aligned = true,
-                                    .dcc_pipe_aligned = true});
+                                    .metadata_pipe_aligned = true});
       registers.SetRenderTargetMask(0x0f);
       scheduler.Begin(registers, user_config, shaders);
 
@@ -24394,6 +24390,147 @@ void CheckPm4StencilInfoValueLane(RenderContext &renderer) {
   std::printf("[host]    %-32s ok\n", "Pm4StencilInfoValueLane");
 }
 
+void CheckPm4NativeTargetGeometryRegisters(RenderContext &renderer) {
+  GraphicsInitJmpTables();
+  CommandProcessor packet(renderer, 0);
+  CommandProcessor indirect(renderer, 0);
+
+  const auto write_context = [](CommandProcessor &processor, uint32_t offset,
+                                uint32_t value) {
+    std::array<uint32_t, 3> command{
+        KYTY_PM4(3, Pm4::IT_SET_CONTEXT_REG, Pm4::R_ZERO), offset, value};
+    Pm4Execution execution;
+    return processor.Process(execution, command) == Pm4ProcessResult::Complete;
+  };
+
+  constexpr uint32_t color_slot = 7;
+  constexpr uint32_t width_minus_one = 1919;
+  constexpr uint32_t height_minus_one = 1079;
+  constexpr uint32_t depth_minus_one = 5;
+  constexpr uint32_t max_mip = 3;
+  constexpr uint32_t dimension_3d = 2;
+  constexpr uint32_t attrib2_value =
+      height_minus_one | (width_minus_one << 14u) | (max_mip << 28u);
+  constexpr uint32_t attrib3_value =
+      depth_minus_one |
+      (static_cast<uint32_t>(Prospero::TileMode::kStandard64KB) << 14u) |
+      (dimension_3d << 24u) | (1u << 26u) | (1u << 30u);
+
+  const bool color_packets_complete =
+      write_context(packet, Pm4::CB_COLOR7_ATTRIB2, attrib2_value) &&
+      write_context(packet, Pm4::CB_COLOR7_ATTRIB3, attrib3_value);
+  g_hw_ctx_indirect_func[Pm4::CB_COLOR7_ATTRIB2](
+      indirect, Pm4::CB_COLOR7_ATTRIB2, attrib2_value);
+  g_hw_ctx_indirect_func[Pm4::CB_COLOR7_ATTRIB3](
+      indirect, Pm4::CB_COLOR7_ATTRIB3, attrib3_value);
+
+  const auto color_matches = [](const HW::RenderTarget &target) {
+    return target.attrib2.width == width_minus_one &&
+           target.attrib2.height == height_minus_one &&
+           target.attrib2.num_mip_levels == max_mip &&
+           target.attrib3.depth == depth_minus_one &&
+           target.attrib3.tile_mode == Prospero::TileMode::kStandard64KB &&
+           target.attrib3.dimension == dimension_3d &&
+           target.attrib3.metadata_pipe_aligned;
+  };
+  Require("Pm4NativeTargetGeometry", "sparse color geometry",
+          color_packets_complete &&
+              color_matches(packet.GetCtx().GetRenderTarget(color_slot)) &&
+              color_matches(indirect.GetCtx().GetRenderTarget(color_slot)) &&
+              !color_matches(packet.GetCtx().GetRenderTarget(0)) &&
+              !color_matches(indirect.GetCtx().GetRenderTarget(0)),
+          "ATTRIB2/ATTRIB3 did not provide native color extent and layout");
+
+  constexpr uint32_t depth_size_value =
+      width_minus_one | (height_minus_one << 16u);
+  const bool depth_packet_complete =
+      write_context(packet, Pm4::DB_DEPTH_SIZE_XY, depth_size_value);
+  g_hw_ctx_indirect_func[Pm4::DB_DEPTH_SIZE_XY](indirect, Pm4::DB_DEPTH_SIZE_XY,
+                                                depth_size_value);
+  const auto depth_matches = [](const HW::DepthRenderTarget &target) {
+    return target.size.valid && target.size.x_max == width_minus_one &&
+           target.size.y_max == height_minus_one;
+  };
+  Require("Pm4NativeTargetGeometry", "native depth geometry",
+          depth_packet_complete &&
+              depth_matches(packet.GetCtx().GetDepthRenderTarget()) &&
+              depth_matches(indirect.GetCtx().GetDepthRenderTarget()),
+          "DB_DEPTH_SIZE_XY did not provide the native depth extent");
+
+  bool legacy_slots_are_unhandled = true;
+  for (uint32_t slot = 0; slot < 8; slot++) {
+    const auto stride = slot * 15u;
+    const std::array legacy_color_slots{
+        Pm4::CB_COLOR0_BASE + stride + 1u,
+        Pm4::CB_COLOR0_BASE + stride + 2u,
+        Pm4::CB_COLOR0_CMASK + stride + 1u,
+        Pm4::CB_COLOR0_FMASK + stride + 1u,
+    };
+    for (const auto offset : legacy_color_slots) {
+      legacy_slots_are_unhandled &= g_hw_ctx_func[offset] == nullptr &&
+                                    g_hw_ctx_indirect_func[offset] == nullptr;
+    }
+  }
+  // These offsets are the removed GCN DB_DEPTH_INFO, DB_DEPTH_SIZE, and
+  // DB_DEPTH_SLICE holes. Keep them numeric so deleting their legacy PM4 names
+  // does not weaken this dispatch-table regression check.
+  constexpr std::array<uint32_t, 3> legacy_depth_slots{0x000fu, 0x0016u,
+                                                       0x0017u};
+  for (const auto offset : legacy_depth_slots) {
+    legacy_slots_are_unhandled &= g_hw_ctx_func[offset] == nullptr &&
+                                  g_hw_ctx_indirect_func[offset] == nullptr;
+  }
+  // Removed GCN PA_SC_NGG_MODE_CNTL.
+  legacy_slots_are_unhandled &= g_hw_ctx_func[0x0314u] == nullptr &&
+                                g_hw_ctx_indirect_func[0x0314u] == nullptr;
+
+  // Removed GCN shader resource/checksum/queue registers. Numeric offsets keep
+  // this check independent of the deleted legacy names.
+  constexpr std::array<uint32_t, 22> legacy_shader_slots{
+      0x000u, 0x001u, 0x002u, 0x003u, 0x030u, 0x081u, 0x0b0u, 0x0bcu,
+      0x100u, 0x101u, 0x130u, 0x14au, 0x14bu, 0x20eu, 0x20fu, 0x210u,
+      0x211u, 0x216u, 0x217u, 0x219u, 0x21au, 0x27du,
+  };
+  for (const auto offset : legacy_shader_slots) {
+    legacy_slots_are_unhandled &= g_hw_sh_func[offset] == nullptr &&
+                                  g_hw_sh_indirect_func[offset] == nullptr;
+  }
+  for (uint32_t offset = 0x0cau; offset <= 0x0ebu; offset++) {
+    legacy_slots_are_unhandled &= g_hw_sh_func[offset] == nullptr &&
+                                  g_hw_sh_indirect_func[offset] == nullptr;
+  }
+
+  constexpr std::array<uint32_t, 1> legacy_uconfig_slots{0x0260u};
+  for (const auto offset : legacy_uconfig_slots) {
+    legacy_slots_are_unhandled &= g_hw_uc_func[offset] == nullptr &&
+                                  g_hw_uc_indirect_func[offset] == nullptr;
+  }
+
+  std::array<uint32_t, 3> index_size_packet{
+      KYTY_PM4(3, Pm4::IT_SET_UCONFIG_REG_INDEX, Pm4::R_ZERO),
+      0x20000000u | Pm4::VGT_INDEX_TYPE,
+      0x441u,
+  };
+  Pm4Execution index_size_execution;
+  const bool native_index_size_packet_complete =
+      packet.Process(index_size_execution, index_size_packet) ==
+          Pm4ProcessResult::Complete &&
+      g_hw_uc_func[Pm4::VGT_INDEX_TYPE] != nullptr &&
+      g_hw_uc_indirect_func[Pm4::VGT_INDEX_TYPE] != nullptr &&
+      g_hw_uc_func[Pm4::IA_MULTI_VGT_PARAM] != nullptr &&
+      g_hw_uc_indirect_func[Pm4::IA_MULTI_VGT_PARAM] != nullptr;
+
+  const bool native_pace_slots_are_handled =
+      g_hw_sh_indirect_func[Pm4::SPI_SHADER_PACE_ID_PS] != nullptr &&
+      g_hw_sh_indirect_func[Pm4::SPI_SHADER_PACE_ID_GS] != nullptr &&
+      g_hw_sh_indirect_func[Pm4::COMPUTE_PACE_ID] != nullptr;
+  Require("Pm4NativeTargetGeometry", "legacy register holes",
+          legacy_slots_are_unhandled && native_pace_slots_are_handled &&
+              native_index_size_packet_complete,
+          "a removed GCN register has a handler or a native packet is not handled");
+  std::printf("[host]    %-32s ok\n", "Pm4NativeTargetGeometry");
+}
+
 void CheckPm4DirectShaderRegisterFallback(RenderContext &renderer) {
   GraphicsInitJmpTables();
   CommandProcessor processor(renderer, 0);
@@ -25153,6 +25290,7 @@ int main(int argc, char **argv) {
   }
   if (argc == 2 && std::strcmp(argv[1], "--context-state-only") == 0) {
     VulkanHarness vulkan;
+    CheckPm4NativeTargetGeometryRegisters(vulkan.RuntimeRenderer());
     CheckPm4BlendColorRegisterRanges(vulkan.RuntimeRenderer());
     CheckPm4PolygonOffsetRegisters(vulkan.RuntimeRenderer());
     CheckPm4ContextStateOperations(vulkan.RuntimeRenderer());
@@ -25332,6 +25470,7 @@ int main(int argc, char **argv) {
   CheckPm4AcquireMemNoOp(vulkan.RuntimeRenderer());
   CheckPm4SyntheticOcclusionCounterDump(vulkan.RuntimeRenderer());
   CheckPm4StencilInfoValueLane(vulkan.RuntimeRenderer());
+  CheckPm4NativeTargetGeometryRegisters(vulkan.RuntimeRenderer());
   CheckPm4DirectShaderRegisterFallback(vulkan.RuntimeRenderer());
   CheckPm4GuardBandRegisterRanges(vulkan.RuntimeRenderer());
   CheckPm4BlendColorRegisterRanges(vulkan.RuntimeRenderer());
diff --git a/tests/shaderCfgTests.cpp b/tests/shaderCfgTests.cpp
index 324579969..5945c95b1 100644
--- a/tests/shaderCfgTests.cpp
+++ b/tests/shaderCfgTests.cpp
@@ -28,6 +28,7 @@
 #include "graphics/shader/shaderCompiler.h"
 #include "libs/agc.h"
 #include "spirv-tools/libspirv.hpp"
+#include "xxhash.h"
 
 #include <algorithm>
 #include <array>
@@ -8887,9 +8888,6 @@ void TestNewShaderRecompilerAuxPositionExports() {
           "compilation");
 #endif
 
-  HW::VertexShaderInfo regs{};
-  regs.es_regs.data_addr = 1;
-  regs.gs_regs.chksum = 1;
   ShaderVertexInputInfo key0{};
   ShaderVertexInputInfo key1{};
   key1.pa_cl_vs_out_cntl = 1;
@@ -10230,7 +10228,6 @@ void TestRenderTargetReverseExportMapping() {
         "pixel shader cache identity omitted the render-target export mapping");
 
   regs.ps_regs.data_addr = reinterpret_cast<uint64_t>(shader);
-  regs.ps_regs.chksum = 0xf16ab6f000000001ull;
   ShaderMappedData mapped{};
   mapped.code_size_bytes = sizeof(shader);
   ShaderMapUserData(regs.ps_regs.data_addr, mapped);
@@ -11118,7 +11115,6 @@ void TestNewShaderRecompilerPixelPipelineEntry() {
 
   HW::PixelShaderInfo regs{};
   regs.ps_regs.data_addr = reinterpret_cast<uint64_t>(shader);
-  regs.ps_regs.chksum = 0x1234567800000001ull;
   ShaderMappedData mapped{};
   mapped.code_size_bytes = sizeof(shader);
   ShaderMapUserData(regs.ps_regs.data_addr, mapped);
@@ -11128,7 +11124,8 @@ void TestNewShaderRecompilerPixelPipelineEntry() {
   ShaderVertexInputInfo vertex_info{};
   ShaderPixelInputInfo input_info{};
   const auto params = PrepareProgram(regs, sh, vertex_info, mappings, input_info);
-  Check(params.hash == regs.ps_regs.chksum && params.code.data() == shader,
+  Check(params.hash == XXH3_64bits(params.code.data(), params.code.size_bytes()) &&
+            params.code.data() == shader,
         "pixel shader program parameters lost source identity");
 
   const uint32_t vcc_load_shader[] = {
@@ -11146,7 +11143,6 @@ void TestNewShaderRecompilerPixelPipelineEntry() {
 
   HW::PixelShaderInfo vcc_regs{};
   vcc_regs.ps_regs.data_addr = reinterpret_cast<uint64_t>(vcc_load_shader);
-  vcc_regs.ps_regs.chksum = 0x6306606500000001ull;
   vcc_regs.ps_regs.rsrc2.user_sgpr = 29;
   vcc_regs.ps_user_sgpr.value[27] = static_cast<uint32_t>(table_address);
   vcc_regs.ps_user_sgpr.value[28] = static_cast<uint32_t>(table_address >> 32u);
@@ -11423,11 +11419,9 @@ void TestPixelProgramCacheBindingIdentity() {
   Check(MakeStageStaticKey(no_depth_export) != MakeStageStaticKey(shifted_push),
         "pixel shader identity omitted graphics push-bank placement");
 
-  auto check_program_identity = [&](const uint32_t *shader,
-                                    uint64_t checksum) {
+  auto check_program_identity = [&](const uint32_t *shader) {
     HW::PixelShaderInfo regs{};
     regs.ps_regs.data_addr = reinterpret_cast<uint64_t>(shader);
-    regs.ps_regs.chksum = checksum;
     ShaderMappedData mapped{};
     mapped.code_size_bytes = sizeof(uint32_t);
     ShaderMapUserData(regs.ps_regs.data_addr, mapped);
@@ -11453,8 +11447,8 @@ void TestPixelProgramCacheBindingIdentity() {
     return std::pair {first_params.hash, first_key};
   };
 
-  const auto request_01 = check_program_identity(shader_01, 0);
-  const auto request_10 = check_program_identity(shader_10, 0);
+  const auto request_01 = check_program_identity(shader_01);
+  const auto request_10 = check_program_identity(shader_10);
   Check(request_01 == request_10,
         "relocated identical pixel programs did not share their source identity");
 
@@ -11465,7 +11459,6 @@ void TestPixelProgramCacheBindingIdentity() {
   };
   HW::PixelShaderInfo push_regs{};
   push_regs.ps_regs.data_addr = reinterpret_cast<uint64_t>(push_shader);
-  push_regs.ps_regs.chksum = 0x91a27e6300000003ull;
   push_regs.ps_regs.rsrc2.user_sgpr = 4;
   ShaderMappedData push_mapped{};
   push_mapped.code_size_bytes = sizeof(push_shader);