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shader: return the first source when both float min/max inputs are NaN
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@@ -27897,7 +27897,8 @@ TestCase VectorMinMaxF32NanAndSignedZeroEdges() {
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}
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// MIN/MAX/MIN3/MAX3 on runtime inputs, so no compiler can fold them. The expected bits follow
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// the emulated rules: a NaN operand yields the other operand and signed zeros are ordered.
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// the emulated rules: a NaN operand yields the other (S0 for two NaNs) and signed zeros are
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// ordered.
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// Denormal operands are left out; their expected results are not pinned down here.
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TestCase VectorMinMaxF32RuntimeEdges(u32 wave) {
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using O = ShaderOpcode;
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@@ -27905,14 +27906,14 @@ TestCase VectorMinMaxF32RuntimeEdges(u32 wave) {
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const auto zero = [](u32 v) { return (v & 0x7fffffffu) == 0u; };
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const auto value = [](u32 v) { return std::bit_cast<float>(v); };
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const auto min2 = [&](u32 a, u32 b) {
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if (nan(a)) return b;
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if (nan(b)) return a;
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if (nan(a)) return b;
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if (zero(a) && zero(b)) return a | b;
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return value(a) < value(b) ? a : b;
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};
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const auto max2 = [&](u32 a, u32 b) {
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if (nan(a)) return b;
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if (nan(b)) return a;
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if (nan(a)) return b;
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if (zero(a) && zero(b)) return a & b;
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return value(a) >= value(b) ? a : b;
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};
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@@ -27922,7 +27923,8 @@ TestCase VectorMinMaxF32RuntimeEdges(u32 wave) {
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{0x40000000u, 0x7fa00001u, 0xc0000000u}, {0x80000000u, 0x00000000u, 0x80000000u},
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{0x00000000u, 0x80000000u, 0x00000000u}, {0x80000000u, 0x80000000u, 0x00000000u},
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{0xff800000u, 0x7f800000u, 0x00000000u}, {0x7fc00000u, 0x00000000u, 0x80000000u},
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{0xffc05678u, 0x3f800000u, 0x7fa00001u}, {0xbf800000u, 0xc0000000u, 0x7fc01234u}};
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{0xffc05678u, 0x3f800000u, 0x7fa00001u}, {0xbf800000u, 0xc0000000u, 0x7fc01234u},
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{0x7fc01234u, 0xffc05678u, 0x7fa00001u}, {0xffc05678u, 0x7fc01234u, 0x3f800000u}};
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TestCase test;
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test.name = "VectorMinMaxF32RuntimeEdges";
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test.has_compute_info = true;
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