mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-25 04:16:55 +01:00
gpu: remove the PS4-era constant engine, marker NOPs and EVENT_WRITE_EOP/EOS packets
This commit is contained in:
nmzik
@@ -50,13 +50,6 @@ private:
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class CommandProcessor {
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public:
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struct FlipInfo {
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int handle = 0;
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int index = 0;
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int flip_mode = 0;
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int64_t flip_arg = 0;
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};
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CommandProcessor(RenderContext& renderer, int interrupt_event_id)
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: m_renderer(renderer), m_interrupt_event_id(interrupt_event_id) {}
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~CommandProcessor() = default;
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@@ -90,18 +83,13 @@ public:
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void DrawIndirectMulti(uint32_t data_offset, uint32_t max_count_or_count,
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const volatile uint32_t* count_addr, uint32_t stride_in_bytes,
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IndirectDrawRegisters registers, uint32_t draw_initiator, bool indexed);
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void WriteAtEndOfPipe32(uint32_t cache_policy, uint32_t event_write_dest,
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uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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void WriteAtEndOfPipe32(uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t event_write_source, void* dst_gpu_addr, uint32_t value,
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uint32_t interrupt_selector, uint32_t interrupt_context_id = 0);
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void WriteAtEndOfPipe64(uint32_t cache_policy, uint32_t event_write_dest,
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uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t interrupt_selector, uint32_t interrupt_context_id);
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void WriteAtEndOfPipe64(uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t event_write_source, void* dst_gpu_addr, uint64_t value,
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uint32_t interrupt_selector, uint32_t interrupt_context_id = 0);
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void Flip();
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void Flip(void* dst_gpu_addr, uint32_t value);
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void FlipWithInterrupt(uint32_t eop_event_type, uint32_t cache_action, void* dst_gpu_addr,
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uint32_t value);
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uint32_t interrupt_selector, uint32_t interrupt_context_id);
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void Flip(int handle, int index, int flip_mode, int64_t flip_arg);
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void PrepareCpuFlip(uint64_t request_id);
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void SynchronizeGpu();
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void TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id);
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@@ -111,19 +99,7 @@ public:
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void WaitFlipDone(uint32_t video_out_handle, uint32_t display_buffer_index);
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void TriggerEvent(uint32_t event_type, uint32_t event_index, uint64_t event_address = 0);
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void SetUserDataMarker(HW::UserSgprType type) { m_user_data_marker = type; }
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[[nodiscard]] HW::UserSgprType GetUserDataMarker() const { return m_user_data_marker; }
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void ResetDeCe();
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void SetCeComplete(bool complete) { m_ce_complete = complete; }
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void WaitCe();
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void WaitDeDiff(uint32_t diff);
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void WaitForRewind(bool valid);
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void IncrementDe();
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void IncrementCe();
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void WriteConstRam(uint32_t offset, const uint32_t* src, uint32_t dw_num);
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void DumpConstRam(uint32_t* dst, uint32_t offset, uint32_t dw_num);
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template <typename T>
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void WaitRegMem(uint32_t func, const T* addr, T ref, T mask, uint32_t poll, uint32_t wait_op);
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@@ -140,18 +116,15 @@ public:
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Pm4ProcessResult Process(Pm4Execution& execution, std::span<const uint32_t> commands);
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void ProcessIndirectBuffer(std::span<const uint32_t> commands, bool chain);
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void SetFlip(const FlipInfo& flip) { m_flip = flip; }
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[[nodiscard]] uint64_t GetSubmitId() const { return m_submit_id; }
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void SetSubmitId(uint64_t submit_id) { m_submit_id = submit_id; }
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[[nodiscard]] bool IsAsyncComputeQueue() const { return m_interrupt_event_id >= 0x20; }
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private:
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template <typename T>
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void WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_write_dest, uint32_t eop_event_type,
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uint32_t cache_action, uint32_t event_index, uint32_t event_write_source,
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void* dst_gpu_addr, T value, uint32_t interrupt_selector,
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uint32_t interrupt_context_id);
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void WriteAtEndOfPipe(uint32_t eop_event_type, uint32_t cache_action, uint32_t event_index,
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uint32_t event_write_source, void* dst_gpu_addr, T value,
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uint32_t interrupt_selector, uint32_t interrupt_context_id);
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void ProcessPm4(Pm4Execution& execution);
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void SuspendPm4();
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uint32_t NumInstances();
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@@ -159,30 +132,22 @@ private:
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CommandScheduler& GetScheduler() const { return m_renderer.GetCommandScheduler(); }
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CommandBuffer& CurrentBuffer() { return GetScheduler().Current(); }
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RenderContext& m_renderer;
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HW::Context m_ctx;
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HW::Context m_saved_ctx;
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bool m_context_state_pushed = false;
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HW::UserConfig m_ucfg;
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HW::Shader m_sh_ctx;
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HW::UserSgprType m_user_data_marker = HW::UserSgprType::Unknown;
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uint32_t m_index_type_and_size = 0;
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uint32_t m_index_buffer_size = 0;
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uint64_t m_index_base_addr = 0;
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uint64_t m_draw_indirect_args_base_addr = 0;
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uint64_t m_dispatch_indirect_args_base_addr = 0;
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RenderContext& m_renderer;
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HW::Context m_ctx;
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HW::Context m_saved_ctx;
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bool m_context_state_pushed = false;
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HW::UserConfig m_ucfg;
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HW::Shader m_sh_ctx;
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uint32_t m_index_type_and_size = 0;
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uint32_t m_index_buffer_size = 0;
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uint64_t m_index_base_addr = 0;
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uint64_t m_draw_indirect_args_base_addr = 0;
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uint64_t m_dispatch_indirect_args_base_addr = 0;
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// Persistent draw state. Indirect draws leave the address of their last instance count,
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// read only when a later draw inherits it.
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uint32_t m_num_instances = 1;
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uint64_t m_num_instances_addr = 0;
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uint32_t m_de_count = 0;
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uint32_t m_ce_count = 0;
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bool m_ce_complete = false;
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uint32_t m_const_ram[0x3000] = {0};
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FlipInfo m_flip;
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const int m_interrupt_event_id;
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uint64_t m_submit_id = 0;
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uint64_t m_synthetic_occlusion_counter = 0;
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@@ -199,8 +199,6 @@ constexpr auto MakeOpcodeDispatchTable() {
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g_cp_op_func[Pm4::IT_INDIRECT_BUFFER] = CpOpIndirectBuffer;
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g_cp_op_func[Pm4::IT_COPY_DATA] = CpOpCopyData;
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g_cp_op_func[Pm4::IT_EVENT_WRITE] = CpOpEventWrite;
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g_cp_op_func[Pm4::IT_EVENT_WRITE_EOP] = CpOpEventWriteEop;
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g_cp_op_func[Pm4::IT_EVENT_WRITE_EOS] = CpOpEventWriteEos;
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g_cp_op_func[Pm4::IT_DMA_DATA] = CpOpDmaData;
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g_cp_op_func[Pm4::IT_ACQUIRE_MEM] = CpOpAcquireMem;
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g_cp_op_func[Pm4::IT_REWIND] = CpOpRewind;
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@@ -211,12 +209,6 @@ constexpr auto MakeOpcodeDispatchTable() {
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g_cp_op_func[Pm4::IT_SET_CONTEXT_REG_INDIRECT] = CpOpIndirectCxRegs;
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g_cp_op_func[Pm4::IT_SET_SH_REG_INDIRECT] = CpOpIndirectShRegs;
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g_cp_op_func[Pm4::IT_SET_UCONFIG_REG_INDIRECT] = CpOpIndirectUcRegs;
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g_cp_op_func[Pm4::IT_WRITE_CONST_RAM] = CpOpWriteConstRam;
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g_cp_op_func[Pm4::IT_DUMP_CONST_RAM] = CpOpDumpConstRam;
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g_cp_op_func[Pm4::IT_INCREMENT_CE_COUNTER] = CpOpIncrementCeCounter;
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g_cp_op_func[Pm4::IT_INCREMENT_DE_COUNTER] = CpOpIncrementDeCounter;
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g_cp_op_func[Pm4::IT_WAIT_ON_CE_COUNTER] = CpOpWaitOnCeCounter;
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g_cp_op_func[Pm4::IT_WAIT_ON_DE_COUNTER_DIFF] = CpOpWaitOnDeCounterDiff;
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g_cp_op_func[Pm4::IT_GET_LOD_STATS] = CpOpGetLodStats;
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g_cp_op_func[Pm4::IT_WAIT_REG_MEM_64] = CpOpWaitRegMem64;
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@@ -133,8 +133,6 @@ uint32_t CpOpWriteData(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, u
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uint32_t CpOpIndirectBuffer(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpCopyData(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpEventWrite(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpEventWriteEop(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpEventWriteEos(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpDmaData(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpAcquireMem(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpSetContextReg(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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@@ -143,12 +141,6 @@ uint32_t CpOpSetUconfigReg(CommandProcessor&, uint32_t, const uint32_t*, uint32_
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uint32_t CpOpIndirectCxRegs(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpIndirectShRegs(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpIndirectUcRegs(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpWriteConstRam(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpDumpConstRam(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpIncrementCeCounter(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpIncrementDeCounter(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpWaitOnCeCounter(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpWaitOnDeCounterDiff(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpGetLodStats(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpDispatchReset(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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uint32_t CpOpWaitRegMem32(CommandProcessor&, uint32_t, const uint32_t*, uint32_t, uint32_t);
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@@ -1068,9 +1068,8 @@ KYTY_HW_SH_PARSER(HwShSetCsUserSgpr) {
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auto write_num = UserSgprWriteNum(slot, reg_num, 16u, "cs");
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for (uint32_t i = 0; i < write_num; i++) {
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cp.GetShCtx().SetCsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
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cp.GetShCtx().SetCsUserSgpr(slot + i, buffer[i]);
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}
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cp.SetUserDataMarker(HW::UserSgprType::Unknown);
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return reg_num;
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}
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@@ -1085,9 +1084,8 @@ KYTY_HW_SH_PARSER(HwShSetPsUserSgpr) {
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auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "ps");
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for (uint32_t i = 0; i < write_num; i++) {
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cp.GetShCtx().SetPsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
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cp.GetShCtx().SetPsUserSgpr(slot + i, buffer[i]);
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}
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cp.SetUserDataMarker(HW::UserSgprType::Unknown);
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return reg_num;
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}
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@@ -1102,9 +1100,8 @@ KYTY_HW_SH_PARSER(HwShSetGsUserSgpr) {
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auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "gs");
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for (uint32_t i = 0; i < write_num; i++) {
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cp.GetShCtx().SetGsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
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cp.GetShCtx().SetGsUserSgpr(slot + i, buffer[i]);
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}
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cp.SetUserDataMarker(HW::UserSgprType::Unknown);
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return reg_num;
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}
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@@ -1119,9 +1116,8 @@ KYTY_HW_SH_PARSER(HwShSetHsUserSgpr) {
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auto write_num = UserSgprWriteNum(slot, reg_num, 32u, "hs");
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for (uint32_t i = 0; i < write_num; i++) {
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cp.GetShCtx().SetHsUserSgpr(slot + i, buffer[i], cp.GetUserDataMarker());
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cp.GetShCtx().SetHsUserSgpr(slot + i, buffer[i]);
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}
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cp.SetUserDataMarker(HW::UserSgprType::Unknown);
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return reg_num;
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}
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@@ -1700,24 +1696,6 @@ KYTY_CP_OP_PARSER(CpOpContextState) {
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return packet_size_dw - 1u;
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}
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KYTY_CP_OP_PARSER(CpOpDumpConstRam) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0038300);
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auto offset = buffer[0];
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auto dw_num = buffer[1];
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auto* dst = reinterpret_cast<uint32_t*>(buffer[2] | (static_cast<uint64_t>(buffer[3]) << 32u));
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EXIT_NOT_IMPLEMENTED(dw_num >= 0x3000);
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EXIT_NOT_IMPLEMENTED(offset > 0xbffc);
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EXIT_NOT_IMPLEMENTED((offset & 0x3u) != 0);
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cp.DumpConstRam(dst, offset, dw_num);
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return 4;
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}
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KYTY_CP_OP_PARSER(CpOpEventWrite) {
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KYTY_PROFILER_FUNCTION();
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@@ -1738,90 +1716,16 @@ KYTY_CP_OP_PARSER(CpOpEventWrite) {
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return packet_size_dw - 1u;
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}
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KYTY_CP_OP_PARSER(CpOpEventWriteEop) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0044700);
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uint32_t cache_policy = (buffer[0] >> 25u) & 0x3u;
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uint32_t event_write_dest = ((buffer[0] >> 23u) & 0x10u) | ((buffer[2] >> 16u) & 0x01u);
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uint32_t eop_event_type = (buffer[0]) & 0x3fu;
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uint32_t cache_action = (buffer[0] >> 12u) & 0x3fu;
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uint32_t event_index = (buffer[0] >> 8u) & 0x7u;
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uint32_t event_write_source = ((buffer[2] >> 29u) & 0x7u);
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uint32_t interrupt_selector = (buffer[2] >> 24u) & 0x7u;
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auto* dst_gpu_addr =
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reinterpret_cast<void*>(buffer[1] | (static_cast<uint64_t>(buffer[2] & 0xffffu) << 32u));
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uint64_t value = (buffer[3] | (static_cast<uint64_t>(buffer[4]) << 32u));
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cp.WriteAtEndOfPipe64(cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
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event_write_source, dst_gpu_addr, value, interrupt_selector);
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return 5;
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}
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KYTY_CP_OP_PARSER(CpOpEventWriteEos) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0034802);
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uint32_t cache_policy = (buffer[0] >> 25u) & 0x3u;
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uint32_t event_write_dest = 0;
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uint32_t eop_event_type = (buffer[0]) & 0x3fu;
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uint32_t cache_action = (buffer[0] >> 12u) & 0x3fu;
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uint32_t event_index = (buffer[0] >> 8u) & 0x7u;
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uint32_t event_write_source = ((buffer[2] >> 29u) & 0x7u);
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uint32_t interrupt_selector = (buffer[2] >> 24u) & 0x7u;
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auto* dst_gpu_addr =
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reinterpret_cast<void*>(buffer[1] | (static_cast<uint64_t>(buffer[2] & 0xffffu) << 32u));
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uint32_t value = buffer[3];
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cp.WriteAtEndOfPipe32(cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
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event_write_source, dst_gpu_addr, value, interrupt_selector);
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return 4;
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}
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KYTY_CP_OP_PARSER(CpOpFlip) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xc004105c);
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CommandProcessor::FlipInfo f;
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f.handle = static_cast<int>(buffer[0]);
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f.index = static_cast<int>(buffer[1]);
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f.flip_mode = static_cast<int>(buffer[2]);
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f.flip_arg = static_cast<int64_t>(buffer[3] | (static_cast<uint64_t>(buffer[4]) << 32u));
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cp.SetFlip(f);
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cp.Flip();
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cp.Flip(static_cast<int>(buffer[0]), static_cast<int>(buffer[1]), static_cast<int>(buffer[2]),
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static_cast<int64_t>(buffer[3] | (static_cast<uint64_t>(buffer[4]) << 32u)));
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return 5;
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}
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KYTY_CP_OP_PARSER(CpOpIncrementCeCounter) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0008400);
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EXIT_NOT_IMPLEMENTED(buffer[0] != 1);
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cp.IncrementCe();
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return 1;
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}
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KYTY_CP_OP_PARSER(CpOpIncrementDeCounter) {
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KYTY_PROFILER_FUNCTION();
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EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0008500);
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EXIT_NOT_IMPLEMENTED(buffer[0] != 0);
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cp.IncrementDe();
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return 1;
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}
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KYTY_CP_OP_PARSER(CpOpIndexType) {
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KYTY_PROFILER_FUNCTION();
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@@ -2103,50 +2007,12 @@ KYTY_CP_OP_PARSER(CpOpIndirectUcRegs) {
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return KYTY_PM4_LEN(cmd_id) - 1u;
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}
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KYTY_CP_OP_PARSER(CpOpMarker) {
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KYTY_PROFILER_FUNCTION();
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|
||||
uint32_t len_dw = ((cmd_id >> 16u) & 0x3fffu);
|
||||
|
||||
switch (buffer[0]) {
|
||||
case 0x68750004: cp.SetUserDataMarker(HW::UserSgprType::Vsharp); break;
|
||||
case 0x6875000d: cp.SetUserDataMarker(HW::UserSgprType::Region); break;
|
||||
case 0x68750777: {
|
||||
cp.Flip();
|
||||
break;
|
||||
}
|
||||
case 0x68750778: {
|
||||
auto* addr =
|
||||
reinterpret_cast<void*>(buffer[1] | (static_cast<uint64_t>(buffer[2]) << 32u));
|
||||
uint32_t value = buffer[3];
|
||||
cp.Flip(addr, value);
|
||||
break;
|
||||
}
|
||||
case 0x68750781: {
|
||||
auto* addr =
|
||||
reinterpret_cast<void*>(buffer[1] | (static_cast<uint64_t>(buffer[2]) << 32u));
|
||||
uint32_t value = buffer[3];
|
||||
uint32_t eop_event_type = buffer[4];
|
||||
uint32_t cache_action = buffer[5];
|
||||
cp.FlipWithInterrupt(eop_event_type, cache_action, addr, value);
|
||||
break;
|
||||
}
|
||||
// NOP payloads are caller-owned data; only complete known marker tags execute.
|
||||
default: break;
|
||||
}
|
||||
|
||||
return len_dw + 1;
|
||||
}
|
||||
|
||||
KYTY_CP_OP_PARSER(CpOpNop) {
|
||||
KYTY_PROFILER_FUNCTION();
|
||||
|
||||
auto r = KYTY_PM4_R(cmd_id);
|
||||
|
||||
if (r == Pm4::R_ZERO) {
|
||||
if ((buffer[0] & 0xffff0000u) == 0x68750000u) {
|
||||
return CpOpMarker(cp, cmd_id, buffer, dw, num_dw);
|
||||
}
|
||||
return KYTY_PM4_LEN(cmd_id) - 1;
|
||||
}
|
||||
|
||||
@@ -2204,12 +2070,10 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd_id != 0xc0061060);
|
||||
|
||||
uint32_t cache_policy = (buffer[0] >> 25u) & 0x3u;
|
||||
uint32_t eop_event_type = buffer[0] & 0x3fu;
|
||||
uint32_t event_index = (buffer[0] >> 8u) & 0x7u;
|
||||
uint32_t gcr_cntl = (buffer[0] >> 12u) & 0xfffu;
|
||||
uint32_t release_dst = (buffer[1] >> 16u) & 0x3u;
|
||||
uint32_t event_write_dest = 0;
|
||||
uint32_t data_sel = (buffer[1] >> 29u) & 0x7u;
|
||||
uint32_t interrupt_selector = (buffer[1] >> 24u) & 0x7u;
|
||||
auto* dst_gpu_addr =
|
||||
@@ -2250,16 +2114,15 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
|
||||
}
|
||||
|
||||
auto cache_action = ReleaseMemCacheActionFromGcr(gcr_cntl);
|
||||
cache_policy = 0;
|
||||
|
||||
if (data_sel == 1) {
|
||||
eop_event_type = 0x2f;
|
||||
event_index = 6;
|
||||
auto event_source = 2u;
|
||||
|
||||
cp.WriteAtEndOfPipe32(cache_policy, event_write_dest, eop_event_type, cache_action,
|
||||
event_index, event_source, dst_gpu_addr, static_cast<uint32_t>(value),
|
||||
interrupt_selector, interrupt_context_id);
|
||||
cp.WriteAtEndOfPipe32(eop_event_type, cache_action, event_index, event_source, dst_gpu_addr,
|
||||
static_cast<uint32_t>(value), interrupt_selector,
|
||||
interrupt_context_id);
|
||||
if (interrupt_selector == 0x01 || interrupt_selector == 0x02) {
|
||||
cp.BufferFlush();
|
||||
}
|
||||
@@ -2276,9 +2139,9 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
|
||||
event_index = 6;
|
||||
auto event_source = 1u;
|
||||
|
||||
cp.WriteAtEndOfPipe32(cache_policy, event_write_dest, eop_event_type, cache_action,
|
||||
event_index, event_source, dst_gpu_addr, static_cast<uint32_t>(value),
|
||||
interrupt_selector, interrupt_context_id);
|
||||
cp.WriteAtEndOfPipe32(eop_event_type, cache_action, event_index, event_source, dst_gpu_addr,
|
||||
static_cast<uint32_t>(value), interrupt_selector,
|
||||
interrupt_context_id);
|
||||
if (interrupt_selector == 0x01) {
|
||||
cp.BufferFlush();
|
||||
}
|
||||
@@ -2302,8 +2165,8 @@ KYTY_CP_OP_PARSER(CpOpReleaseMem) {
|
||||
data_sel = 4;
|
||||
}
|
||||
|
||||
cp.WriteAtEndOfPipe64(cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
|
||||
data_sel, dst_gpu_addr, value, interrupt_selector, interrupt_context_id);
|
||||
cp.WriteAtEndOfPipe64(eop_event_type, cache_action, event_index, data_sel, dst_gpu_addr, value,
|
||||
interrupt_selector, interrupt_context_id);
|
||||
|
||||
return 7;
|
||||
}
|
||||
@@ -2524,42 +2387,6 @@ KYTY_CP_OP_PARSER(CpOpWaitRegMem64) {
|
||||
return CpOpWaitRegMemSized<uint64_t>(cp, cmd_id, buffer);
|
||||
}
|
||||
|
||||
KYTY_CP_OP_PARSER(CpOpWaitOnCeCounter) {
|
||||
KYTY_PROFILER_FUNCTION();
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0008600);
|
||||
EXIT_NOT_IMPLEMENTED(buffer[0] != 1);
|
||||
|
||||
cp.WaitCe();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
KYTY_CP_OP_PARSER(CpOpWaitOnDeCounterDiff) {
|
||||
KYTY_PROFILER_FUNCTION();
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cmd_id != 0xC0008800);
|
||||
|
||||
cp.WaitDeDiff(buffer[0]);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
KYTY_CP_OP_PARSER(CpOpWriteConstRam) {
|
||||
KYTY_PROFILER_FUNCTION();
|
||||
|
||||
auto dw_num = (cmd_id >> 16u) & 0x3fffu;
|
||||
auto offset = buffer[0];
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(dw_num >= 0x3000);
|
||||
EXIT_NOT_IMPLEMENTED(offset > 0xbffc);
|
||||
EXIT_NOT_IMPLEMENTED((offset & 0x3u) != 0);
|
||||
|
||||
cp.WriteConstRam(offset, buffer + 1, dw_num);
|
||||
|
||||
return 1 + dw_num;
|
||||
}
|
||||
|
||||
KYTY_CP_OP_PARSER(CpOpWriteData) {
|
||||
KYTY_PROFILER_FUNCTION();
|
||||
|
||||
@@ -3519,9 +3346,7 @@ void GraphicsInitJmpTablesShIndirect() {
|
||||
|
||||
for (uint32_t slot = 0; slot < 16; slot++) {
|
||||
g_hw_sh_indirect_func[Pm4::COMPUTE_USER_DATA_0 + slot] = [](KYTY_HW_SH_INDIRECT_ARGS) {
|
||||
auto sgpr = cmd_offset - Pm4::COMPUTE_USER_DATA_0;
|
||||
cp.GetShCtx().SetCsUserSgpr(sgpr, value, cp.GetUserDataMarker());
|
||||
cp.SetUserDataMarker(HW::UserSgprType::Unknown);
|
||||
cp.GetShCtx().SetCsUserSgpr(cmd_offset - Pm4::COMPUTE_USER_DATA_0, value);
|
||||
};
|
||||
}
|
||||
for (uint32_t slot = 0; slot < 4; slot++) {
|
||||
@@ -3532,21 +3357,15 @@ void GraphicsInitJmpTablesShIndirect() {
|
||||
for (uint32_t slot = 0; slot < 32; slot++) {
|
||||
g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_PS_0 + slot] =
|
||||
[](KYTY_HW_SH_INDIRECT_ARGS) {
|
||||
auto sgpr = cmd_offset - Pm4::SPI_SHADER_USER_DATA_PS_0;
|
||||
cp.GetShCtx().SetPsUserSgpr(sgpr, value, cp.GetUserDataMarker());
|
||||
cp.SetUserDataMarker(HW::UserSgprType::Unknown);
|
||||
cp.GetShCtx().SetPsUserSgpr(cmd_offset - Pm4::SPI_SHADER_USER_DATA_PS_0, value);
|
||||
};
|
||||
g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_GS_0 + slot] =
|
||||
[](KYTY_HW_SH_INDIRECT_ARGS) {
|
||||
auto sgpr = cmd_offset - Pm4::SPI_SHADER_USER_DATA_GS_0;
|
||||
cp.GetShCtx().SetGsUserSgpr(sgpr, value, cp.GetUserDataMarker());
|
||||
cp.SetUserDataMarker(HW::UserSgprType::Unknown);
|
||||
cp.GetShCtx().SetGsUserSgpr(cmd_offset - Pm4::SPI_SHADER_USER_DATA_GS_0, value);
|
||||
};
|
||||
g_hw_sh_indirect_func[Pm4::SPI_SHADER_USER_DATA_HS_0 + slot] =
|
||||
[](KYTY_HW_SH_INDIRECT_ARGS) {
|
||||
auto sgpr = cmd_offset - Pm4::SPI_SHADER_USER_DATA_HS_0;
|
||||
cp.GetShCtx().SetHsUserSgpr(sgpr, value, cp.GetUserDataMarker());
|
||||
cp.SetUserDataMarker(HW::UserSgprType::Unknown);
|
||||
cp.GetShCtx().SetHsUserSgpr(cmd_offset - Pm4::SPI_SHADER_USER_DATA_HS_0, value);
|
||||
};
|
||||
}
|
||||
for (uint32_t slot = 0; slot < 4; slot++) {
|
||||
|
||||
@@ -127,16 +127,14 @@ void GuestGpu::SendCommandSync(Common::UniqueFunction<void>&& command) {
|
||||
done.acquire();
|
||||
}
|
||||
|
||||
void GuestGpu::Submit(std::span<const uint32_t> draw_commands,
|
||||
std::span<const uint32_t> constant_commands) {
|
||||
if (draw_commands.empty()) {
|
||||
void GuestGpu::Submit(std::span<const uint32_t> commands) {
|
||||
if (commands.empty()) {
|
||||
return;
|
||||
}
|
||||
Submission submission;
|
||||
submission.type = SubmissionType::Graphics;
|
||||
submission.queue_id = 0;
|
||||
submission.commands = draw_commands;
|
||||
submission.constant_commands = constant_commands;
|
||||
submission.type = SubmissionType::Graphics;
|
||||
submission.queue_id = 0;
|
||||
submission.commands = commands;
|
||||
Enqueue(std::move(submission));
|
||||
}
|
||||
|
||||
@@ -200,11 +198,8 @@ void CommandProcessor::Reset() {
|
||||
m_num_instances = 1;
|
||||
m_num_instances_addr = 0;
|
||||
m_predicate_skip = false;
|
||||
m_user_data_marker = HW::UserSgprType::Unknown;
|
||||
m_draw_indirect_args_base_addr = 0;
|
||||
m_dispatch_indirect_args_base_addr = 0;
|
||||
|
||||
std::memset(m_const_ram, 0, sizeof(m_const_ram));
|
||||
}
|
||||
|
||||
void CommandProcessor::ApplyContextStateOperation(ContextStateOperation operation) {
|
||||
@@ -246,47 +241,12 @@ void CommandProcessor::BufferWait() {
|
||||
GetScheduler().Finish();
|
||||
}
|
||||
|
||||
void CommandProcessor::ResetDeCe() {
|
||||
m_de_count = 0;
|
||||
m_ce_count = 0;
|
||||
m_ce_complete = false;
|
||||
}
|
||||
|
||||
void CommandProcessor::WaitCe() {
|
||||
if (m_ce_count <= m_de_count && !m_ce_complete) {
|
||||
SuspendPm4();
|
||||
}
|
||||
}
|
||||
|
||||
void CommandProcessor::WaitDeDiff(uint32_t diff) {
|
||||
EXIT_IF(m_de_count > m_ce_count);
|
||||
if (m_ce_count - m_de_count >= diff) {
|
||||
SuspendPm4();
|
||||
}
|
||||
}
|
||||
|
||||
void CommandProcessor::WaitForRewind(bool valid) {
|
||||
if (!valid) {
|
||||
SuspendPm4();
|
||||
}
|
||||
}
|
||||
|
||||
void CommandProcessor::IncrementDe() {
|
||||
m_de_count++;
|
||||
}
|
||||
|
||||
void CommandProcessor::IncrementCe() {
|
||||
m_ce_count++;
|
||||
}
|
||||
|
||||
void CommandProcessor::WriteConstRam(uint32_t offset, const uint32_t* src, uint32_t dw_num) {
|
||||
memcpy(m_const_ram + offset / 4, src, static_cast<size_t>(dw_num) * 4);
|
||||
}
|
||||
|
||||
void CommandProcessor::DumpConstRam(uint32_t* dst, uint32_t offset, uint32_t dw_num) {
|
||||
memcpy(dst, m_const_ram + offset / 4, static_cast<size_t>(dw_num) * 4);
|
||||
}
|
||||
|
||||
bool TestWaitRegMemValue(uint64_t value, uint64_t ref, uint64_t mask, uint32_t func) {
|
||||
switch (func) {
|
||||
case 0: return true;
|
||||
@@ -541,64 +501,34 @@ bool GuestGpu::Process(Submission& submission) {
|
||||
if (first_slice) {
|
||||
submission.started = true;
|
||||
cp.SetSubmitId(++m_submit_id);
|
||||
cp.ResetDeCe();
|
||||
cp.SetFlip({});
|
||||
}
|
||||
|
||||
cp.BufferInit();
|
||||
bool complete = true;
|
||||
|
||||
switch (submission.type) {
|
||||
case SubmissionType::Graphics: {
|
||||
bool progressed = false;
|
||||
submission.constant_complete |= submission.constant_commands.empty();
|
||||
for (;;) {
|
||||
bool round_progress = false;
|
||||
if (!submission.constant_complete) {
|
||||
submission.constant_complete =
|
||||
cp.Process(submission.constant_execution, submission.constant_commands) ==
|
||||
Pm4ProcessResult::Complete;
|
||||
round_progress |= submission.constant_execution.MadeProgress();
|
||||
}
|
||||
cp.SetCeComplete(submission.constant_complete);
|
||||
if (!submission.command_complete) {
|
||||
submission.command_complete =
|
||||
cp.Process(submission.command_execution, submission.commands) ==
|
||||
Pm4ProcessResult::Complete;
|
||||
round_progress |= submission.command_execution.MadeProgress();
|
||||
}
|
||||
progressed |= round_progress;
|
||||
complete = submission.command_complete && submission.constant_complete;
|
||||
if (complete || !round_progress) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (progressed) {
|
||||
cp.BufferFlush();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case SubmissionType::Compute: {
|
||||
const auto num_dw = static_cast<uint32_t>(submission.commands.size());
|
||||
const auto* buffer = submission.commands.data();
|
||||
static uint32_t compute_batch_log_count = 0;
|
||||
if (first_slice && num_dw <= 128 && compute_batch_log_count++ < 32) {
|
||||
LOGF("compute direct batch: data=0x%016" PRIx64 ", num_dw=%" PRIu32 "\n",
|
||||
reinterpret_cast<uint64_t>(buffer), num_dw);
|
||||
for (uint32_t i = 0; i < std::min<uint32_t>(num_dw, 16); i++) {
|
||||
LOGF("\t compute[%02" PRIu32 "] = 0x%08" PRIx32 "\n", i, buffer[i]);
|
||||
}
|
||||
}
|
||||
case SubmissionType::Compute:
|
||||
if (first_slice) {
|
||||
const auto num_dw = static_cast<uint32_t>(submission.commands.size());
|
||||
const auto* buffer = submission.commands.data();
|
||||
static uint32_t compute_batch_log_count = 0;
|
||||
if (num_dw <= 128 && compute_batch_log_count++ < 32) {
|
||||
LOGF("compute direct batch: data=0x%016" PRIx64 ", num_dw=%" PRIu32 "\n",
|
||||
reinterpret_cast<uint64_t>(buffer), num_dw);
|
||||
for (uint32_t i = 0; i < std::min<uint32_t>(num_dw, 16); i++) {
|
||||
LOGF("\t compute[%02" PRIu32 "] = 0x%08" PRIx32 "\n", i, buffer[i]);
|
||||
}
|
||||
}
|
||||
GraphicsDbgDumpDcb("cc", num_dw, buffer);
|
||||
}
|
||||
complete = cp.Process(submission.command_execution, submission.commands) ==
|
||||
Pm4ProcessResult::Complete;
|
||||
if (submission.command_execution.MadeProgress()) {
|
||||
[[fallthrough]];
|
||||
case SubmissionType::Graphics:
|
||||
complete =
|
||||
cp.Process(submission.execution, submission.commands) == Pm4ProcessResult::Complete;
|
||||
if (submission.execution.MadeProgress()) {
|
||||
cp.BufferFlush();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case SubmissionType::FlipPreparation:
|
||||
cp.PrepareCpuFlip(submission.flip_request_id);
|
||||
break;
|
||||
@@ -1019,8 +949,7 @@ void CommandProcessor::WaitFlipDone(uint32_t video_out_handle, uint32_t display_
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_write_dest,
|
||||
uint32_t eop_event_type, uint32_t cache_action,
|
||||
void CommandProcessor::WriteAtEndOfPipe(uint32_t eop_event_type, uint32_t cache_action,
|
||||
uint32_t event_index, uint32_t event_write_source,
|
||||
void* dst_gpu_addr, T value, uint32_t interrupt_selector,
|
||||
uint32_t interrupt_context_id) {
|
||||
@@ -1033,8 +962,6 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
const auto log_width = static_cast<int>(sizeof(T) * 2u);
|
||||
|
||||
LOGF("CommandProcessor::WriteAtEndOfPipe%u()\n"
|
||||
"\t cache_policy = 0x%08" PRIx32 "\n"
|
||||
"\t event_write_dest = 0x%08" PRIx32 "\n"
|
||||
"\t eop_event_type = 0x%08" PRIx32 "\n"
|
||||
"\t cache_action = 0x%08" PRIx32 "\n"
|
||||
"\t event_index = 0x%08" PRIx32 "\n"
|
||||
@@ -1043,13 +970,11 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
"\t interrupt_context = 0x%08" PRIx32 "\n"
|
||||
"\t dst_gpu_addr = 0x%016" PRIx64 "\n"
|
||||
"\t value = 0x%0*" PRIx64 "\n",
|
||||
bits, cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
|
||||
event_write_source, interrupt_selector, interrupt_context_id,
|
||||
reinterpret_cast<uint64_t>(dst_gpu_addr), log_width, static_cast<uint64_t>(value));
|
||||
bits, eop_event_type, cache_action, event_index, event_write_source,
|
||||
interrupt_selector, interrupt_context_id, reinterpret_cast<uint64_t>(dst_gpu_addr),
|
||||
log_width, static_cast<uint64_t>(value));
|
||||
}
|
||||
|
||||
EXIT_NOT_IMPLEMENTED(cache_policy != 0x00000000);
|
||||
EXIT_NOT_IMPLEMENTED(event_write_dest != 0x00000000);
|
||||
// Dumped occlusion counters are written before any end-of-pipe signal reaches the guest.
|
||||
m_renderer.GetOcclusionQueries().Publish();
|
||||
|
||||
@@ -1093,9 +1018,6 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
}
|
||||
return;
|
||||
}
|
||||
} else if (eop_event_type == 0x04 && cache_action == 0x00 && event_index == 0x05) {
|
||||
write32();
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 0x02:
|
||||
@@ -1156,9 +1078,7 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
case 0x04:
|
||||
case 0x14:
|
||||
case 0x28:
|
||||
if (((eop_event_type == 0x04 || eop_event_type == 0x28) &&
|
||||
event_index == 0x05) ||
|
||||
(event_index == 0x00)) {
|
||||
if (event_index == 0x00) {
|
||||
write64();
|
||||
return;
|
||||
}
|
||||
@@ -1179,12 +1099,6 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
default: break;
|
||||
}
|
||||
break;
|
||||
case 0x3b:
|
||||
if (eop_event_type == 0x04 && event_index == 0x05 && with_interrupt) {
|
||||
write64();
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
@@ -1195,26 +1109,22 @@ void CommandProcessor::WriteAtEndOfPipe(uint32_t cache_policy, uint32_t event_wr
|
||||
EXIT("unknown event type\n");
|
||||
}
|
||||
|
||||
void CommandProcessor::WriteAtEndOfPipe32(uint32_t cache_policy, uint32_t event_write_dest,
|
||||
uint32_t eop_event_type, uint32_t cache_action,
|
||||
void CommandProcessor::WriteAtEndOfPipe32(uint32_t eop_event_type, uint32_t cache_action,
|
||||
uint32_t event_index, uint32_t event_write_source,
|
||||
void* dst_gpu_addr, uint32_t value,
|
||||
uint32_t interrupt_selector,
|
||||
uint32_t interrupt_context_id) {
|
||||
WriteAtEndOfPipe(cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
|
||||
event_write_source, dst_gpu_addr, value, interrupt_selector,
|
||||
interrupt_context_id);
|
||||
WriteAtEndOfPipe(eop_event_type, cache_action, event_index, event_write_source, dst_gpu_addr,
|
||||
value, interrupt_selector, interrupt_context_id);
|
||||
}
|
||||
|
||||
void CommandProcessor::WriteAtEndOfPipe64(uint32_t cache_policy, uint32_t event_write_dest,
|
||||
uint32_t eop_event_type, uint32_t cache_action,
|
||||
void CommandProcessor::WriteAtEndOfPipe64(uint32_t eop_event_type, uint32_t cache_action,
|
||||
uint32_t event_index, uint32_t event_write_source,
|
||||
void* dst_gpu_addr, uint64_t value,
|
||||
uint32_t interrupt_selector,
|
||||
uint32_t interrupt_context_id) {
|
||||
WriteAtEndOfPipe(cache_policy, event_write_dest, eop_event_type, cache_action, event_index,
|
||||
event_write_source, dst_gpu_addr, value, interrupt_selector,
|
||||
interrupt_context_id);
|
||||
WriteAtEndOfPipe(eop_event_type, cache_action, event_index, event_write_source, dst_gpu_addr,
|
||||
value, interrupt_selector, interrupt_context_id);
|
||||
}
|
||||
|
||||
void CommandProcessor::TriggerEopEventAtEndOfPipe(uint32_t interrupt_context_id) {
|
||||
@@ -1304,65 +1214,20 @@ void CommandProcessor::TriggerEvent(uint32_t event_type, uint32_t event_index,
|
||||
}
|
||||
}
|
||||
|
||||
void CommandProcessor::Flip() {
|
||||
void CommandProcessor::Flip(int handle, int index, int flip_mode, int64_t flip_arg) {
|
||||
if (GraphicsRunDebugDumpEnabled()) {
|
||||
LOGF("CommandProcessor::Flip()\n");
|
||||
}
|
||||
m_renderer.GetOcclusionQueries().Publish();
|
||||
|
||||
auto& command = CurrentBuffer();
|
||||
auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
|
||||
m_flip.flip_arg);
|
||||
auto request = Sync::PrepareVideoOutFlip(command, handle, index, flip_mode, flip_arg);
|
||||
(void)command.Handle();
|
||||
GetScheduler().DeferPriorityOperation(
|
||||
[&renderer = m_renderer, request] { renderer.GetVideoOut().CompleteFlip(request); });
|
||||
GetScheduler().Flush();
|
||||
}
|
||||
|
||||
void CommandProcessor::Flip(void* dst_gpu_addr, uint32_t value) {
|
||||
if (GraphicsRunDebugDumpEnabled()) {
|
||||
LOGF("CommandProcessor::Flip()\n"
|
||||
"\t dst_gpu_addr = 0x%016" PRIx64 "\n"
|
||||
"\t value = 0x%08" PRIx32 "\n",
|
||||
reinterpret_cast<uint64_t>(dst_gpu_addr), value);
|
||||
}
|
||||
|
||||
EXIT_IF(dst_gpu_addr == nullptr);
|
||||
m_renderer.GetOcclusionQueries().Publish();
|
||||
std::memcpy(dst_gpu_addr, &value, sizeof(value));
|
||||
Flip();
|
||||
}
|
||||
|
||||
void CommandProcessor::FlipWithInterrupt(uint32_t eop_event_type, uint32_t cache_action,
|
||||
void* dst_gpu_addr, uint32_t value) {
|
||||
auto& command = CurrentBuffer();
|
||||
|
||||
if (GraphicsRunDebugDumpEnabled()) {
|
||||
LOGF("CommandProcessor::FlipWithInterrupt()\n"
|
||||
"\t eop_event_type = 0x%08" PRIx32 "\n"
|
||||
"\t cache_action = 0x%08" PRIx32 "\n"
|
||||
"\t dst_gpu_addr = 0x%016" PRIx64 "\n"
|
||||
"\t value = 0x%08" PRIx32 "\n",
|
||||
eop_event_type, cache_action, reinterpret_cast<uint64_t>(dst_gpu_addr), value);
|
||||
}
|
||||
|
||||
if (eop_event_type != 0x00000004 || cache_action != 0x00000038) {
|
||||
EXIT("unknown event type\n");
|
||||
}
|
||||
EXIT_IF(dst_gpu_addr == nullptr);
|
||||
m_renderer.GetOcclusionQueries().Publish();
|
||||
std::memcpy(dst_gpu_addr, &value, sizeof(value));
|
||||
auto request = Sync::PrepareVideoOutFlip(command, m_flip.handle, m_flip.index, m_flip.flip_mode,
|
||||
m_flip.flip_arg);
|
||||
(void)command.Handle();
|
||||
GetScheduler().DeferPriorityOperation(
|
||||
[&renderer = m_renderer, event_id = m_interrupt_event_id, request] {
|
||||
renderer.GetVideoOut().CompleteFlip(request);
|
||||
renderer.TriggerInterrupt(event_id, 0);
|
||||
});
|
||||
GetScheduler().Flush();
|
||||
}
|
||||
|
||||
void CommandProcessor::PrepareCpuFlip(uint64_t request_id) {
|
||||
auto& command = CurrentBuffer();
|
||||
if (g_current_processor != nullptr) {
|
||||
|
||||
@@ -35,8 +35,7 @@ public:
|
||||
void Wake();
|
||||
|
||||
// Submitted command memory is borrowed and must remain valid until GPU execution completes.
|
||||
void Submit(std::span<const uint32_t> draw_commands,
|
||||
std::span<const uint32_t> constant_commands);
|
||||
void Submit(std::span<const uint32_t> commands);
|
||||
void SubmitCompute(uint32_t queue, std::span<const uint32_t> commands);
|
||||
void SubmitFlipPreparation(uint64_t request_id);
|
||||
// Insert an ordered graphics drain; only a previous suspend point can block the caller.
|
||||
@@ -60,14 +59,10 @@ private:
|
||||
SubmissionType type = SubmissionType::Graphics;
|
||||
uint32_t queue_id = 0;
|
||||
std::span<const uint32_t> commands;
|
||||
std::span<const uint32_t> constant_commands;
|
||||
Pm4Execution command_execution;
|
||||
Pm4Execution constant_execution;
|
||||
bool started = false;
|
||||
bool command_complete = false;
|
||||
bool constant_complete = false;
|
||||
bool blocked = false;
|
||||
uint64_t flip_request_id = 0;
|
||||
Pm4Execution execution;
|
||||
bool started = false;
|
||||
bool blocked = false;
|
||||
uint64_t flip_request_id = 0;
|
||||
};
|
||||
|
||||
void Enqueue(Submission submission);
|
||||
|
||||
@@ -597,14 +597,10 @@ struct ShaderRegisters {
|
||||
}
|
||||
};
|
||||
|
||||
enum class UserSgprType { Unknown, Region, Vsharp };
|
||||
|
||||
struct UserSgprInfo {
|
||||
static constexpr int SGPRS_MAX = 32;
|
||||
|
||||
uint32_t value[SGPRS_MAX] = {0};
|
||||
UserSgprType type[SGPRS_MAX] = {};
|
||||
uint32_t count = 0;
|
||||
uint32_t value[SGPRS_MAX] = {0};
|
||||
};
|
||||
|
||||
struct VertexShaderInfo {
|
||||
@@ -1056,30 +1052,10 @@ public:
|
||||
void SetCsShader(const CsStageRegisters& cs_regs) { m_cs.cs_regs = cs_regs; }
|
||||
void SetCsWaveSize(uint8_t wave_size) { m_cs.cs_regs.wave_size = wave_size; }
|
||||
|
||||
void SetPsUserSgpr(uint32_t id, uint32_t value, UserSgprType type) {
|
||||
m_ps.ps_user_sgpr.value[id] = value;
|
||||
m_ps.ps_user_sgpr.type[id] = type;
|
||||
m_ps.ps_user_sgpr.count =
|
||||
((id + 1) > m_ps.ps_user_sgpr.count ? (id + 1) : m_ps.ps_user_sgpr.count);
|
||||
}
|
||||
void SetCsUserSgpr(uint32_t id, uint32_t value, UserSgprType type) {
|
||||
m_cs.cs_user_sgpr.value[id] = value;
|
||||
m_cs.cs_user_sgpr.type[id] = type;
|
||||
m_cs.cs_user_sgpr.count =
|
||||
((id + 1) > m_cs.cs_user_sgpr.count ? (id + 1) : m_cs.cs_user_sgpr.count);
|
||||
}
|
||||
void SetHsUserSgpr(uint32_t id, uint32_t value, UserSgprType type) {
|
||||
m_vs.hs_user_sgpr.value[id] = value;
|
||||
m_vs.hs_user_sgpr.type[id] = type;
|
||||
m_vs.hs_user_sgpr.count =
|
||||
((id + 1) > m_vs.hs_user_sgpr.count ? (id + 1) : m_vs.hs_user_sgpr.count);
|
||||
}
|
||||
void SetGsUserSgpr(uint32_t id, uint32_t value, UserSgprType type) {
|
||||
m_vs.gs_user_sgpr.value[id] = value;
|
||||
m_vs.gs_user_sgpr.type[id] = type;
|
||||
m_vs.gs_user_sgpr.count =
|
||||
((id + 1) > m_vs.gs_user_sgpr.count ? (id + 1) : m_vs.gs_user_sgpr.count);
|
||||
}
|
||||
void SetPsUserSgpr(uint32_t id, uint32_t value) { m_ps.ps_user_sgpr.value[id] = value; }
|
||||
void SetCsUserSgpr(uint32_t id, uint32_t value) { m_cs.cs_user_sgpr.value[id] = value; }
|
||||
void SetHsUserSgpr(uint32_t id, uint32_t value) { m_vs.hs_user_sgpr.value[id] = value; }
|
||||
void SetGsUserSgpr(uint32_t id, uint32_t value) { m_vs.gs_user_sgpr.value[id] = value; }
|
||||
|
||||
[[nodiscard]] const PixelShaderInfo& GetPs() const { return m_ps; }
|
||||
[[nodiscard]] const VertexShaderInfo& GetVs() const { return m_vs; }
|
||||
|
||||
@@ -54,7 +54,6 @@ constexpr auto MakeOpcodeNames() {
|
||||
names[IT_DRAW_INDIRECT_MULTI] = "IT_DRAW_INDIRECT_MULTI";
|
||||
names[IT_DRAW_INDEX_AUTO] = "IT_DRAW_INDEX_AUTO";
|
||||
names[IT_NUM_INSTANCES] = "IT_NUM_INSTANCES";
|
||||
names[IT_INDIRECT_BUFFER_CNST] = "IT_INDIRECT_BUFFER_CNST";
|
||||
names[IT_DRAW_INDEX_OFFSET_2] = "IT_DRAW_INDEX_OFFSET_2";
|
||||
names[IT_WRITE_DATA] = "IT_WRITE_DATA";
|
||||
names[IT_MEM_SEMAPHORE] = "IT_MEM_SEMAPHORE";
|
||||
@@ -66,8 +65,6 @@ constexpr auto MakeOpcodeNames() {
|
||||
names[IT_PFP_SYNC_ME] = "IT_PFP_SYNC_ME";
|
||||
names[IT_SURFACE_SYNC] = "IT_SURFACE_SYNC";
|
||||
names[IT_EVENT_WRITE] = "IT_EVENT_WRITE";
|
||||
names[IT_EVENT_WRITE_EOP] = "IT_EVENT_WRITE_EOP";
|
||||
names[IT_EVENT_WRITE_EOS] = "IT_EVENT_WRITE_EOS";
|
||||
names[IT_RELEASE_MEM] = "IT_RELEASE_MEM";
|
||||
names[IT_DMA_DATA] = "IT_DMA_DATA";
|
||||
names[IT_ACQUIRE_MEM] = "IT_ACQUIRE_MEM";
|
||||
@@ -80,12 +77,6 @@ constexpr auto MakeOpcodeNames() {
|
||||
names[IT_SET_QUEUE_REG] = "IT_SET_QUEUE_REG";
|
||||
names[IT_SET_UCONFIG_REG] = "IT_SET_UCONFIG_REG";
|
||||
names[IT_SET_UCONFIG_REG_INDEX] = "IT_SET_UCONFIG_REG_INDEX";
|
||||
names[IT_WRITE_CONST_RAM] = "IT_WRITE_CONST_RAM";
|
||||
names[IT_DUMP_CONST_RAM] = "IT_DUMP_CONST_RAM";
|
||||
names[IT_INCREMENT_CE_COUNTER] = "IT_INCREMENT_CE_COUNTER";
|
||||
names[IT_INCREMENT_DE_COUNTER] = "IT_INCREMENT_DE_COUNTER";
|
||||
names[IT_WAIT_ON_CE_COUNTER] = "IT_WAIT_ON_CE_COUNTER";
|
||||
names[IT_WAIT_ON_DE_COUNTER_DIFF] = "IT_WAIT_ON_DE_COUNTER_DIFF";
|
||||
names[IT_DISPATCH_DRAW_PREAMBLE] = "IT_DISPATCH_DRAW_PREAMBLE";
|
||||
names[IT_DISPATCH_DRAW] = "IT_DISPATCH_DRAW";
|
||||
names[IT_GET_LOD_STATS] = "IT_GET_LOD_STATS";
|
||||
|
||||
@@ -40,7 +40,6 @@ constexpr uint32_t IT_INDEX_TYPE = 0x2A;
|
||||
constexpr uint32_t IT_DRAW_INDIRECT_MULTI = 0x2C;
|
||||
constexpr uint32_t IT_DRAW_INDEX_AUTO = 0x2D;
|
||||
constexpr uint32_t IT_NUM_INSTANCES = 0x2F;
|
||||
constexpr uint32_t IT_INDIRECT_BUFFER_CNST = 0x33;
|
||||
constexpr uint32_t IT_DRAW_INDEX_OFFSET_2 = 0x35;
|
||||
constexpr uint32_t IT_WRITE_DATA = 0x37;
|
||||
constexpr uint32_t IT_MEM_SEMAPHORE = 0x39;
|
||||
@@ -53,8 +52,6 @@ constexpr uint32_t IT_CP_DMA = 0x41;
|
||||
constexpr uint32_t IT_PFP_SYNC_ME = 0x42;
|
||||
constexpr uint32_t IT_SURFACE_SYNC = 0x43;
|
||||
constexpr uint32_t IT_EVENT_WRITE = 0x46;
|
||||
constexpr uint32_t IT_EVENT_WRITE_EOP = 0x47;
|
||||
constexpr uint32_t IT_EVENT_WRITE_EOS = 0x48;
|
||||
constexpr uint32_t IT_RELEASE_MEM = 0x49;
|
||||
constexpr uint32_t IT_DMA_DATA = 0x50;
|
||||
constexpr uint32_t IT_ACQUIRE_MEM = 0x58;
|
||||
@@ -67,12 +64,6 @@ constexpr uint32_t IT_SET_SH_REG = 0x76;
|
||||
constexpr uint32_t IT_SET_QUEUE_REG = 0x78;
|
||||
constexpr uint32_t IT_SET_UCONFIG_REG = 0x79;
|
||||
constexpr uint32_t IT_SET_UCONFIG_REG_INDEX = 0x7A;
|
||||
constexpr uint32_t IT_WRITE_CONST_RAM = 0x81;
|
||||
constexpr uint32_t IT_DUMP_CONST_RAM = 0x83;
|
||||
constexpr uint32_t IT_INCREMENT_CE_COUNTER = 0x84;
|
||||
constexpr uint32_t IT_INCREMENT_DE_COUNTER = 0x85;
|
||||
constexpr uint32_t IT_WAIT_ON_CE_COUNTER = 0x86;
|
||||
constexpr uint32_t IT_WAIT_ON_DE_COUNTER_DIFF = 0x88;
|
||||
constexpr uint32_t IT_DISPATCH_DRAW = 0x8D;
|
||||
constexpr uint32_t IT_GET_LOD_STATS = 0x8E;
|
||||
constexpr uint32_t IT_WAIT_REG_MEM_64 = 0x93;
|
||||
|
||||
Reference in New Issue
Block a user