diff --git a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
index 33e632c2b..69bc0b25a 100644
--- a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
+++ b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp
@@ -1312,6 +1312,14 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_
 			    (value >> Pm4::COMPUTE_PGM_RSRC1_VGPRS_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_VGPRS_MASK;
 			cs_regs.sgprs =
 			    (value >> Pm4::COMPUTE_PGM_RSRC1_SGPRS_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_SGPRS_MASK;
+			cs_regs.float_mode    = (value >> Pm4::COMPUTE_PGM_RSRC1_FLOAT_MODE_SHIFT) &
+			                        Pm4::COMPUTE_PGM_RSRC1_FLOAT_MODE_MASK;
+			cs_regs.dx10_clamp    = ((value >> Pm4::COMPUTE_PGM_RSRC1_DX10_CLAMP_SHIFT) &
+			                         Pm4::COMPUTE_PGM_RSRC1_DX10_CLAMP_MASK) != 0u;
+			cs_regs.ieee_mode     = ((value >> Pm4::COMPUTE_PGM_RSRC1_IEEE_MODE_SHIFT) &
+			                         Pm4::COMPUTE_PGM_RSRC1_IEEE_MODE_MASK) != 0u;
+			cs_regs.fp16_overflow = ((value >> Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT) &
+			                         Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_MASK) != 0u;
 			cs_regs.bulky =
 			    (value >> Pm4::COMPUTE_PGM_RSRC1_BULKY_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_BULKY_MASK;
 			cs_regs.wave_size = (((value >> Pm4::COMPUTE_PGM_RSRC1_W32_EN_SHIFT) &
diff --git a/src/graphics/guest_gpu/hardwareContext.h b/src/graphics/guest_gpu/hardwareContext.h
index 073e411cd..c92fc3562 100644
--- a/src/graphics/guest_gpu/hardwareContext.h
+++ b/src/graphics/guest_gpu/hardwareContext.h
@@ -519,6 +519,10 @@ struct CsStageRegisters {
 	uint32_t num_thread_z   = 0;
 	uint8_t  vgprs          = 0;
 	uint8_t  sgprs          = 0;
+	uint8_t  float_mode     = 0;
+	bool     dx10_clamp     = false;
+	bool     ieee_mode      = false;
+	bool     fp16_overflow  = false;
 	uint8_t  bulky          = 0;
 	uint8_t  wave_size      = 64;
 	uint8_t  scratch_en     = 0;
diff --git a/src/graphics/guest_gpu/pm4.h b/src/graphics/guest_gpu/pm4.h
index c83807155..996e36569 100644
--- a/src/graphics/guest_gpu/pm4.h
+++ b/src/graphics/guest_gpu/pm4.h
@@ -932,15 +932,23 @@ constexpr uint32_t COMPUTE_TBA_HI                  = 0x20F;
 constexpr uint32_t COMPUTE_TMA_LO                  = 0x210;
 constexpr uint32_t COMPUTE_TMA_HI                  = 0x211;
 
-constexpr uint32_t COMPUTE_PGM_RSRC1              = 0x212;
-constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT  = 0;
-constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_MASK   = 0x3F;
-constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_SHIFT  = 6;
-constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_MASK   = 0xF;
-constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_SHIFT  = 24;
-constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_MASK   = 0x1;
-constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_SHIFT = 30;
-constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_MASK  = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1                  = 0x212;
+constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT      = 0;
+constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_MASK       = 0x3F;
+constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_SHIFT      = 6;
+constexpr uint32_t COMPUTE_PGM_RSRC1_SGPRS_MASK       = 0xF;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FLOAT_MODE_SHIFT = 12;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FLOAT_MODE_MASK  = 0xFF;
+constexpr uint32_t COMPUTE_PGM_RSRC1_DX10_CLAMP_SHIFT = 21;
+constexpr uint32_t COMPUTE_PGM_RSRC1_DX10_CLAMP_MASK  = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_IEEE_MODE_SHIFT  = 23;
+constexpr uint32_t COMPUTE_PGM_RSRC1_IEEE_MODE_MASK   = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_SHIFT      = 24;
+constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_MASK       = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT  = 26;
+constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_MASK   = 0x1;
+constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_SHIFT     = 30;
+constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_MASK      = 0x1;
 
 constexpr uint32_t COMPUTE_PGM_RSRC2                      = 0x213;
 constexpr uint32_t COMPUTE_PGM_RSRC2_SCRATCH_EN_SHIFT     = 0;