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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
shader: lower complete wave minima for sparse fragment subgroups
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nmzik
@@ -619,6 +619,124 @@ void TestReadLaneElimination() {
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"dynamic-lane read was rewritten unsafely");
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}
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void TestCompleteUMinReduction() {
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enum class Case {
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Masked, Subset, Literal, LiteralMasked, LiteralMove, Wave32,
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UnrelatedSeed, UnmaskedSymbolic, WrongNeutral, RowMask, BankMask,
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Shift, FetchInactive, BoundControl, Dpp8, MoveExec, UpdateExec,
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Previous, DppSource, CrossExec, CrossRow, CrossSelectorLow,
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CrossSelectorHigh, CrossFetch, CrossBound, CrossSource, FinalExec,
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Endpoint, EndpointSource, DifferentWitness, CrossBlock, WrongOperation
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};
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for (const auto test : {Case::Masked, Case::Subset, Case::Literal,
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Case::LiteralMasked, Case::LiteralMove, Case::Wave32, Case::UnrelatedSeed,
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Case::UnmaskedSymbolic, Case::WrongNeutral, Case::RowMask, Case::BankMask,
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Case::Shift, Case::FetchInactive, Case::BoundControl, Case::Dpp8,
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Case::MoveExec, Case::UpdateExec, Case::Previous, Case::DppSource,
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Case::CrossExec, Case::CrossRow, Case::CrossSelectorLow,
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Case::CrossSelectorHigh, Case::CrossFetch, Case::CrossBound,
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Case::CrossSource, Case::FinalExec, Case::Endpoint, Case::EndpointSource,
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Case::DifferentWitness, Case::CrossBlock, Case::WrongOperation}) {
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Fixture fixture(test == Case::CrossBlock ? 2 : 1);
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const auto source = fixture.Emit(ValueOpcode::LaneId);
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const auto mask = fixture.Emit(ValueOpcode::ULessThan32, {source, Value(19u)});
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const auto other_mask = fixture.Emit(ValueOpcode::IEqual32, {source, Value(7u)});
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const auto negated = fixture.Emit(ValueOpcode::LogicalNot, {mask});
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const bool literal = test == Case::Literal || test == Case::LiteralMasked;
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const auto enabled = literal ? Value(true) :
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fixture.Emit(ValueOpcode::LogicalOr, {negated, mask});
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auto seed_mask = test == Case::UnrelatedSeed ? other_mask : mask;
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if (test == Case::Subset)
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seed_mask = fixture.Emit(ValueOpcode::LogicalAnd, {other_mask, mask});
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const auto seed = test == Case::Literal || test == Case::UnmaskedSymbolic ? source :
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fixture.Emit(ValueOpcode::SelectU32,
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{seed_mask, source, Value(test == Case::WrongNeutral ? 0u : UINT32_MAX)});
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auto prefix = fixture.Emit(ValueOpcode::SelectU32, {enabled, seed, source});
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Value preserved;
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const auto operation = test == Case::WrongOperation ? ValueOpcode::BitwiseOr32 :
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ValueOpcode::UMin32;
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for (const uint32_t shift : {1u, 2u, 4u, 8u}) {
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DppMoveFlags flags{.control = 0x110u + shift};
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if (shift == 2) {
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if (test == Case::RowMask) flags.row_mask = 7;
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if (test == Case::BankMask) flags.bank_mask = 7;
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if (test == Case::Shift) flags.control = 0x113;
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if (test == Case::FetchInactive) flags.fetch_inactive = true;
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if (test == Case::BoundControl) flags.bound_control = true;
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if (test == Case::Dpp8) flags.dpp8 = true;
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}
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const auto move = fixture.Emit(ValueOpcode::DppMoveU32,
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{test == Case::DppSource ? source : prefix,
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test == Case::MoveExec ? mask : test == Case::LiteralMove ? Value(true) : enabled});
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move.Instruction()->SetFlags(flags);
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const auto combined = fixture.Emit(operation, {move, prefix});
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const auto update = fixture.Emit(ValueOpcode::DppUpdateU32,
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{combined, test == Case::Previous ? source : prefix,
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test == Case::UpdateExec ? mask : enabled});
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update.Instruction()->SetFlags(flags);
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prefix = update;
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if (shift == 2) preserved = fixture.Emit(ValueOpcode::ReferenceU32, {prefix});
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}
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auto cross_exec = test == Case::CrossExec ? mask : enabled;
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if (test == Case::DifferentWitness) {
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const auto other_not = fixture.Emit(ValueOpcode::LogicalNot, {other_mask});
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cross_exec = fixture.Emit(ValueOpcode::LogicalOr, {other_mask, other_not});
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}
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const auto cross = fixture.Emit(ValueOpcode::Permlane16U32,
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{test == Case::CrossSource ? source : prefix,
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Value(test == Case::CrossSelectorLow ? 0xfffffff0u : UINT32_MAX),
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Value(test == Case::CrossSelectorHigh ? 0xfffffff0u : UINT32_MAX), cross_exec});
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cross.Instruction()->SetFlags(PermlaneFlags{
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.x16 = test != Case::CrossRow, .fetch_inactive = test == Case::CrossFetch,
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.bound_control = test != Case::CrossBound});
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const auto cross_write = fixture.Emit(ValueOpcode::SelectU32, {enabled, cross, source});
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const auto combined = fixture.Emit(operation, {prefix, cross_write});
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const auto final = fixture.Emit(ValueOpcode::SelectU32,
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{test == Case::FinalExec ? mask : enabled, combined, prefix});
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const uint32_t result_block = test == Case::CrossBlock ? 1u : 0u;
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const auto low = fixture.Emit(ValueOpcode::ReadLane,
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{final, Value(test == Case::Endpoint ? 30u : 31u)}, 0, result_block);
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const auto high = fixture.Emit(ValueOpcode::ReadLane,
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{test == Case::EndpointSource ? prefix : final, Value(63u)}, 0, result_block);
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const auto result = fixture.Emit(operation, {high, low}, 0, result_block);
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const auto use = fixture.Emit(ValueOpcode::ReferenceU32, {result}, 0, result_block);
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using Terminator = Libs::Graphics::ShaderRecompiler::CFG::TerminatorKind;
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fixture.BlockAt(result_block).terminator.kind = Terminator::Return;
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if (result_block != 0) {
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fixture.BlockAt().AddBranch(&fixture.BlockAt(1));
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fixture.BlockAt().terminator.kind = Terminator::Branch;
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fixture.BlockAt().terminator.true_block = &fixture.BlockAt(1);
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}
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ValidateProgram(fixture.program, true);
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const auto stats = EliminateReadLane(fixture.program, test == Case::Wave32 ? 32u : 64u);
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const bool matches = test == Case::Masked || test == Case::Subset ||
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test == Case::Literal || test == Case::LiteralMasked || test == Case::LiteralMove;
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Check(stats.rewritten_reductions == (matches ? 1u : 0u) && stats.rewritten_reads == 0,
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("UMin reduction proof failed case " + std::to_string(static_cast<unsigned>(test))).c_str());
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if (matches) {
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const auto *reduction = use.Instruction()->Arg(0).ResolveInstruction();
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Check(reduction->GetOpcode() == ValueOpcode::SubgroupUMinU32 &&
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reduction->Arg(0).Resolve() == seed.Resolve(),
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"UMin reduction changed the neutral-masked input");
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RemoveIdentities(fixture.program.blocks);
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EliminateDeadCode(fixture.program.blocks);
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uint32_t updates = 0;
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for (const auto &inst : fixture.BlockAt()) {
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updates += inst.GetOpcode() == ValueOpcode::DppUpdateU32;
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Check(inst.GetOpcode() != ValueOpcode::ReadLane &&
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inst.GetOpcode() != ValueOpcode::Permlane16U32,
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"UMin reduction retained unused endpoint or cross-row operations");
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}
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Check(updates == 2 && preserved.Instruction()->Arg(0).Instruction()->HasUses(),
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"UMin reduction destroyed an independently consumed prefix or kept its dead suffix");
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ValidateProgram(fixture.program, true);
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} else {
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Check(use.Instruction()->Arg(0).Resolve() == result,
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"rejected UMin proof changed its original result");
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}
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}
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}
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void TestOptimizationPipeline() {
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Fixture fixture;
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const auto sum = fixture.Emit(ValueOpcode::IAdd32, {Value(40u), Value(2u)});
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@@ -756,6 +874,7 @@ int main() {
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TestSharedIntegerRuntimeDependencies();
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TestConstantBufferBounds();
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TestReadLaneElimination();
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TestCompleteUMinReduction();
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TestOptimizationPipeline();
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TestControlFlowValueSurvivesReadLaneFolding();
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TestDeadPhiCyclesAndPlanningRoots();
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@@ -39536,6 +39536,63 @@ TestCase ImageAtomicGlc0DoesNotReturnOldValue() {
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return test;
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}
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void AppendWave64Minimum(std::vector<u32> &code) {
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code.insert(code.end(), {EncodeSop1(0x04, 24, 126), // Save contributing lanes.
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EncodeSop1(0x28, 106, 126)});
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AppendVop3(&code, 0x101, 13, 193, Vgpr(13), 24); // Inactive lanes contribute UINT_MAX.
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for (u32 shift : {1u, 2u, 4u, 8u}) {
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code.push_back(EncodeVop2(0x13, 13, 250, 13));
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code.push_back(EncodeVop2Dpp(13, 0x110u + shift));
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}
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// Exact RDNA2 wave64 reduction from PS 964747887d898821, PCs 0x224..0x244.
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code.insert(code.end(), {0xd778100cu, 0x0305830du,
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EncodeVop2(0x13, 13, Vgpr(13), 12), EncodeSop1(0x04, 126, 106),
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0xd7600006u, 0x00013f0du, 0xd7600007u, 0x00017f0du,
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EncodeSop2(0x07, 8, 6, 7), EncodeVop1(0x01, 0, 8)});
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}
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GraphicsCase GraphicsSparseWaveMinimum() {
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GraphicsCase test;
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test.name = "GraphicsSparseWaveMinimum";
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auto &code = test.fragment_code;
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code = {EncodeVintrp(0x02, 13, 0, 0, 2)};
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AppendWave64Minimum(code);
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code.insert(code.end(), {EncodeExp0(0x00, 0xf), EncodeExp1(0, 0, 0, 0)});
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AppendEnd(&code);
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test.pixel_interpolator_settings = {0x00000400u};
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test.expected_pixel = {0x3e800000u, 0x3e800000u, 0x3e800000u, 0x3e800000u};
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test.opcodes = {ShaderOpcode::V_MIN_U32, ShaderOpcode::V_PERMLANEX16_B32,
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ShaderOpcode::V_READLANE_B32, ShaderOpcode::S_MIN_U32};
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return test;
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}
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TestCase ComputeWave64Minimum(bool masked) {
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TestCase test;
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test.name = masked ? "ComputeWave64MinimumMasked" : "ComputeWave64Minimum";
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auto &code = test.code;
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code = {EncodeVop2(0x1a, 20, InlineU32(2), 0)};
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AppendVMovU32(&code, 13, 100);
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code.push_back(EncodeVop2(0x26, 13, Vgpr(13), 0)); // 100 - lane: minimum is in the upper half.
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if (masked) {
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AppendSMovLiteral(&code, 126, 0xfffffffeu);
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AppendSMovLiteral(&code, 127, 0x7fffffffu);
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}
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AppendWave64Minimum(code);
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AppendBufferStoreDword(&code, 0, 20);
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AppendEnd(&code);
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test.initial.assign(64, 0xa5a5a5a5u);
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test.expected.assign(64, masked ? 38u : 37u);
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if (masked) test.expected.front() = test.expected.back() = 0xa5a5a5a5u;
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test.compute_info.threads_num[0] = 64;
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test.compute_info.threads_num[1] = test.compute_info.threads_num[2] = 1;
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test.compute_info.thread_ids_num = 1;
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test.compute_info.wave_size = 64;
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test.has_compute_info = true;
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test.opcodes = {ShaderOpcode::V_MIN_U32, ShaderOpcode::V_PERMLANEX16_B32,
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ShaderOpcode::V_READLANE_B32, ShaderOpcode::S_MIN_U32};
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return test;
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}
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GraphicsCase GraphicsInterpolationExport() {
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using O = ShaderOpcode;
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@@ -40193,6 +40250,8 @@ std::vector<TestCase> MakeCases() {
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AddCase(VectorDppRowXmask);
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cases.push_back(VectorDppRowShare(32));
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cases.push_back(VectorDppRowShare(64));
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cases.push_back(ComputeWave64Minimum(false));
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cases.push_back(ComputeWave64Minimum(true));
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AddCase(VectorDppBankMaskPreservesDestination);
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AddCase(VectorDppBoundsControlZeroPreservesDestination);
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AddCase(Vop3FmacF32NegatedSourceAccumulates);
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@@ -40586,6 +40645,7 @@ std::vector<TestCase> MakeCases() {
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std::vector<GraphicsCase> MakeGraphicsCases() {
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return {
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GraphicsSparseWaveMinimum(),
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GraphicsInterpolationExport(),
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GraphicsPositionWExport(),
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GraphicsPackedHalfCentroid(),
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@@ -45974,6 +46034,9 @@ int main(int argc, char **argv) {
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}
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if (argc == 2 && std::strcmp(argv[1], "--dpp-only") == 0) {
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VulkanHarness vulkan;
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RunGraphicsCase(&vulkan, GraphicsSparseWaveMinimum());
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RunCase(&vulkan, ComputeWave64Minimum(false));
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RunCase(&vulkan, ComputeWave64Minimum(true));
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RunCase(&vulkan, VectorDpp8Captured(false));
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for (const u32 wave_size : {32u, 64u})
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for (const bool fi : {false, true})
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