diff --git a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp index 69bc0b25a..2ad17e6f6 100644 --- a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp +++ b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp @@ -1320,26 +1320,28 @@ static void HwShSetCsRegister(CommandProcessor& cp, uint32_t cmd_offset, uint32_ Pm4::COMPUTE_PGM_RSRC1_IEEE_MODE_MASK) != 0u; cs_regs.fp16_overflow = ((value >> Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_FP16_OVFL_MASK) != 0u; - cs_regs.bulky = - (value >> Pm4::COMPUTE_PGM_RSRC1_BULKY_SHIFT) & Pm4::COMPUTE_PGM_RSRC1_BULKY_MASK; - cs_regs.wave_size = (((value >> Pm4::COMPUTE_PGM_RSRC1_W32_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC1_W32_EN_MASK) != 0u) - ? 32u - : 64u; + cs_regs.bulky = ((value >> Pm4::COMPUTE_PGM_RSRC1_BULKY_SHIFT) & + Pm4::COMPUTE_PGM_RSRC1_BULKY_MASK) != 0u; + cs_regs.threadgroup_configuration = ((value >> Pm4::COMPUTE_PGM_RSRC1_WGP_MODE_SHIFT) & + Pm4::COMPUTE_PGM_RSRC1_WGP_MODE_MASK) != 0u; + cs_regs.wave_size = (((value >> Pm4::COMPUTE_PGM_RSRC1_W32_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC1_W32_EN_MASK) != 0u) + ? 32u + : 64u; break; case Pm4::COMPUTE_PGM_RSRC2: - cs_regs.scratch_en = (value >> Pm4::COMPUTE_PGM_RSRC2_SCRATCH_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC2_SCRATCH_EN_MASK; + cs_regs.scratch_en = ((value >> Pm4::COMPUTE_PGM_RSRC2_SCRATCH_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC2_SCRATCH_EN_MASK) != 0u; cs_regs.user_sgpr = (value >> Pm4::COMPUTE_PGM_RSRC2_USER_SGPR_SHIFT) & Pm4::COMPUTE_PGM_RSRC2_USER_SGPR_MASK; - cs_regs.tgid_x_en = (value >> Pm4::COMPUTE_PGM_RSRC2_TGID_X_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC2_TGID_X_EN_MASK; - cs_regs.tgid_y_en = (value >> Pm4::COMPUTE_PGM_RSRC2_TGID_Y_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC2_TGID_Y_EN_MASK; - cs_regs.tgid_z_en = (value >> Pm4::COMPUTE_PGM_RSRC2_TGID_Z_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC2_TGID_Z_EN_MASK; - cs_regs.tg_size_en = (value >> Pm4::COMPUTE_PGM_RSRC2_TG_SIZE_EN_SHIFT) & - Pm4::COMPUTE_PGM_RSRC2_TG_SIZE_EN_MASK; + cs_regs.tgid_x_en = ((value >> Pm4::COMPUTE_PGM_RSRC2_TGID_X_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC2_TGID_X_EN_MASK) != 0u; + cs_regs.tgid_y_en = ((value >> Pm4::COMPUTE_PGM_RSRC2_TGID_Y_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC2_TGID_Y_EN_MASK) != 0u; + cs_regs.tgid_z_en = ((value >> Pm4::COMPUTE_PGM_RSRC2_TGID_Z_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC2_TGID_Z_EN_MASK) != 0u; + cs_regs.tg_size_en = ((value >> Pm4::COMPUTE_PGM_RSRC2_TG_SIZE_EN_SHIFT) & + Pm4::COMPUTE_PGM_RSRC2_TG_SIZE_EN_MASK) != 0u; cs_regs.tidig_comp_cnt = (value >> Pm4::COMPUTE_PGM_RSRC2_TIDIG_COMP_CNT_SHIFT) & Pm4::COMPUTE_PGM_RSRC2_TIDIG_COMP_CNT_MASK; cs_regs.lds_size = (value >> Pm4::COMPUTE_PGM_RSRC2_LDS_SIZE_SHIFT) & @@ -4241,29 +4243,28 @@ void GraphicsInitJmpTablesShIndirect() { }; g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC1_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) { - HW::VsShaderResource1 r1; - r1.vgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, VGPRS); - r1.sgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, SGPRS); - r1.priority = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, PRIORITY); - r1.float_mode = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FLOAT_MODE); - r1.dx10_clamp = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, DX10_CLAMP) != 0; - r1.ieee_mode = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, IEEE_MODE) != 0; - r1.vgpr_component_count = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, VGPR_COMP_CNT); - r1.cu_group_enable = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, CU_GROUP_ENABLE) != 0; + HW::HsShaderResource1 r1; + r1.vgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, VGPRS); + r1.priority = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, PRIORITY); + r1.float_mode = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, FLOAT_MODE); + r1.dx10_clamp = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, DX10_CLAMP) != 0; + r1.debug_mode = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, DEBUG_MODE) != 0; + r1.ieee_mode = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, IEEE_MODE) != 0; r1.require_forward_progress = - KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FWD_PROGRESS) != 0; - r1.fp16_overflow = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_VS, FP16_OVFL) != 0; + KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, FWD_PROGRESS) != 0; + r1.threadgroup_configuration = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, WGP_MODE) != 0; + r1.ls_vgpr_component_count = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, LS_VGPR_COMP_CNT); + r1.fp16_overflow = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_HS, FP16_OVFL) != 0; cp.GetShCtx().SetHsShaderResource1(r1); }; g_hw_sh_indirect_func[Pm4::SPI_SHADER_PGM_RSRC2_HS] = [](KYTY_HW_SH_INDIRECT_ARGS) { - HW::VsShaderResource2 r2; - r2.scratch_en = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SCRATCH_EN) != 0; - r2.user_sgpr = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, USER_SGPR) + - (KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, USER_SGPR_MSB) << 5u); - r2.offchip_lds = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, OC_LDS_EN) != 0; - r2.streamout_enabled = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SO_EN) != 0; - r2.shared_vgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_VS, SHARED_VGPR_CNT); + HW::HsShaderResource2 r2; + r2.scratch_en = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_HS, SCRATCH_EN) != 0; + r2.user_sgpr = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_HS, USER_SGPR) + + (KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_HS, USER_SGPR_MSB) << 5u); + r2.lds_size = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_HS, LDS_SIZE); + r2.shared_vgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_HS, SHARED_VGPR_CNT); cp.GetShCtx().SetHsShaderResource2(r2); }; @@ -4351,7 +4352,7 @@ void GraphicsInitJmpTablesShIndirect() { r1.cu_group_enable = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, CU_GROUP_ENABLE) != 0; r1.require_forward_progress = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, FWD_PROGRESS) != 0; - r1.lds_configuration = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, WGP_MODE) != 0; + r1.threadgroup_configuration = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, WGP_MODE) != 0; r1.gs_vgpr_component_count = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, GS_VGPR_COMP_CNT); r1.fp16_overflow = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC1_GS, FP16_OVFL) != 0; cp.GetShCtx().SetGsShaderResource1(r1); @@ -4411,7 +4412,7 @@ void GraphicsInitJmpTablesShIndirect() { r2.wave_cnt_en = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_PS, WAVE_CNT_EN); r2.extra_lds_size = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_PS, EXTRA_LDS_SIZE); r2.raster_ordered_shading = - KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_PS, LOAD_INTRAWAVE_COLLISION); + KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_PS, RASTER_ORDERED_SHADING); r2.shared_vgprs = KYTY_PM4_GET(value, SPI_SHADER_PGM_RSRC2_PS, SHARED_VGPR_CNT); cp.GetShCtx().SetPsShaderResource2(r2); }; diff --git a/src/graphics/guest_gpu/hardwareContext.h b/src/graphics/guest_gpu/hardwareContext.h index c92fc3562..4699e7dff 100644 --- a/src/graphics/guest_gpu/hardwareContext.h +++ b/src/graphics/guest_gpu/hardwareContext.h @@ -482,6 +482,26 @@ struct VsShaderResource2 { uint8_t shared_vgprs = 0; }; +struct HsShaderResource1 { + uint8_t vgprs = 0; + uint8_t priority = 0; + uint8_t float_mode = 0; + bool dx10_clamp = false; + bool debug_mode = false; + bool ieee_mode = false; + bool require_forward_progress = false; + bool threadgroup_configuration = false; + uint8_t ls_vgpr_component_count = 0; + bool fp16_overflow = false; +}; + +struct HsShaderResource2 { + bool scratch_en = false; + uint8_t user_sgpr = 0; + uint16_t lds_size = 0; + uint8_t shared_vgprs = 0; +}; + struct PsShaderResource1 { uint8_t vgprs = 0; uint8_t sgprs = 0; @@ -500,7 +520,7 @@ struct PsShaderResource2 { uint8_t user_sgpr = 0; bool wave_cnt_en = false; uint8_t extra_lds_size = 0; - bool raster_ordered_shading = false; + uint8_t raster_ordered_shading = 0; uint8_t shared_vgprs = 0; }; @@ -513,26 +533,27 @@ struct PsStageRegisters { struct CsStageRegisters { - uint64_t data_addr = 0; - uint32_t num_thread_x = 0; - uint32_t num_thread_y = 0; - uint32_t num_thread_z = 0; - uint8_t vgprs = 0; - uint8_t sgprs = 0; - uint8_t float_mode = 0; - bool dx10_clamp = false; - bool ieee_mode = false; - bool fp16_overflow = false; - uint8_t bulky = 0; - uint8_t wave_size = 64; - uint8_t scratch_en = 0; - uint8_t user_sgpr = 0; - uint8_t tgid_x_en = 0; - uint8_t tgid_y_en = 0; - uint8_t tgid_z_en = 0; - uint8_t tg_size_en = 0; - uint8_t tidig_comp_cnt = 0; - uint8_t lds_size = 0; + uint64_t data_addr = 0; + uint32_t num_thread_x = 0; + uint32_t num_thread_y = 0; + uint32_t num_thread_z = 0; + uint8_t vgprs = 0; + uint8_t sgprs = 0; + uint8_t float_mode = 0; + bool dx10_clamp = false; + bool ieee_mode = false; + bool fp16_overflow = false; + bool bulky = false; + bool threadgroup_configuration = false; + uint8_t wave_size = 64; + bool scratch_en = false; + uint8_t user_sgpr = 0; + bool tgid_x_en = false; + bool tgid_y_en = false; + bool tgid_z_en = false; + bool tg_size_en = false; + uint8_t tidig_comp_cnt = 0; + uint16_t lds_size = 0; }; struct EsStageRegisters { @@ -547,24 +568,24 @@ struct LsStageRegisters { struct HsStageRegisters { uint64_t data_addr = 0; - VsShaderResource1 rsrc1; - VsShaderResource2 rsrc2; + HsShaderResource1 rsrc1; + HsShaderResource2 rsrc2; uint64_t chksum = 0; }; struct GsShaderResource1 { - uint8_t vgprs = 0; - uint8_t sgprs = 0; - uint8_t priority = 0; - uint8_t float_mode = 0; - bool dx10_clamp = false; - bool debug_mode = false; - bool ieee_mode = false; - bool cu_group_enable = false; - bool require_forward_progress = false; - bool lds_configuration = false; - uint8_t gs_vgpr_component_count = 0; - bool fp16_overflow = false; + uint8_t vgprs = 0; + uint8_t sgprs = 0; + uint8_t priority = 0; + uint8_t float_mode = 0; + bool dx10_clamp = false; + bool debug_mode = false; + bool ieee_mode = false; + bool cu_group_enable = false; + bool require_forward_progress = false; + bool threadgroup_configuration = false; + uint8_t gs_vgpr_component_count = 0; + bool fp16_overflow = false; }; struct GsShaderResource2 { @@ -1038,8 +1059,8 @@ public: void SetLsShaderResource1(const VsShaderResource1& rsrc1) { m_vs.ls_regs.rsrc1 = rsrc1; } void SetLsShaderResource2(const VsShaderResource2& rsrc2) { m_vs.ls_regs.rsrc2 = rsrc2; } void SetHsShaderBase(uint64_t addr) { m_vs.hs_regs.data_addr = addr; } - void SetHsShaderResource1(const VsShaderResource1& rsrc1) { m_vs.hs_regs.rsrc1 = rsrc1; } - void SetHsShaderResource2(const VsShaderResource2& rsrc2) { m_vs.hs_regs.rsrc2 = rsrc2; } + void SetHsShaderResource1(const HsShaderResource1& rsrc1) { m_vs.hs_regs.rsrc1 = rsrc1; } + void SetHsShaderResource2(const HsShaderResource2& rsrc2) { m_vs.hs_regs.rsrc2 = rsrc2; } void SetHsShaderChksum(uint32_t value) { m_vs.hs_regs.chksum = value; } void SetGsShaderBase(uint64_t addr) { m_vs.gs_regs.data_addr = addr; } void SetGsShaderResource1(const GsShaderResource1& rsrc1) { m_vs.gs_regs.rsrc1 = rsrc1; } diff --git a/src/graphics/guest_gpu/pm4.h b/src/graphics/guest_gpu/pm4.h index 996e36569..a5fb532a0 100644 --- a/src/graphics/guest_gpu/pm4.h +++ b/src/graphics/guest_gpu/pm4.h @@ -779,21 +779,21 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_MASK = 0x1; constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_SHIFT = 29; constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_MASK = 0x1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_SHIFT = 8; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_MASK = 0xFF; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_SHIFT = 26; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_MASK = 0x1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_SHIFT = 27; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_MASK = 0x1; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_SHIFT = 28; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK = 0xF; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_SHIFT = 8; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_MASK = 0xFF; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_RASTER_ORDERED_SHADING_SHIFT = 25; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_RASTER_ORDERED_SHADING_MASK = 0x3; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_SHIFT = 27; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_SHIFT = 28; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK = 0xF; constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC; constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B; @@ -886,51 +886,81 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_MASK = 0x1; constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_SHIFT = 28; constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_MASK = 0xF; -constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C; -constexpr uint32_t SPI_SHADER_USER_DATA_GS_15 = 0x9B; -constexpr uint32_t SPI_SHADER_USER_DATA_GS_31 = 0xAB; -constexpr uint32_t SPI_SHADER_REQ_CTRL_ESGS = 0xB0; -constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2; -constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_3 = 0xB5; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES_GS = 0xBC; -constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8; -constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9; -constexpr uint32_t SPI_SHADER_PGM_RSRC1_ES = 0xCA; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES = 0xCB; -constexpr uint32_t SPI_SHADER_USER_DATA_ES_0 = 0xCC; -constexpr uint32_t SPI_SHADER_USER_DATA_ES_15 = 0xDB; -constexpr uint32_t SPI_SHADER_USER_DATA_ES_31 = 0xEB; -constexpr uint32_t SPI_SHADER_PGM_CHKSUM_HS = 0x100; -constexpr uint32_t SPI_SHADER_PGM_RSRC4_HS = 0x101; -constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_HS = 0x102; -constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_HS = 0x103; -constexpr uint32_t SPI_SHADER_PGM_RSRC3_HS = 0x107; -constexpr uint32_t SPI_SHADER_PGM_LO_HS = 0x108; -constexpr uint32_t SPI_SHADER_PGM_HI_HS = 0x109; -constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS = 0x10A; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS = 0x10B; -constexpr uint32_t SPI_SHADER_USER_DATA_HS_0 = 0x10C; -constexpr uint32_t SPI_SHADER_USER_DATA_HS_15 = 0x11B; -constexpr uint32_t SPI_SHADER_USER_DATA_HS_31 = 0x12B; -constexpr uint32_t SPI_SHADER_REQ_CTRL_LSHS = 0x130; -constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_0 = 0x132; -constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_3 = 0x135; -constexpr uint32_t SPI_SHADER_PGM_LO_LS = 0x148; -constexpr uint32_t SPI_SHADER_PGM_HI_LS = 0x149; -constexpr uint32_t SPI_SHADER_PGM_RSRC1_LS = 0x14A; -constexpr uint32_t SPI_SHADER_PGM_RSRC2_LS = 0x14B; -constexpr uint32_t COMPUTE_START_X = 0x204; -constexpr uint32_t COMPUTE_START_Y = 0x205; -constexpr uint32_t COMPUTE_START_Z = 0x206; -constexpr uint32_t COMPUTE_NUM_THREAD_X = 0x207; -constexpr uint32_t COMPUTE_NUM_THREAD_Y = 0x208; -constexpr uint32_t COMPUTE_NUM_THREAD_Z = 0x209; -constexpr uint32_t COMPUTE_PGM_LO = 0x20C; -constexpr uint32_t COMPUTE_PGM_HI = 0x20D; -constexpr uint32_t COMPUTE_TBA_LO = 0x20E; -constexpr uint32_t COMPUTE_TBA_HI = 0x20F; -constexpr uint32_t COMPUTE_TMA_LO = 0x210; -constexpr uint32_t COMPUTE_TMA_HI = 0x211; +constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C; +constexpr uint32_t SPI_SHADER_USER_DATA_GS_15 = 0x9B; +constexpr uint32_t SPI_SHADER_USER_DATA_GS_31 = 0xAB; +constexpr uint32_t SPI_SHADER_REQ_CTRL_ESGS = 0xB0; +constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2; +constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_3 = 0xB5; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES_GS = 0xBC; +constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8; +constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_ES = 0xCA; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_ES = 0xCB; +constexpr uint32_t SPI_SHADER_USER_DATA_ES_0 = 0xCC; +constexpr uint32_t SPI_SHADER_USER_DATA_ES_15 = 0xDB; +constexpr uint32_t SPI_SHADER_USER_DATA_ES_31 = 0xEB; +constexpr uint32_t SPI_SHADER_PGM_CHKSUM_HS = 0x100; +constexpr uint32_t SPI_SHADER_PGM_RSRC4_HS = 0x101; +constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_HS = 0x102; +constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_HS = 0x103; +constexpr uint32_t SPI_SHADER_PGM_RSRC3_HS = 0x107; +constexpr uint32_t SPI_SHADER_PGM_LO_HS = 0x108; +constexpr uint32_t SPI_SHADER_PGM_HI_HS = 0x109; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS = 0x10A; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS = 0x10B; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_VGPRS_SHIFT = 0; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_VGPRS_MASK = 0x3F; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_PRIORITY_SHIFT = 10; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_PRIORITY_MASK = 0x3; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FLOAT_MODE_SHIFT = 12; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FLOAT_MODE_MASK = 0xFF; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_DX10_CLAMP_SHIFT = 21; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_DX10_CLAMP_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_DEBUG_MODE_SHIFT = 22; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_DEBUG_MODE_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_IEEE_MODE_SHIFT = 23; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_IEEE_MODE_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FWD_PROGRESS_SHIFT = 25; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FWD_PROGRESS_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_WGP_MODE_SHIFT = 26; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_WGP_MODE_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_LS_VGPR_COMP_CNT_SHIFT = 28; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_LS_VGPR_COMP_CNT_MASK = 0x3; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FP16_OVFL_SHIFT = 30; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS_FP16_OVFL_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_SCRATCH_EN_SHIFT = 0; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_SCRATCH_EN_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_USER_SGPR_SHIFT = 1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_USER_SGPR_MASK = 0x1F; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_LDS_SIZE_SHIFT = 18; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_LDS_SIZE_MASK = 0x1FF; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_USER_SGPR_MSB_SHIFT = 27; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_USER_SGPR_MSB_MASK = 0x1; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_SHARED_VGPR_CNT_SHIFT = 28; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS_SHARED_VGPR_CNT_MASK = 0xF; +constexpr uint32_t SPI_SHADER_USER_DATA_HS_0 = 0x10C; +constexpr uint32_t SPI_SHADER_USER_DATA_HS_15 = 0x11B; +constexpr uint32_t SPI_SHADER_USER_DATA_HS_31 = 0x12B; +constexpr uint32_t SPI_SHADER_REQ_CTRL_LSHS = 0x130; +constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_0 = 0x132; +constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_3 = 0x135; +constexpr uint32_t SPI_SHADER_PGM_LO_LS = 0x148; +constexpr uint32_t SPI_SHADER_PGM_HI_LS = 0x149; +constexpr uint32_t SPI_SHADER_PGM_RSRC1_LS = 0x14A; +constexpr uint32_t SPI_SHADER_PGM_RSRC2_LS = 0x14B; +constexpr uint32_t COMPUTE_START_X = 0x204; +constexpr uint32_t COMPUTE_START_Y = 0x205; +constexpr uint32_t COMPUTE_START_Z = 0x206; +constexpr uint32_t COMPUTE_NUM_THREAD_X = 0x207; +constexpr uint32_t COMPUTE_NUM_THREAD_Y = 0x208; +constexpr uint32_t COMPUTE_NUM_THREAD_Z = 0x209; +constexpr uint32_t COMPUTE_PGM_LO = 0x20C; +constexpr uint32_t COMPUTE_PGM_HI = 0x20D; +constexpr uint32_t COMPUTE_TBA_LO = 0x20E; +constexpr uint32_t COMPUTE_TBA_HI = 0x20F; +constexpr uint32_t COMPUTE_TMA_LO = 0x210; +constexpr uint32_t COMPUTE_TMA_HI = 0x211; constexpr uint32_t COMPUTE_PGM_RSRC1 = 0x212; constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT = 0; @@ -947,6 +977,8 @@ constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_SHIFT = 24; constexpr uint32_t COMPUTE_PGM_RSRC1_BULKY_MASK = 0x1; constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_SHIFT = 26; constexpr uint32_t COMPUTE_PGM_RSRC1_FP16_OVFL_MASK = 0x1; +constexpr uint32_t COMPUTE_PGM_RSRC1_WGP_MODE_SHIFT = 29; +constexpr uint32_t COMPUTE_PGM_RSRC1_WGP_MODE_MASK = 0x1; constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_SHIFT = 30; constexpr uint32_t COMPUTE_PGM_RSRC1_W32_EN_MASK = 0x1; diff --git a/src/graphics/shader/shader.cpp b/src/graphics/shader/shader.cpp index 67804b008..2ae0ff0b8 100644 --- a/src/graphics/shader/shader.cpp +++ b/src/graphics/shader/shader.cpp @@ -302,7 +302,7 @@ static void vs_check(const HW::VertexShaderInfo& vs, const HW::ShaderRegisters& EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.ieee_mode != false); EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.cu_group_enable != false); EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.require_forward_progress != false); - EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.lds_configuration != false); + EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.threadgroup_configuration != false); EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.gs_vgpr_component_count != 3); EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc1.fp16_overflow != false); EXIT_NOT_IMPLEMENTED(vs.gs_regs.rsrc2.scratch_en != false); @@ -374,7 +374,7 @@ static void ps_check(const HW::PsStageRegisters& ps, const HW::ShaderRegisters& ps.rsrc2.extra_lds_size); } } - EXIT_NOT_IMPLEMENTED(ps.rsrc2.raster_ordered_shading != false); + EXIT_NOT_IMPLEMENTED(ps.rsrc2.raster_ordered_shading != 0); EXIT_NOT_IMPLEMENTED(ps.rsrc2.shared_vgprs != 0); if (sh.shader_z_format != 0x00000000 && sh.shader_z_format != 0x00000001 &&