mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
shader: run merged geometry stages as mesh shaders
Co-authored-by: Brandon Strong <brandostrong@gmail.com> Co-authored-by: fxpw <fxpw@outlook.com> Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
This commit is contained in:
nmzik
@@ -110,8 +110,9 @@ Decoder::Operand Translator::PlainOperand(const Decoder::Operand& operand) {
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}
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std::array<IR::U32, 2> Translator::BallotMask(IR::U1 value) {
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return {ir.Select(value, IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u))),
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IR::U32(IR::Value(0u))};
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const auto mask = ir.Emit(IR::ValueOpcode::Ballot, {value});
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return {ir.CompositeExtract(mask, 0),
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current_wave_size == 64u ? ir.CompositeExtract(mask, 1) : IR::U32(IR::Value(0u))};
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}
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IR::U32 Translator::ReadRawU32(const Decoder::Operand& operand) {
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@@ -285,7 +286,6 @@ void Translator::WriteRawU32(const Decoder::Operand& operand, IR::U32 value) {
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case Decoder::OperandKind::Sgpr: {
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const auto reg = static_cast<IR::ScalarReg>(operand.reg);
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ir.SetScalarReg(reg, value);
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ir.SetThreadBitScalarReg(reg, ThreadBit(value));
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ir.SetScalarMaskTag(reg, IR::U1(IR::Value(false)));
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if (IR::RegIndex(reg) > 0u) {
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ir.SetScalarMaskTag(static_cast<IR::ScalarReg>(IR::RegIndex(reg) - 1u),
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@@ -314,20 +314,20 @@ void Translator::WriteRawU32(const Decoder::Operand& operand, IR::U32 value) {
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}
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case Decoder::OperandKind::VccLo:
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ir.SetVccLo(IR::U32(value));
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ir.SetVcc(ThreadBit(IR::U32(value)));
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ir.SetVcc(ThreadBit({value, ir.GetVccHi()}));
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break;
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case Decoder::OperandKind::VccHi:
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ir.SetVccHi(IR::U32(value));
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ir.SetVcc(ThreadBit(ir.GetVccLo()));
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ir.SetVcc(ThreadBit({ir.GetVccLo(), value}));
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break;
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case Decoder::OperandKind::M0: ir.SetM0(IR::U32(value)); break;
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case Decoder::OperandKind::ExecLo:
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ir.SetExecLo(IR::U32(value));
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ir.SetExec(ThreadBit(IR::U32(value)));
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ir.SetExec(ThreadBit({value, ir.GetExecHi()}));
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break;
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case Decoder::OperandKind::ExecHi:
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ir.SetExecHi(IR::U32(value));
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ir.SetExec(ThreadBit(ir.GetExecLo()));
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ir.SetExec(ThreadBit({ir.GetExecLo(), value}));
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break;
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case Decoder::OperandKind::Scc:
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ir.SetScc(ir.INotEqual(value, IR::U32(IR::Value(0u))));
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@@ -576,15 +576,14 @@ void Translator::WriteU32Pair(const Decoder::Operand& operand,
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if (operand.kind == Decoder::OperandKind::Null) {
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return;
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}
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const auto thread_bit = ThreadBit(value[0]);
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switch (operand.kind) {
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case Decoder::OperandKind::ExecLo:
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ir.SetExec(thread_bit);
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ir.SetExec(ThreadBit(value));
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ir.SetExecLo(value[0]);
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ir.SetExecHi(value[1]);
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return;
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case Decoder::OperandKind::VccLo:
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ir.SetVcc(thread_bit);
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ir.SetVcc(ThreadBit(value));
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ir.SetVccLo(value[0]);
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ir.SetVccHi(value[1]);
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return;
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@@ -595,8 +594,14 @@ void Translator::WriteU32Pair(const Decoder::Operand& operand,
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WriteRawU32(OffsetOperand(operand, 1), value[1]);
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}
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IR::U1 Translator::ThreadBit(IR::U32 low) {
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return ir.INotEqual(low, IR::U32(IR::Value(0u)));
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IR::U1 Translator::ThreadBit(const std::array<IR::U32, 2>& mask) {
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const auto lane = IR::U32(ir.Emit(IR::ValueOpcode::LaneId));
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const auto word = current_wave_size == 64u
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? ir.Select(ir.ULessThan(lane, IR::U32(IR::Value(32u))), mask[0], mask[1])
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: mask[0];
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const auto bit = ir.BitwiseAnd(lane, IR::U32(IR::Value(31u)));
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return ir.INotEqual(ir.BitwiseAnd(ir.ShiftRightLogical(word, bit), IR::U32(IR::Value(1u))),
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IR::U32(IR::Value(0u)));
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}
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IR::U1 Translator::ReadCondition(const Decoder::Operand& operand) {
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@@ -604,11 +609,6 @@ IR::U1 Translator::ReadCondition(const Decoder::Operand& operand) {
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}
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IR::U32 Translator::ConditionBit(const Decoder::Operand& operand) {
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if (operand.kind == Decoder::OperandKind::LiteralConstant ||
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operand.kind == Decoder::OperandKind::IntegerInlineConstant ||
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operand.kind == Decoder::OperandKind::FloatInlineConstant) {
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return IR::U32(IR::Value(operand.value & 1u));
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}
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return ir.Select(ReadMask(operand), IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u)));
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}
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@@ -616,12 +616,17 @@ IR::U1 Translator::ReadMask(const Decoder::Operand& operand) {
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if (operand.kind == Decoder::OperandKind::LiteralConstant ||
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operand.kind == Decoder::OperandKind::IntegerInlineConstant ||
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operand.kind == Decoder::OperandKind::FloatInlineConstant) {
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return IR::U1(IR::Value(operand.value != 0u));
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return ThreadBit(ReadU32Pair(operand));
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}
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switch (operand.kind) {
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case Decoder::OperandKind::Sgpr: {
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const auto reg = static_cast<IR::ScalarReg>(operand.reg);
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return ir.GetThreadBitScalarReg(reg);
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const auto mask = current_wave_size == 64u
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? ReadU32Pair(operand)
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: std::array {ReadRawU32(operand), IR::U32(IR::Value(0u))};
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return IR::U1(ir.Emit(
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IR::ValueOpcode::SelectU1,
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{ir.GetScalarMaskTag(reg), ir.GetThreadBitScalarReg(reg), ThreadBit(mask)}));
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}
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case Decoder::OperandKind::ExecLo:
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case Decoder::OperandKind::ExecHi: return ir.GetExec();
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@@ -660,11 +665,12 @@ IR::U1 Translator::ReadMaskValid(const Decoder::Operand& operand) {
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}
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}
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void Translator::WriteMask(const Decoder::Operand& operand, IR::U1 value) {
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std::array<IR::U32, 2> Translator::WriteMask(const Decoder::Operand& operand, IR::U1 value,
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bool write_64) {
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const auto mask = BallotMask(value);
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switch (operand.kind) {
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case Decoder::OperandKind::Sgpr: {
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const auto reg = static_cast<IR::ScalarReg>(operand.reg);
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const auto mask = BallotMask(value);
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ir.SetThreadBitScalarReg(reg, value);
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ir.SetScalarMaskTag(reg, IR::U1(IR::Value(true)));
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if (IR::RegIndex(reg) > 0u) {
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@@ -673,57 +679,34 @@ void Translator::WriteMask(const Decoder::Operand& operand, IR::U1 value) {
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}
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ir.SetScalarReg(reg, mask[0]);
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// A wave32 VALU mask destination must not overwrite the neighboring SGPR.
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if (current_wave_size == 64u && IR::RegIndex(reg) + 1u < IR::NumScalarRegs) {
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if ((write_64 || current_wave_size == 64u) &&
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IR::RegIndex(reg) + 1u < IR::NumScalarRegs) {
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const auto high = static_cast<IR::ScalarReg>(IR::RegIndex(reg) + 1u);
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ir.SetScalarReg(high, mask[1]);
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ir.SetThreadBitScalarReg(high, IR::U1(IR::Value(false)));
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ir.SetScalarMaskTag(high, IR::U1(IR::Value(false)));
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}
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return;
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return mask;
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}
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case Decoder::OperandKind::ExecLo:
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case Decoder::OperandKind::ExecHi: {
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const auto mask = BallotMask(value);
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ir.SetExec(value);
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ir.SetExecLo(mask[0]);
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ir.SetExecHi(mask[1]);
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return;
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return mask;
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}
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case Decoder::OperandKind::VccLo:
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case Decoder::OperandKind::VccHi: {
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const auto mask = BallotMask(value);
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ir.SetVcc(value);
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ir.SetVccLo(mask[0]);
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ir.SetVccHi(mask[1]);
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return;
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return mask;
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}
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case Decoder::OperandKind::Scc: ir.SetScc(value); return;
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case Decoder::OperandKind::Scc: ir.SetScc(value); return mask;
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default:
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WriteRawU32(operand, ir.Select(value, IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u))));
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WriteRawU32(OffsetOperand(operand, 1), IR::U32(IR::Value(0u)));
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return;
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}
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}
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void Translator::WriteMask64(const Decoder::Operand& operand, IR::U1 value) {
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if (operand.kind != Decoder::OperandKind::Sgpr) {
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WriteMask(operand, value);
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return;
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}
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const auto reg = static_cast<IR::ScalarReg>(operand.reg);
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const auto mask = BallotMask(value);
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ir.SetThreadBitScalarReg(reg, value);
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ir.SetScalarMaskTag(reg, IR::U1(IR::Value(true)));
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if (IR::RegIndex(reg) > 0u) {
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ir.SetScalarMaskTag(static_cast<IR::ScalarReg>(IR::RegIndex(reg) - 1u),
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IR::U1(IR::Value(false)));
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}
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ir.SetScalarReg(reg, mask[0]);
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if (IR::RegIndex(reg) + 1u < IR::NumScalarRegs) {
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const auto high = static_cast<IR::ScalarReg>(IR::RegIndex(reg) + 1u);
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ir.SetScalarReg(high, mask[1]);
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ir.SetThreadBitScalarReg(high, IR::U1(IR::Value(false)));
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ir.SetScalarMaskTag(high, IR::U1(IR::Value(false)));
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WriteRawU32(operand, mask[0]);
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WriteRawU32(OffsetOperand(operand, 1), mask[1]);
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return mask;
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}
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}
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@@ -910,6 +893,7 @@ void ValidateTranslateOptions(const TranslateOptions& options) {
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}
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switch (options.stage) {
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case ShaderType::Vertex:
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case ShaderType::Mesh:
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if (options.vertex == nullptr) {
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EXIT("vertex shader translation has no vertex input metadata");
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}
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@@ -1022,12 +1006,32 @@ IR::Program TranslateProgram(const Decoder::Program& decoded, const CFG::Graph&
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}
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const auto value = entry_ir.GetUserData(reg);
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entry_ir.SetScalarReg(reg, value);
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entry_ir.SetThreadBitScalarReg(reg, entry_ir.INotEqual(value, IR::U32(IR::Value(0u))));
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entry_ir.SetScalarMaskTag(reg, IR::U1(IR::Value(false)));
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}
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entry_ir.SetExec(IR::U1(IR::Value(true)));
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entry_ir.SetExecLo(IR::U32(IR::Value(1u)));
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entry_ir.SetExecHi(IR::U32(IR::Value(0u)));
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auto initial_exec = IR::U1(IR::Value(true));
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uint32_t total_threads = 0;
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ShaderStageInputInfo stage_input {};
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if (options.stage == ShaderType::Compute) {
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stage_input.compute = options.compute;
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} else {
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stage_input.vertex = options.vertex;
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}
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const auto* workgroup = ShaderWorkgroupInput(options.stage, stage_input);
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if (workgroup != nullptr) {
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total_threads = std::max(workgroup->threads_num[0], 1u) *
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std::max(workgroup->threads_num[1], 1u) *
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std::max(workgroup->threads_num[2], 1u);
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if (options.wave_size == 64u && workgroup->host_subgroup_size == 32u &&
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total_threads % 64u != 0u) {
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initial_exec = entry_ir.ULessThan(builtin(IR::StageInputKind::LocalInvocationIndex),
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IR::U32(IR::Value(total_threads)));
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}
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}
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entry_ir.SetExec(initial_exec);
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const auto initial_mask = entry_ir.Emit(IR::ValueOpcode::Ballot, {initial_exec});
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entry_ir.SetExecLo(entry_ir.CompositeExtract(initial_mask, 0));
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entry_ir.SetExecHi(options.wave_size == 64u ? entry_ir.CompositeExtract(initial_mask, 1)
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: IR::U32(IR::Value(0u)));
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if (options.stage == ShaderType::Compute) {
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const auto* cs = options.compute;
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const auto thread_ids =
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@@ -1046,9 +1050,6 @@ IR::Program TranslateProgram(const Decoder::Program& decoded, const CFG::Graph&
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}
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if (cs->tg_size_en) {
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const auto wave_size = cs->wave_size != 0u ? cs->wave_size : 64u;
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const auto total_threads = std::max(cs->threads_num[0], 1u) *
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std::max(cs->threads_num[1], 1u) *
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std::max(cs->threads_num[2], 1u);
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const auto waves = std::min((total_threads + wave_size - 1u) / wave_size, 0x3fu);
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const auto local_index = builtin(IR::StageInputKind::LocalInvocationIndex);
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const auto wave_id = IR::U32(
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@@ -1062,6 +1063,53 @@ IR::Program TranslateProgram(const Decoder::Program& decoded, const CFG::Graph&
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entry_ir.BitwiseOr(entry_ir.BitwiseOr(wave_bits, IR::U32(IR::Value(waves))),
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first_bit));
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}
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} else if (options.stage == ShaderType::Mesh) {
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const auto& mesh = options.vertex->mesh;
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EXIT_NOT_IMPLEMENTED(options.wave_size != 64u || mesh.primitives_per_group == 0u ||
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mesh.vertices_per_group > 64u || total_threads > 15u * 64u);
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const auto u32 = [](uint32_t value) { return IR::U32(IR::Value(value)); };
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const auto draw = [&](uint32_t index) {
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return IR::U32(
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entry_ir.Emit(IR::ValueOpcode::MeshDrawParameter, {IR::Value(index)}));
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};
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const auto minimum = [&](IR::U32 lhs, IR::U32 rhs) {
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return IR::U32(entry_ir.Emit(IR::ValueOpcode::UMin32, {lhs, rhs}));
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};
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const auto subtract_saturate = [&](IR::U32 lhs, IR::U32 rhs) {
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return entry_ir.ISub(lhs, minimum(lhs, rhs));
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};
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const auto local = builtin(IR::StageInputKind::LocalInvocationIndex);
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const auto chunk = entry_ir.IMul(builtin(IR::StageInputKind::WorkgroupId, 0),
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u32(mesh.primitives_per_group));
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const auto vertices =
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minimum(subtract_saturate(draw(0), chunk), u32(mesh.vertices_per_group));
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const auto primitives = subtract_saturate(vertices, u32(2));
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const auto wave = entry_ir.ShiftRightLogical(local, u32(6));
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const auto wave_base = entry_ir.BitwiseAnd(local, u32(~63u));
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const auto vertex_count = minimum(subtract_saturate(vertices, wave_base), u32(64));
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const auto primitive_count = minimum(subtract_saturate(primitives, wave_base), u32(64));
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const auto wave_info = entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(wave, u32(24)),
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u32(((total_threads + 63u) / 64u) << 28u));
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entry_ir.SetScalarReg(
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static_cast<IR::ScalarReg>(3),
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entry_ir.BitwiseOr(wave_info, entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(
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primitive_count, u32(8)),
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vertex_count)));
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// Triangle-strip adjacency addresses the ES records in LDS. Alternating the
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// first two indices preserves winding across subgroup boundaries.
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const auto parity = entry_ir.BitwiseAnd(entry_ir.IAdd(chunk, local), u32(1));
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const auto first = entry_ir.IAdd(local, parity);
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const auto second = entry_ir.ISub(entry_ir.IAdd(local, u32(1)), parity);
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(0),
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entry_ir.BitwiseOr(entry_ir.ShiftLeftLogical(first, u32(2)),
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entry_ir.ShiftLeftLogical(second, u32(18))));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(1),
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entry_ir.ShiftLeftLogical(entry_ir.IAdd(local, u32(2)), u32(2)));
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entry_ir.SetVectorReg(static_cast<IR::VectorReg>(5),
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entry_ir.IAdd(draw(1), entry_ir.IAdd(chunk, local)));
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entry_ir.SetVectorReg(
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static_cast<IR::VectorReg>(8),
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entry_ir.IAdd(draw(2), builtin(IR::StageInputKind::WorkgroupId, 1)));
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} else if (options.stage == ShaderType::Pixel) {
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const auto* ps = options.pixel;
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if (ps->ps_perspective_center_vgpr != UINT32_MAX) {
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