mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 10:56:58 +02:00
shader: run merged geometry stages as mesh shaders
Co-authored-by: Brandon Strong <brandostrong@gmail.com> Co-authored-by: fxpw <fxpw@outlook.com> Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com>
This commit is contained in:
nmzik
+66
-162
@@ -21,7 +21,6 @@
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#include "graphics/shader/recompiler/ir/passes/ReadLaneElimination.h"
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#include "graphics/shader/recompiler/ir/passes/ResourceTracking.h"
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#include "graphics/shader/recompiler/ir/passes/ShaderInfoCollection.h"
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#include "graphics/shader/recompiler/ir/passes/SharedMemoryBarrier.h"
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#include "graphics/shader/recompiler/ir/passes/SrtWalker.h"
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#include "graphics/shader/recompiler/ir/passes/SsaRewrite.h"
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#include "graphics/shader/shader.h"
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@@ -7882,9 +7881,9 @@ void TestNewShaderRecompilerCfgExecSccSharedArm() {
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"EXEC/SCC shared-arm SPIR-V has the wrong selection-merge count");
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Check(SpirvInstructionOpcodeCount(result.spirv, 251) == 0u,
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"EXEC/SCC shared-arm SPIR-V unexpectedly used dispatcher OpSwitch");
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Check(!Common::ContainsStr(DisassembleSpirvBinary(result.spirv),
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Check(Common::ContainsStr(DisassembleSpirvBinary(result.spirv),
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"OpGroupNonUniformBallot"),
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"per-invocation EXEC/SCC branch reconstructed a native subgroup mask");
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"scalar mask SCC did not reduce the complete wave mask");
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CheckSpirvBinaryValidates(result.spirv);
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}
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@@ -8727,6 +8726,43 @@ void TestNewShaderRecompilerSetpcBranch() {
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CheckSpirvBinaryValidates(result.spirv);
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}
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void TestFusedShaderHandoffPreservesRegisters() {
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using namespace ShaderRecompiler;
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const uint32_t front[] = {
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EncodeSMovB32(12, 255), 0x1003u, // three vertices and one primitive
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EncodeSop1(0x20, 0, 6), // merged-stage handoff through s[6:7]
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0xffffffffu, // front shader metadata must not be decoded
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};
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const uint32_t back[] = {
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EncodeSMovB32(124, 12), // s_mov_b32 m0, s12
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EncodeSopp(0x10, 9), // s_sendmsg MSG_GS_ALLOC_REQ
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EncodeSopp(0x01),
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};
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ShaderVertexInputInfo input{};
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input.mesh.threads_num[0] = 192;
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input.mesh.threads_num[1] = input.mesh.threads_num[2] = 1;
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input.mesh.primitives_per_group = 62;
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input.mesh.vertices_per_group = 64;
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CompileOptions options{};
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options.stage = ShaderType::Mesh;
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options.input_info.vertex = &input;
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options.back_code = back;
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auto translated = TranslateProgram(front, options);
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uint32_t allocations = 0;
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for (const auto* block: translated.program.blocks) {
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for (const auto& inst: *block) {
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if (inst.GetOpcode() != IR::ValueOpcode::MeshAllocate) {
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continue;
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}
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const auto value = inst.Arg(0).Resolve();
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Check(value.IsImmediate() && value.U32() == 0x1003u,
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"fused back shader lost the front shader's scalar register value");
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allocations++;
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}
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}
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Check(allocations == 1u, "fused shader omitted the back shader allocation");
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}
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void TestNewShaderRecompilerSetpcJumpTable() {
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const uint32_t shader[] = {
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EncodeSop2(0x07, 0, 0, 129), // s_min_u32 s0, s0, 1
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@@ -9237,6 +9273,7 @@ void TestTypedEntryStateIsMinimal() {
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uint32_t set_exec_lo = 0;
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uint32_t set_exec_hi = 0;
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uint32_t ballots = 0;
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const IR::Inst* ballot = nullptr;
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IR::Value exec;
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IR::Value exec_lo;
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IR::Value exec_hi;
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@@ -9245,6 +9282,7 @@ void TestTypedEntryStateIsMinimal() {
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switch (inst.GetOpcode()) {
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case IR::ValueOpcode::Ballot:
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ballots++;
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ballot = &inst;
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break;
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case IR::ValueOpcode::SetExec:
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set_exec++;
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@@ -9274,11 +9312,19 @@ void TestTypedEntryStateIsMinimal() {
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}
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}
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}
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const auto is_mask_word = [&](IR::Value value, uint32_t word) {
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const auto* extract = value.ResolveInstruction();
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return extract != nullptr &&
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extract->GetOpcode() == IR::ValueOpcode::CompositeExtractU32x4 &&
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extract->Arg(0).ResolveInstruction() == ballot &&
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extract->Arg(1).IsImmediate() && extract->Arg(1).U32() == word;
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};
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Check(set_exec == 1u && set_exec_lo == 1u && set_exec_hi == 1u &&
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ballots == 0u && exec.IsImmediate() && exec.U1() &&
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exec_lo.IsImmediate() && exec_lo.U32() == 1u &&
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exec_hi.IsImmediate() && exec_hi.U32() == 0u,
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"typed entry is not the local {1,0} invocation mask");
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ballots == 1u && exec.IsImmediate() && exec.U1() &&
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ballot->Arg(0) == exec && is_mask_word(exec_lo, 0u) &&
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(wave_size == 64u ? is_mask_word(exec_hi, 1u)
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: exec_hi.IsImmediate() && exec_hi.U32() == 0u),
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"typed entry did not materialize the active invocation mask once");
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IR::RewriteToSsa(values.blocks);
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IR::RemoveIdentities(values.blocks);
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@@ -9609,21 +9655,9 @@ void TestValuePhiValidation() {
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#endif
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}
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void TestWqmMaskSignatureAndU64ShiftConstantPropagation() {
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void TestU64ShiftConstantPropagation() {
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using namespace ShaderRecompiler::IR;
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#if KYTY_PLATFORM != KYTY_PLATFORM_WINDOWS
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Program malformed;
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malformed.block_storage.push_back(std::make_unique<Block>());
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malformed.blocks.push_back(malformed.block_storage.back().get());
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malformed.block_info.emplace_back();
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IREmitter malformed_ir(malformed.blocks.front());
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auto malformed_value = malformed_ir.Emit(ValueOpcode::WqmMask, {Value(true)});
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malformed_value.TryInstruction()->SetArg(0, Value(uint64_t{1}));
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ExpectFatal([&] { ValidateProgram(malformed, false); },
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"invalid WqmMask operand type did not terminate IR validation");
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#endif
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Program shifts;
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shifts.block_storage.push_back(std::make_unique<Block>());
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shifts.blocks.push_back(shifts.block_storage.back().get());
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@@ -10021,8 +10055,8 @@ void TestNewShaderRecompilerVertexExportUsesInvocationExecMask() {
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auto result = RecompileForTest(shader, options);
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(!Common::ContainsStr(source, "OpLoad %uint %gl_SubgroupInvocationID"),
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"vertex EXEC guard depends on the native subgroup lane");
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Check(Common::ContainsStr(source, "OpLoad %uint %gl_SubgroupInvocationID"),
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"raw EXEC=1 did not select guest lane zero");
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Check(Common::ContainsStr(source, "OpBranchConditional"),
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"vertex export lost its per-invocation EXEC guard");
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}
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@@ -10049,8 +10083,8 @@ void TestNewShaderRecompilerPerInvocationMasksWithoutMirrors() {
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Check(
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!Common::ContainsStr(source, "OpGroupNonUniformBallot"),
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"per-invocation VCC producer still materialized a shared subgroup mask");
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Check(!Common::ContainsStr(source, "OpLoad %uint %gl_SubgroupInvocationID"),
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"per-invocation BFM EXEC prefix still selected native subgroup lanes");
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Check(Common::ContainsStr(source, "OpLoad %uint %gl_SubgroupInvocationID"),
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"BFM EXEC prefix did not select the four requested guest lanes");
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Check(!Common::ContainsStr(source, "%vcc_lo") &&
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!Common::ContainsStr(source, "%vcc_hi"),
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"per-invocation comparison retained VCC register mirrors");
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@@ -10067,8 +10101,8 @@ void TestNewShaderRecompilerPerInvocationMasksWithoutMirrors() {
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Check(Common::ContainsStr(wqm_source, "OpCapability GroupNonUniformBallot") &&
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Common::ContainsStr(wqm_source, "OpGroupNonUniformBallot"),
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"per-invocation scalar WQM omitted its subgroup ballot capability");
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Check(SpirvInstructionOpcodeCount(result.spirv, 132u) == 2u,
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"wave64 WQM did not compact exactly two ballot words");
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Check(SpirvInstructionOpcodeCount(result.spirv, 132u) == 1u,
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"wave64 WQM did not expand its scalar word pair together");
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auto wave32_options = options;
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wave32_options.wave_size = 32u;
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@@ -11352,9 +11386,9 @@ void TestComputeLdsAllocationIdentity() {
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"compute pipeline identity omitted the LDS allocation");
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auto split_wave = lds_896;
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split_wave.needs_lds_barriers = true;
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split_wave.host_subgroup_size = 32;
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Check(MakeStageStaticKey(lds_896) != MakeStageStaticKey(split_wave),
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"compute shader identity omitted split-wave LDS synchronization");
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"compute shader identity omitted the host subgroup size");
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auto tg_size_disabled = lds_896;
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auto tg_size_enabled = lds_896;
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@@ -11418,135 +11452,6 @@ void TestComputeLdsAllocationIdentity() {
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CheckSpirvBinaryValidates(append_result.spirv);
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}
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void TestWave64LdsSynchronization() {
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const uint32_t shader[] = {
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EncodeDs0(0x0d), // ds_write_b32 v0, v1
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EncodeDs1(0, 1, 0),
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EncodeSopp(0x01),
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};
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const auto compile = [&](bool needs_lds_barriers, uint32_t wave_size,
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uint32_t threads) {
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ShaderComputeInputInfo input_info{};
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input_info.lds_size_dwords = 128;
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input_info.needs_lds_barriers = needs_lds_barriers;
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input_info.threads_num[0] = threads;
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input_info.threads_num[1] = 1;
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input_info.threads_num[2] = 1;
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auto options = MakeCompileOptions(ShaderType::Compute);
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options.wave_size = wave_size;
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options.input_info.compute = &input_info;
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auto result = RecompileForTest(shader, options);
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CheckSpirvBinaryValidates(result.spirv);
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return result;
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};
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const auto native_wave64 = compile(false, 64, 64);
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Check(!SpirvContainsOpcode(native_wave64.spirv, 224),
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"native wave64 shader gained a synthetic workgroup barrier");
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const auto split_wave64 = compile(true, 64, 64);
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Check(SpirvContainsOpcode(split_wave64.spirv, 224),
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"split wave64 LDS shader omitted workgroup synchronization");
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const auto split_wave32 = compile(true, 32, 64);
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Check(!SpirvContainsOpcode(split_wave32.spirv, 224),
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"wave32 shader gained wave64 synchronization");
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const auto larger_workgroup = compile(true, 64, 128);
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Check(!SpirvContainsOpcode(larger_workgroup.spirv, 224),
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"multi-wave workgroup gained unsupported synthetic synchronization");
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}
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void TestSharedMemoryBarrierSafety() {
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using namespace ShaderRecompiler::IR;
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const auto make_program = [](size_t block_count) {
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Program program;
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program.memory_info.push_back({.kind = ResourceKind::Lds});
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for (size_t index = 0; index < block_count; index++) {
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program.block_storage.push_back(std::make_unique<Block>());
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program.blocks.push_back(program.block_storage.back().get());
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program.block_info.emplace_back();
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program.block_info.back().id = static_cast<uint32_t>(index);
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}
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return program;
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};
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const auto append_write = [](Block& block) {
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auto& inst = block.AppendNewInst(
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ValueOpcode::WriteSharedU32,
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{Value(0u), Value(1u), Value(true)});
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inst.SetFlags(MemoryFlags{.index = 0});
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};
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const auto append_read = [](Block& block) {
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auto& inst = block.AppendNewInst(ValueOpcode::LoadSharedU32,
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{Value(0u), Value(true)});
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inst.SetFlags(MemoryFlags{.index = 0});
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};
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const auto count_barriers = [](const Block& block) {
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return std::ranges::count_if(block, [](const Inst& inst) {
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return inst.GetOpcode() == ValueOpcode::Barrier;
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});
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};
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const auto divergent_condition = [](Program& program, size_t block) {
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IREmitter ir(program.blocks[block]);
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const auto local_id = U32(ir.Emit(
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ValueOpcode::GetBuiltin,
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{Value(static_cast<uint32_t>(StageInputKind::LocalInvocationId)),
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Value(0u)}));
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return ir.INotEqual(local_id, U32(Value(0u)));
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};
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ShaderComputeInputInfo compute_info{};
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compute_info.needs_lds_barriers = true;
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compute_info.lds_size_dwords = 128;
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compute_info.threads_num[0] = 64;
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compute_info.threads_num[1] = 1;
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compute_info.threads_num[2] = 1;
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auto phases = make_program(1);
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append_write(*phases.blocks[0]);
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append_read(*phases.blocks[0]);
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const auto phase_stats = InsertSharedMemoryBarriers(phases, 64u, compute_info);
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std::vector<ValueOpcode> phase_opcodes;
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for (const auto& inst : *phases.blocks[0]) {
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phase_opcodes.push_back(inst.GetOpcode());
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}
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Check(phase_stats.inserted_barriers == 2 && phase_opcodes.size() == 4 &&
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phase_opcodes[0] == ValueOpcode::WriteSharedU32 &&
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phase_opcodes[1] == ValueOpcode::Barrier &&
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phase_opcodes[2] == ValueOpcode::LoadSharedU32 &&
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phase_opcodes[3] == ValueOpcode::Barrier,
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"LDS write/read phases were not separated by a barrier");
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auto selection = make_program(3);
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selection.block_info[0].terminator.kind =
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ShaderRecompiler::CFG::TerminatorKind::ConditionalBranch;
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selection.block_info[0].terminator.merge_block = 2;
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selection.block_info[0].condition = divergent_condition(selection, 0);
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append_write(*selection.blocks[1]);
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append_read(*selection.blocks[2]);
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const auto selection_stats =
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InsertSharedMemoryBarriers(selection, 64u, compute_info);
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Check(selection_stats.inserted_barriers == 2 &&
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count_barriers(*selection.blocks[1]) == 0 &&
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selection.blocks[2]->begin()->GetOpcode() ==
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ValueOpcode::Barrier,
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"workgroup barrier was placed inside divergent selection flow");
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auto loop = make_program(1);
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loop.block_info[0].terminator.kind =
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ShaderRecompiler::CFG::TerminatorKind::ConditionalBranch;
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loop.block_info[0].condition = divergent_condition(loop, 0);
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append_write(*loop.blocks[0]);
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append_read(*loop.blocks[0]);
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const auto loop_stats = InsertSharedMemoryBarriers(loop, 64u, compute_info);
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Check(loop_stats.inserted_barriers == 0 &&
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count_barriers(*loop.blocks[0]) == 0,
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"workgroup barrier was inserted into divergent loop control");
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}
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void TestPixelProgramCacheBindingIdentity() {
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const uint32_t shader_01[] = {0xbf810000u};
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const uint32_t shader_10[] = {0xbf810000u};
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@@ -11914,8 +11819,8 @@ void TestNewShaderRecompilerSpirvSizeBaselines() {
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.conditional_branches = 1,
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.ballots = 1},
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ShaderType::Vertex);
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Check(Common::ContainsStr(wqm_result.ir_dump, "WqmMask"),
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"WQM size fixture no longer reaches per-invocation WqmMask IR");
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Check(Common::ContainsStr(wqm_result.ir_dump, "WqmU64"),
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"WQM size fixture no longer reaches scalar mask expansion");
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const uint32_t dispatcher[] = {
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EncodeSopp(0x05, 2), // entry -> B, fallthrough A
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@@ -12028,6 +11933,7 @@ int main() {
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TestNewShaderRecompilerPixelImageSampleLodSelection();
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TestNewShaderRecompilerBranchConditionForms();
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TestNewShaderRecompilerSetpcBranch();
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TestFusedShaderHandoffPreservesRegisters();
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TestNewShaderRecompilerSetpcJumpTable();
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TestNewShaderRecompilerPrunesUnreachableSetpcMetadata();
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TestNewShaderRecompilerSetpcDwordJumpTable();
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@@ -12036,7 +11942,7 @@ int main() {
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TestFinalSsaRejectsRegisterStatePseudos();
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#endif
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TestValuePhiValidation();
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TestWqmMaskSignatureAndU64ShiftConstantPropagation();
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TestU64ShiftConstantPropagation();
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#if KYTY_PLATFORM != KYTY_PLATFORM_WINDOWS
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TestNativeWideValueValidation();
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#endif
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@@ -12064,8 +11970,6 @@ int main() {
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TestGraphicsCreateInterpolantMapping();
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TestNewShaderRecompilerPixelPipelineEntry();
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TestComputeLdsAllocationIdentity();
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TestWave64LdsSynchronization();
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TestSharedMemoryBarrierSafety();
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TestPixelProgramCacheBindingIdentity();
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TestGraphicsPushConstantPlacement();
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TestNewShaderRecompilerUnsupportedMemoryDecode();
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