mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
Fix wave64 LDS synchronization on subgroup32 hosts
This commit is contained in:
@@ -1019,8 +1019,7 @@ void CreatePipelineInternal(GraphicContext& graphics, PipelineCache::ComputePipe
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comp_shader_stage_info.pSpecializationInfo = nullptr;
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EXIT_IF(!input_info.stage);
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const auto wave_size = input_info.stage.program->wave_size;
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if (graphics.subgroup_size_control_enabled &&
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(graphics.required_subgroup_size_stages & vk::ShaderStageFlagBits::eCompute) &&
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if (graphics.compute_subgroup_size_control_enabled &&
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wave_size >= graphics.min_subgroup_size && wave_size <= graphics.max_subgroup_size) {
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comp_subgroup_size.sType =
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vk::StructureType::ePipelineShaderStageRequiredSubgroupSizeCreateInfo;
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@@ -210,7 +210,9 @@ void RenderExecutor::DispatchDirect(uint64_t submit_id, RenderCommandBuffer& buf
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ShaderComputeInputInfo input_info {};
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std::span<const uint32_t> cs_shader;
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if (!ShaderCompileInfoCS(cs_regs, sh_regs, input_info, cs_shader)) {
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if (!ShaderCompileInfoCS(cs_regs, sh_regs,
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!m_context.GetGraphics().compute_wave64_supported, input_info,
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cs_shader)) {
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EXIT("ShaderCompileInfoCS failed for dispatch with CS shader 0x%016" PRIx64 "\n",
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cs_regs.cs_regs.data_addr);
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}
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@@ -25,7 +25,8 @@ struct VulkanInstance {
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VmaAllocator allocator = nullptr;
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bool memory_budget_ext_enabled = false;
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bool rt_extensions_enabled = false;
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bool subgroup_size_control_enabled = false;
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bool compute_subgroup_size_control_enabled = false;
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bool compute_wave64_supported = false;
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bool sample_rate_shading_enabled = false;
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uint32_t subgroup_size = 0;
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uint32_t min_subgroup_size = 0;
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@@ -493,14 +493,19 @@ static void VulkanInitSubgroupSizeControl(vk::PhysicalDevice physical_device,
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graphics.min_subgroup_size = subgroup_size_control.minSubgroupSize;
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graphics.max_subgroup_size = subgroup_size_control.maxSubgroupSize;
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graphics.required_subgroup_size_stages = subgroup_size_control.requiredSubgroupSizeStages;
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graphics.subgroup_size_control_enabled = features13.subgroupSizeControl == VK_TRUE &&
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subgroup_size_control.minSubgroupSize <= 64 &&
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subgroup_size_control.maxSubgroupSize >= 64;
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graphics.compute_subgroup_size_control_enabled =
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features13.subgroupSizeControl == VK_TRUE &&
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(graphics.required_subgroup_size_stages & vk::ShaderStageFlagBits::eCompute) &&
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subgroup_size_control.minSubgroupSize <= 64 &&
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subgroup_size_control.maxSubgroupSize >= 64;
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graphics.compute_wave64_supported =
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graphics.subgroup_size == 64u || graphics.compute_subgroup_size_control_enabled;
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LOGF("Vulkan subgroup: default=%u min=%u max=%u stages=0x%08x size_control=%s\n",
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LOGF("Vulkan subgroup: default=%u min=%u max=%u stages=0x%08x size_control=%s wave64=%s\n",
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graphics.subgroup_size, graphics.min_subgroup_size, graphics.max_subgroup_size,
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static_cast<vk::ShaderStageFlags::MaskType>(graphics.required_subgroup_size_stages),
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graphics.subgroup_size_control_enabled ? "true" : "false");
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graphics.compute_subgroup_size_control_enabled ? "true" : "false",
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graphics.compute_wave64_supported ? "true" : "false");
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}
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static vk::Device VulkanCreateDevice(vk::PhysicalDevice physical_device, const VulkanExtensions& r,
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@@ -645,8 +650,9 @@ static vk::Device VulkanCreateDevice(vk::PhysicalDevice physical_device, const V
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robustness2.nullDescriptor = supported_robustness2.nullDescriptor;
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}
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const bool subgroup_size_control_enabled = graphics.subgroup_size_control_enabled &&
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supported_features13.subgroupSizeControl == VK_TRUE;
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const bool subgroup_size_control_enabled =
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graphics.compute_subgroup_size_control_enabled &&
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supported_features13.subgroupSizeControl == VK_TRUE;
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auto features13 = required_features13;
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#if defined(__APPLE__)
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@@ -15,6 +15,7 @@
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#include "graphics/shader/recompiler/ir/passes/ResourceMaterialization.h"
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#include "graphics/shader/recompiler/ir/passes/ResourceTracking.h"
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#include "graphics/shader/recompiler/ir/passes/ShaderInfoCollection.h"
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#include "graphics/shader/recompiler/ir/passes/SharedMemoryBarrier.h"
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#include "graphics/shader/recompiler/ir/passes/SrtWalker.h"
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#include "graphics/shader/recompiler/ir/passes/SsaRewrite.h"
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@@ -741,6 +742,14 @@ bool TryRecompile(std::span<const uint32_t> code, const CompileOptions& options,
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IR::RemoveIdentities(ir.values->blocks);
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IR::EliminateDeadCode(ir.values->blocks);
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}
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if (options.stage == ShaderType::Compute) {
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const auto lds_barriers =
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IR::InsertSharedMemoryBarriers(*ir.values, ir.wave_size, *compute);
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if (lds_barriers.inserted_barriers != 0) {
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LOGF("%s wave64 LDS synchronization: barriers=%" PRIu32 "\n", GetDumpLabel(options),
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lds_barriers.inserted_barriers);
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}
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}
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std::string srt_error;
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if (!IR::BuildSrtPlan(ir, &srt_error)) {
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LOGF("%s SRT planning failed: %s\n", GetDumpLabel(options), srt_error.c_str());
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@@ -0,0 +1,153 @@
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#include "graphics/shader/recompiler/ir/passes/SharedMemoryBarrier.h"
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#include "graphics/shader/recompiler/ir/ValueProgram.h"
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#include <algorithm>
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#include <queue>
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#include <unordered_map>
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#include <unordered_set>
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namespace Libs::Graphics::ShaderRecompiler::IR {
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namespace {
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enum class LdsPhase { None, Read, Write };
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LdsPhase GetLdsPhase(const ValueProgram& program, const Inst& inst) {
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const auto access = SharedAccessOf(inst.GetOpcode());
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if (access != SharedAccess::Read && access != SharedAccess::Write) {
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return LdsPhase::None;
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}
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const auto index = inst.Flags<MemoryFlags>().index;
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if (index >= program.memory_info.size() ||
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program.memory_info[index].kind != ResourceKind::Lds) {
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return LdsPhase::None;
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}
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return access == SharedAccess::Read ? LdsPhase::Read : LdsPhase::Write;
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}
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bool DependsOnInvocation(Value value) {
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std::queue<Value> queue;
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std::unordered_set<Inst*> visited;
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queue.push(value);
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while (!queue.empty()) {
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value = queue.front().Resolve();
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queue.pop();
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auto* inst = value.TryInstruction();
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if (inst == nullptr || !visited.insert(inst).second) {
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continue;
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}
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if (inst->GetOpcode() == ValueOpcode::LaneId) {
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return true;
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}
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if (inst->GetOpcode() == ValueOpcode::GetBuiltin) {
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const auto kind = static_cast<StageInputKind>(inst->Arg(0).U32());
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if (kind == StageInputKind::LocalInvocationId ||
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kind == StageInputKind::LocalInvocationIndex ||
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kind == StageInputKind::GlobalInvocationId) {
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return true;
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}
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}
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for (size_t index = 0; index < inst->NumArgs(); index++) {
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queue.push(inst->Arg(index));
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}
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}
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return false;
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}
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uint32_t InsertBarrier(Block& block, Block::iterator position) {
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block.PrependNewInst(position, ValueOpcode::Barrier);
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return 1;
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}
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uint32_t InsertBlockBarriers(ValueProgram& program, Block& block) {
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uint32_t inserted = 0;
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LdsPhase phase = LdsPhase::None;
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for (auto inst = block.begin(); inst != block.end(); ++inst) {
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if (inst->GetOpcode() == ValueOpcode::Barrier) {
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phase = LdsPhase::None;
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continue;
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}
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const auto next = GetLdsPhase(program, *inst);
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if (next == LdsPhase::None) {
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continue;
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}
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if (phase != LdsPhase::None && phase != next) {
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inserted += InsertBarrier(block, inst);
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}
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phase = next;
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}
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if (phase != LdsPhase::None) {
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block.AppendNewInst(ValueOpcode::Barrier);
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inserted++;
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}
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return inserted;
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}
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uint32_t InsertMergeBarrier(Block& block) {
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auto position = std::ranges::find_if(
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block, [](const Inst& inst) { return inst.GetOpcode() != ValueOpcode::Phi; });
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if (position != block.end() && position->GetOpcode() == ValueOpcode::Barrier) {
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return 0;
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}
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return InsertBarrier(block, position);
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}
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} // namespace
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SharedMemoryBarrierStats InsertSharedMemoryBarriers(ValueProgram& program, uint32_t wave_size,
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const ShaderComputeInputInfo& compute_info) {
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SharedMemoryBarrierStats stats;
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const auto threadgroup_size = compute_info.threads_num[0] * compute_info.threads_num[1] *
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compute_info.threads_num[2];
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if (wave_size != 64u || !compute_info.needs_lds_barriers ||
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compute_info.lds_size_dwords == 0u || threadgroup_size != 64u) {
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return stats;
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}
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if (program.blocks.size() != program.block_info.size()) {
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return stats;
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}
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for (const auto& info: program.block_info) {
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if (info.terminator.kind == CFG::TerminatorKind::ConditionalBranch &&
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info.terminator.merge_block == UINT32_MAX && DependsOnInvocation(info.condition)) {
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return stats;
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}
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}
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std::unordered_map<uint32_t, Block*> blocks;
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for (size_t index = 0; index < program.blocks.size(); index++) {
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blocks.emplace(program.block_info[index].id, program.blocks[index]);
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}
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uint32_t divergence_depth = 0;
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std::unordered_map<uint32_t, uint32_t> divergence_ends;
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std::unordered_set<uint32_t> synchronized_merges;
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for (size_t index = 0; index < program.blocks.size(); index++) {
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const auto id = program.block_info[index].id;
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if (const auto end = divergence_ends.find(id); end != divergence_ends.end()) {
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EXIT_IF(end->second > divergence_depth);
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divergence_depth -= end->second;
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}
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if (divergence_depth == 0) {
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stats.inserted_barriers += InsertBlockBarriers(program, *program.blocks[index]);
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}
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const auto& info = program.block_info[index];
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const auto& term = info.terminator;
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if (term.kind != CFG::TerminatorKind::ConditionalBranch || term.merge_block == UINT32_MAX ||
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!DependsOnInvocation(info.condition)) {
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continue;
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}
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if (divergence_depth == 0 && synchronized_merges.insert(term.merge_block).second) {
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const auto merge = blocks.find(term.merge_block);
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if (merge != blocks.end()) {
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stats.inserted_barriers += InsertMergeBarrier(*merge->second);
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}
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}
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divergence_depth++;
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divergence_ends[term.merge_block]++;
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}
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return stats;
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}
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} // namespace Libs::Graphics::ShaderRecompiler::IR
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@@ -0,0 +1,15 @@
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#pragma once
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#include "graphics/shader/recompiler/ir/ShaderIR.h"
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namespace Libs::Graphics::ShaderRecompiler::IR {
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struct SharedMemoryBarrierStats {
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uint32_t inserted_barriers = 0;
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};
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[[nodiscard]] SharedMemoryBarrierStats
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InsertSharedMemoryBarriers(ValueProgram& program, uint32_t wave_size,
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const ShaderComputeInputInfo& compute_info);
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} // namespace Libs::Graphics::ShaderRecompiler::IR
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@@ -1212,10 +1212,12 @@ bool ShaderCompileInfoPS(const HW::PixelShaderInfo& regs, const HW::ShaderRegist
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}
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bool ShaderCompileInfoCS(const HW::ComputeShaderInfo& regs, const HW::ShaderRegisters& sh,
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ShaderComputeInputInfo& info, std::span<const uint32_t>& spirv) {
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bool needs_lds_barriers, ShaderComputeInputInfo& info,
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std::span<const uint32_t>& spirv) {
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spirv = {};
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ShaderGetStaticInputInfoCS(regs, sh, info);
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info.needs_lds_barriers = needs_lds_barriers;
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const auto shader_hash = regs.cs_regs.data_addr;
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const auto program_id = ShaderGetIdCS(regs, info, false);
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const auto key = MakeShaderStageProgramKey(ShaderType::Compute, shader_hash, program_id);
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@@ -1344,9 +1346,11 @@ void ShaderDbgDumpInputInfo(const ShaderComputeInputInfo& info) {
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"\t thread_ids_num = %d\n"
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"\t wave_size = %u\n"
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"\t lds_size_dwords = %u\n"
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"\t needs_lds_barriers = %s\n"
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"\t threads_num = {%u, %u, %u}\n"
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"\t tg_size_en = %s\n",
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info.workgroup_register, info.thread_ids_num, info.wave_size, info.lds_size_dwords,
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info.needs_lds_barriers ? "true" : "false",
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info.threads_num[0], info.threads_num[1], info.threads_num[2],
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info.tg_size_en ? "true" : "false");
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LOGF("\t threadgroup_id = {%s, %s, %s}\n", info.group_id[0] ? "true" : "false",
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@@ -1742,6 +1746,7 @@ ShaderId ShaderGetIdCS(const HW::ComputeShaderInfo& regs, const ShaderComputeInp
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ret.ids.push_back(input_info.thread_ids_num);
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ret.ids.push_back(input_info.lds_size_dwords);
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ret.ids.push_back(input_info.scratch_size_dwords);
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ret.ids.push_back(static_cast<uint32_t>(input_info.needs_lds_barriers));
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for (int i = 0; i < 3; i++) {
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ret.ids.push_back(input_info.threads_num[i]);
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@@ -107,6 +107,7 @@ struct ShaderComputeInputInfo {
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uint32_t scratch_size_dwords = 0;
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bool group_id[3] = {false, false, false};
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bool dispatch_thread_dimensions = false;
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bool needs_lds_barriers = false;
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uint32_t wave_size = 64;
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int thread_ids_num = 0;
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int workgroup_register = 0;
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@@ -268,7 +269,8 @@ bool ShaderCompileInfoPS(const HW::PixelShaderInfo& regs, const HW::ShaderRegist
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std::span<const Prospero::ColorComponentMapping, 8> target_export_mapping,
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ShaderPixelInputInfo& input_info, std::span<const uint32_t>& spirv);
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bool ShaderCompileInfoCS(const HW::ComputeShaderInfo& regs, const HW::ShaderRegisters& sh,
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ShaderComputeInputInfo& input_info, std::span<const uint32_t>& spirv);
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bool needs_lds_barriers, ShaderComputeInputInfo& input_info,
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std::span<const uint32_t>& spirv);
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bool ShaderCompileSpirvVS(const HW::VertexShaderInfo& regs, const HW::ShaderRegisters& sh,
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ShaderVertexInputInfo& input_info, std::vector<uint32_t>& spirv);
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bool ShaderCompileSpirvPS(const HW::PixelShaderInfo& regs, const HW::ShaderRegisters& sh,
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