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shader: implement RDNA2 subrev borrow

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This commit is contained in:
nmzik
2026-08-15 04:47:25 +02:00
parent 9c316e6988
commit 4a7bc55afa
8 changed files with 128 additions and 21 deletions
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src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.cpp
+1
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@@ -671,6 +671,7 @@ std::string OpcodeToString(Opcode opcode) {
case Opcode::VMadMixhiF16: return "v_mad_mixhi_f16";
case Opcode::VAddNcU32: return "v_add_nc_u32";
case Opcode::VAddcU32: return "v_addc_u32";
case Opcode::VSubrevCoCiU32: return "v_subrev_co_ci_u32";
case Opcode::VSubNcU32: return "v_sub_nc_u32";
case Opcode::VSubrevNcU32: return "v_subrev_nc_u32";
case Opcode::VAddNcU16: return "v_add_nc_u16";
src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.h
+1
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@@ -269,6 +269,7 @@ enum class Opcode {
VMadMixhiF16,
VAddNcU32,
VAddcU32,
VSubrevCoCiU32,
VSubNcU32,
VSubrevNcU32,
VAddNcU16,
src/graphics/shader/recompiler/frontend/decode/VectorAluOps.cpp
+22 -18
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@@ -63,6 +63,7 @@ constexpr Vop2OpcodeInfo VOP2_OPS[] = {
{0x24u, Opcode::VMbcntHiU32B32},
{0x25u, Opcode::VAddNcU32, Vop2SdwaProfile::IntegerFullDestination},
{0x28u, Opcode::VAddcU32},
{0x2au, Opcode::VSubrevCoCiU32},
{0x26u, Opcode::VSubNcU32, Vop2SdwaProfile::IntegerPartialDestination},
{0x27u, Opcode::VSubrevNcU32, Vop2SdwaProfile::IntegerFullDestination},
{0x2bu, Opcode::VMacF32},
@@ -967,6 +968,7 @@ bool FinalizeVop2Instruction(uint32_t pc, std::span<const uint32_t> code, uint32
inst.src_count = 3;
break;
case Opcode::VAddcU32:
case Opcode::VSubrevCoCiU32:
inst.dst2.kind = OperandKind::VccLo;
inst.src2.kind = OperandKind::VccLo;
inst.src_count = 3;
@@ -1373,9 +1375,10 @@ bool SupportsNativeVop3ResultModifiers(Opcode opcode) {
}
}
bool HasUnsupportedNativeVop3Modifiers(Opcode opcode, bool permlane, bool mad_mix, bool addc,
bool scalar_dst, uint32_t abs, uint32_t op_sel,
uint32_t clamp, uint32_t omod, uint32_t neg) {
bool HasUnsupportedNativeVop3Modifiers(Opcode opcode, bool permlane, bool mad_mix,
bool carry_in_out, bool scalar_dst, uint32_t abs,
uint32_t op_sel, uint32_t clamp, uint32_t omod,
uint32_t neg) {
const bool source_modifiers = SupportsNativeVop3SourceModifiers(opcode);
const bool result_modifiers = SupportsNativeVop3ResultModifiers(opcode);
@@ -1391,7 +1394,7 @@ bool HasUnsupportedNativeVop3Modifiers(Opcode opcode, bool permlane, bool mad_mi
if (IsNativeVop3B16BinaryOpcode(opcode)) {
return abs != 0u || clamp != 0u || omod != 0u || neg != 0u;
}
if (addc || scalar_dst) {
if (carry_in_out || scalar_dst) {
return clamp != 0u || omod != 0u || neg != 0u;
}
switch (opcode) {
@@ -1606,19 +1609,20 @@ bool DecodeVop3(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
inst.opcode = LookupVop3Opcode(opcode);
SetRawWords(inst, code, word_index, 2);
const bool addc = inst.opcode == Opcode::VAddcU32 && opcode == 0x128u;
const bool vop3b_carry_out = IsVop3BCarryOutOpcode(inst.opcode);
const bool vop3b_mad_u64 = IsVop3BMadU64Opcode(inst.opcode);
const bool vop3b_uses_sdst = addc || vop3b_carry_out || vop3b_mad_u64;
const bool mad_mix = false;
const bool f16_ternary = IsNativeVop3F16TernaryOpcode(inst.opcode);
const bool b16_binary = IsNativeVop3B16BinaryOpcode(inst.opcode);
const bool pack_b32_f16 = inst.opcode == Opcode::VPackB32F16;
const bool permlane = IsPermlaneOpcode(inst.opcode);
const bool vop3_vopc = IsVop3EncodedVopc(opcode);
const bool compare_exec = vop3_vopc && IsVopcCompareExec(inst.opcode);
const bool scalar_dst = vop3_vopc || UsesScalarDestination(inst.opcode);
const bool scalar_modifier_limits = UsesScalarDestination(inst.opcode);
const bool carry_in_out = (inst.opcode == Opcode::VAddcU32 && opcode == 0x128u) ||
(inst.opcode == Opcode::VSubrevCoCiU32 && opcode == 0x12au);
const bool vop3b_carry_out = IsVop3BCarryOutOpcode(inst.opcode);
const bool vop3b_mad_u64 = IsVop3BMadU64Opcode(inst.opcode);
const bool vop3b_uses_sdst = carry_in_out || vop3b_carry_out || vop3b_mad_u64;
const bool mad_mix = false;
const bool f16_ternary = IsNativeVop3F16TernaryOpcode(inst.opcode);
const bool b16_binary = IsNativeVop3B16BinaryOpcode(inst.opcode);
const bool pack_b32_f16 = inst.opcode == Opcode::VPackB32F16;
const bool permlane = IsPermlaneOpcode(inst.opcode);
const bool vop3_vopc = IsVop3EncodedVopc(opcode);
const bool compare_exec = vop3_vopc && IsVopcCompareExec(inst.opcode);
const bool scalar_dst = vop3_vopc || UsesScalarDestination(inst.opcode);
const bool scalar_modifier_limits = UsesScalarDestination(inst.opcode);
const bool native_source_modifiers = SupportsNativeVop3SourceModifiers(inst.opcode);
const bool native_result_modifiers = SupportsNativeVop3ResultModifiers(inst.opcode);
const bool modifiers =
@@ -1678,7 +1682,7 @@ bool DecodeVop3(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
}
return ReadLiteralOperands(code, word_index, inst, error);
}
if (addc) {
if (carry_in_out) {
if (!DecodeScalarDestination(sdst, pc, inst.dst2, error) ||
!DecodeScalarSource(src1, pc, inst.src1, error) ||
!DecodeScalarSource(src2, pc, inst.src2, error)) {
src/graphics/shader/recompiler/frontend/translate/Control.cpp
+8 -2
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@@ -74,7 +74,8 @@ bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
}
return true;
}
case IR::Opcode::ScalarSubBorrowCarryU32: {
case IR::Opcode::ScalarSubBorrowCarryU32:
case IR::Opcode::ISubBorrowCarryU32: {
const auto lhs = ReadU32(inst.src[0]);
const auto rhs = ReadU32(inst.src[1]);
const auto borrow_in = ConditionBit(inst.src[2]);
@@ -83,7 +84,12 @@ bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
const auto borrow0 = ir.UGreaterThan(rhs, lhs);
const auto borrow1 = ir.UGreaterThan(borrow_in, partial);
WriteOperand(inst.dst, result);
ir.SetScc(ir.LogicalOr(borrow0, borrow1));
const auto borrow = ir.LogicalOr(borrow0, borrow1);
if (inst.op == IR::Opcode::ScalarSubBorrowCarryU32) {
ir.SetScc(borrow);
} else {
WriteMask(inst.dst2, borrow);
}
return true;
}
case IR::Opcode::ScalarSignedAddOverflowI32:
src/graphics/shader/recompiler/frontend/translate/Translate.cpp
+1 -1
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@@ -585,7 +585,7 @@ IR::U32 Translator::ConditionBit(const IR::Operand& operand) {
if (operand.kind == IR::OperandKind::ImmediateU32) {
return IR::U32(IR::Value(operand.imm & 1u));
}
return ir.Select(ReadCondition(operand), IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u)));
return ir.Select(ReadMask(operand), IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u)));
}
IR::U1 Translator::ReadMask(const IR::Operand& operand) {