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shader: implement RDNA2 FP64 equality comparisons
Co-authored-by: Senaxx <michelbeld@gmail.com> Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com>
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@@ -40,11 +40,13 @@ void Translator::EmitInteger16Compare(const Decoder::Instruction& inst, IR::Valu
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void Translator::EmitFloatCompare(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool half, bool cmpx) {
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const auto type = IR::ArgTypeOf(opcode, 0);
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const auto lhs =
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half ? IR::Value(ReadF16AsF32(inst.src0)) : ReadOperand(inst.src0, IR::Type::F32);
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half ? IR::Value(ReadF16AsF32(inst.src0)) : ReadOperand(inst.src0, type);
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const auto rhs =
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half ? IR::Value(ReadF16AsF32(inst.src1)) : ReadOperand(inst.src1, IR::Type::F32);
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const IR::FPCompareFlags flags{.flush_input_denorms = !half && flush_f32_inputs};
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half ? IR::Value(ReadF16AsF32(inst.src1)) : ReadOperand(inst.src1, type);
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const IR::FPCompareFlags flags{
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.flush_input_denorms = !half && type == IR::Type::F32 && flush_f32_inputs};
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EmitCompareResult(inst, IR::U1(ir.Emit(opcode, {lhs, rhs}, flags)), false, cmpx);
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}
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@@ -889,6 +889,10 @@ void IncludeInstructionVectorRegisters(const Decoder::Instruction& inst, uint32_
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case Decoder::Opcode::V_MUL_F64: include_vector(inst.src1, 2u); [[fallthrough]];
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case Decoder::Opcode::V_RCP_F64: include_vector(inst.dst, 2u); [[fallthrough]];
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case Decoder::Opcode::V_CVT_F32_F64: include_vector(inst.src0, 2u); break;
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case Decoder::Opcode::V_CMP_EQ_F64:
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include_vector(inst.src0, 2u);
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include_vector(inst.src1, 2u);
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break;
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default: break;
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}
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if (inst.family == Decoder::Family::DS) {
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@@ -168,6 +168,9 @@ void Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_CMP_EQ_F32:
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EmitFloatCompare(inst, IR::ValueOpcode::FPOrdEqual32, false, false);
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return;
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case O::V_CMP_EQ_F64:
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EmitFloatCompare(inst, IR::ValueOpcode::FPOrdEqual64, false, false);
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return;
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case O::V_CMPX_EQ_F32:
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EmitFloatCompare(inst, IR::ValueOpcode::FPOrdEqual32, false, true);
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return;
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