mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 10:56:58 +02:00
shader: generate SPIR-V dispatch and marshal handler arguments
This commit is contained in:
nmzik
@@ -1,4 +1,4 @@
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#include "graphics/shader/recompiler/backend/spirv/spirvEmitterInternal.h"
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#include "graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h"
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#include <algorithm>
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@@ -426,7 +426,9 @@ uint32_t ConvertPositionToClipSpace(EmitterState& state, uint32_t position) {
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return converted;
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}
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void EmitExport(ValueEmitContext& ctx, const IR::Inst& inst) {
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} // namespace
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void EmitSetAttribute(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto& exp = ctx.Export(inst);
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const auto exec = ctx.Arg(inst, 1);
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@@ -515,179 +517,176 @@ void EmitExport(ValueEmitContext& ctx, const IR::Inst& inst) {
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});
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}
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} // namespace
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uint32_t EmitIdentity(ValueEmitContext&, uint32_t value) {
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return value;
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}
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bool EmitValueFlow(ValueEmitContext& ctx, const IR::Inst& inst) {
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void EmitVoid(ValueEmitContext&) {}
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void EmitBarrier(ValueEmitContext& ctx) {
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auto& state = ctx.state;
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const auto semantics =
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spv::MemorySemanticsAcquireReleaseMask | spv::MemorySemanticsWorkgroupMemoryMask;
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state.builder.AddFunction({spv::OpControlBarrier, ConstantU32(state, spv::ScopeWorkgroup),
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ConstantU32(state, spv::ScopeWorkgroup),
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ConstantU32(state, semantics)});
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}
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uint32_t EmitMeshDrawParameter(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto result = state.builder.AllocateId();
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const auto index = inst.Arg(0).U32();
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if (state.program.stage != ShaderType::Mesh || index >= IR::PushData::MeshDrawDwordCount) {
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ctx.Fail(inst, "invalid mesh draw parameter");
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}
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const auto pointer = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpAccessChain, TypePushConstantElementPointer(state), pointer,
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state.push_constant_variable, ConstantU32(state, 0),
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ConstantU32(state, index)});
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state.builder.AddFunction({spv::OpLoad, TypeU32(state), result, pointer});
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return result;
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}
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uint32_t EmitGetUserData(ValueEmitContext& ctx, IR::ScalarReg reg) {
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auto& state = ctx.state;
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switch (inst.GetOpcode()) {
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case IR::ValueOpcode::Identity: ctx.Define(inst, ctx.Arg(inst, 0)); return true;
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case IR::ValueOpcode::Void:
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case IR::ValueOpcode::Reference:
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case IR::ValueOpcode::ReferenceU32:
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case IR::ValueOpcode::ControlNop:
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case IR::ValueOpcode::Waitcnt:
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case IR::ValueOpcode::Sendmsg:
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case IR::ValueOpcode::TtraceData:
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case IR::ValueOpcode::InstPrefetch: return true;
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case IR::ValueOpcode::Barrier: {
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const auto semantics =
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spv::MemorySemanticsAcquireReleaseMask | spv::MemorySemanticsWorkgroupMemoryMask;
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state.builder.AddFunction(
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{spv::OpControlBarrier, ConstantU32(state, spv::ScopeWorkgroup),
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ConstantU32(state, spv::ScopeWorkgroup), ConstantU32(state, semantics)});
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return true;
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}
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case IR::ValueOpcode::MeshAllocate: EmitMeshAllocate(ctx, inst); return true;
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case IR::ValueOpcode::MeshDrawParameter: {
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const auto index = inst.Arg(0).U32();
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if (state.program.stage != ShaderType::Mesh ||
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index >= IR::PushData::MeshDrawDwordCount) {
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ctx.Fail(inst, "invalid mesh draw parameter");
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}
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const auto pointer = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpAccessChain, TypePushConstantElementPointer(state),
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pointer, state.push_constant_variable, ConstantU32(state, 0),
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ConstantU32(state, index)});
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state.builder.AddFunction({spv::OpLoad, TypeU32(state), ctx.Result(inst), pointer});
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return true;
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}
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case IR::ValueOpcode::GetUserData: {
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const auto reg = inst.Arg(0).ScalarRegister();
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uint32_t dword = 0;
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if (!UserDataDwordIndex(state, reg, dword)) {
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ctx.Define(inst, ConstantU32(state, 0));
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} else {
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ctx.Define(inst, EmitShaderDataDwordLoad(state, dword));
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}
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return true;
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}
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case IR::ValueOpcode::GetBuiltin:
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ctx.Define(inst, EmitBuiltinU32(ctx, static_cast<IR::StageInputKind>(inst.Arg(0).U32()),
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inst.Arg(1).U32()));
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return true;
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case IR::ValueOpcode::UndefU1:
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case IR::ValueOpcode::UndefU8:
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case IR::ValueOpcode::UndefU16:
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case IR::ValueOpcode::UndefU32:
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case IR::ValueOpcode::UndefU64:
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state.builder.AddFunction({spv::OpUndef, ctx.TypeId(inst.GetType()), ctx.Result(inst)});
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return true;
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case IR::ValueOpcode::DppMoveU32: {
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const auto flags = inst.Flags<IR::DppMoveFlags>();
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const auto target = EmitDppTargetLane(state, flags.control);
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const auto shuffled = ctx.Shuffle(inst, 0, target.lane);
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if (flags.fetch_inactive) {
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ctx.Define(inst, shuffled);
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return true;
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}
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const auto ballot = ctx.Ballot(inst.Arg(1));
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const auto source_active = EmitBallotLaneActiveBool(state, ballot, target.lane);
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const auto can_fetch = state.builder.AllocateId();
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state.builder.AddFunction(
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{spv::OpLogicalAnd, TypeBool(state), can_fetch, target.valid, source_active});
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ctx.Emit(inst, spv::OpSelect, IR::Type::U32,
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{can_fetch, shuffled, ConstantU32(state, 0)});
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return true;
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}
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case IR::ValueOpcode::DppUpdateU32: {
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const auto flags = inst.Flags<IR::DppMoveFlags>();
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const auto write = EmitDppWriteCondition(ctx, flags, ctx.Arg(inst, 2));
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ctx.Emit(inst, spv::OpSelect, IR::Type::U32,
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{write, ctx.Arg(inst, 0), ctx.Arg(inst, 1)});
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return true;
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}
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case IR::ValueOpcode::WqmU64:
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ctx.Define(inst, EmitWqmU64(ctx.state, ctx.Arg(inst, 0)));
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return true;
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case IR::ValueOpcode::LaneId:
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ctx.Define(inst, EmitSubgroupLocalInvocationId(state));
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return true;
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case IR::ValueOpcode::Ballot: ctx.Define(inst, ctx.Ballot(inst.Arg(0))); return true;
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case IR::ValueOpcode::ReadFirstLane: {
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const auto ballot = ctx.Ballot(inst.Arg(1));
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const auto lane = ctx.FirstLane(ballot);
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ctx.Define(inst, ctx.Shuffle(inst, 0, lane));
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return true;
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}
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case IR::ValueOpcode::ReadLane:
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ctx.Define(inst, ctx.Shuffle(inst, 0, ctx.Arg(inst, 1)));
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return true;
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case IR::ValueOpcode::WriteLane: {
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const auto hit = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpIEqual, TypeBool(state), hit,
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EmitSubgroupLocalInvocationId(state), ctx.Arg(inst, 2)});
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ctx.Emit(inst, spv::OpSelect, IR::Type::U32, {hit, ctx.Arg(inst, 1), ctx.Arg(inst, 0)});
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return true;
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}
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case IR::ValueOpcode::Permlane16U32: {
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const auto flags = inst.Flags<IR::PermlaneFlags>();
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const auto subid = EmitSubgroupLocalInvocationId(state);
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const auto row = state.builder.AllocateId();
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const auto row_value = state.builder.AllocateId();
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const auto lane = state.builder.AllocateId();
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const auto lane8 = state.builder.AllocateId();
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const auto shift = state.builder.AllocateId();
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const auto upper = state.builder.AllocateId();
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const auto selected = state.builder.AllocateId();
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const auto shifted = state.builder.AllocateId();
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const auto index = state.builder.AllocateId();
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const auto target = state.builder.AllocateId();
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), row, subid, ConstantU32(state, 0xfffffff0u)});
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if (flags.x16) {
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state.builder.AddFunction(
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{spv::OpBitwiseXor, TypeU32(state), row_value, row, ConstantU32(state, 16)});
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} else {
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state.builder.AddFunction({spv::OpCopyObject, TypeU32(state), row_value, row});
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}
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), lane, subid, ConstantU32(state, 15)});
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), lane8, lane, ConstantU32(state, 7)});
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state.builder.AddFunction(
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{spv::OpShiftLeftLogical, TypeU32(state), shift, lane8, ConstantU32(state, 2)});
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state.builder.AddFunction(
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{spv::OpUGreaterThanEqual, TypeBool(state), upper, lane, ConstantU32(state, 8)});
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state.builder.AddFunction({spv::OpSelect, TypeU32(state), selected, upper,
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ctx.Arg(inst, 2), ctx.Arg(inst, 1)});
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state.builder.AddFunction(
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{spv::OpShiftRightLogical, TypeU32(state), shifted, selected, shift});
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), index, shifted, ConstantU32(state, 15)});
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state.builder.AddFunction({spv::OpBitwiseOr, TypeU32(state), target, row_value, index});
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const auto shuffled = ctx.Shuffle(inst, 0, target);
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uint32_t result = shuffled;
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if (!flags.fetch_inactive) {
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const auto source_exec = ctx.Shuffle(inst, 3, target);
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result = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpSelect, TypeU32(state), result, source_exec,
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shuffled, ConstantU32(state, 0)});
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}
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ctx.Define(inst, result);
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return true;
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}
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case IR::ValueOpcode::GetAttribute:
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ctx.Define(inst, EmitAttribute(ctx, inst.Arg(0).U32(), inst.Arg(1).U32()));
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return true;
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case IR::ValueOpcode::GetInterpolationParameter:
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ctx.Define(inst, EmitInterpolationParameter(ctx, inst.Arg(0).U32(), inst.Arg(1).U32(),
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inst.Arg(2).U32()));
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return true;
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case IR::ValueOpcode::SetAttribute: EmitExport(ctx, inst); return true;
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case IR::ValueOpcode::GetShaderBase:
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// Guest S_GETPC values stay shader-relative in SPIR-V, matching the runtime ABI. The
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// runtime descriptor evaluator supplies the mapped shader base for host-side planning.
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ctx.Define(inst, ctx.Def(IR::Value(uint64_t {0})));
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return true;
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case IR::ValueOpcode::GetSrtResource:
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case IR::ValueOpcode::GetBufferResource:
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case IR::ValueOpcode::GetAddressResource:
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case IR::ValueOpcode::GetScratchResource:
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case IR::ValueOpcode::GetImageResource:
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case IR::ValueOpcode::GetSamplerResource:
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case IR::ValueOpcode::MakeImageAddress: return true;
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default: return false;
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uint32_t dword = 0;
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if (!UserDataDwordIndex(state, reg, dword)) {
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return ConstantU32(state, 0);
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} else {
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return EmitShaderDataDwordLoad(state, dword);
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}
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}
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uint32_t EmitGetBuiltin(ValueEmitContext& ctx, IR::Value kind, IR::Value index) {
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return EmitBuiltinU32(ctx, static_cast<IR::StageInputKind>(kind.U32()), index.U32());
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}
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uint32_t EmitUndefU1(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpUndef, ctx.TypeId(inst.GetType()), result});
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return result;
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}
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uint32_t EmitDppMoveU32(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto flags = inst.Flags<IR::DppMoveFlags>();
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const auto target = EmitDppTargetLane(state, flags.control);
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const auto shuffled = ctx.Shuffle(inst, 0, target.lane);
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if (flags.fetch_inactive) {
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return shuffled;
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}
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const auto ballot = ctx.Ballot(inst.Arg(1));
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const auto source_active = EmitBallotLaneActiveBool(state, ballot, target.lane);
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const auto can_fetch = state.builder.AllocateId();
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state.builder.AddFunction(
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{spv::OpLogicalAnd, TypeBool(state), can_fetch, target.valid, source_active});
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return EmitNative<spv::OpSelect, IR::Type::U32>(ctx, can_fetch, shuffled,
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ConstantU32(state, 0));
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}
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uint32_t EmitDppUpdateU32(ValueEmitContext& ctx, const IR::Inst& inst) {
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const auto flags = inst.Flags<IR::DppMoveFlags>();
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const auto write = EmitDppWriteCondition(ctx, flags, ctx.Arg(inst, 2));
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return EmitNative<spv::OpSelect, IR::Type::U32>(ctx, write, ctx.Arg(inst, 0), ctx.Arg(inst, 1));
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}
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uint32_t EmitWqmU64(ValueEmitContext& ctx, uint32_t value) {
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return EmitWqmU64(ctx.state, value);
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}
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uint32_t EmitLaneId(ValueEmitContext& ctx) {
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auto& state = ctx.state;
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return EmitSubgroupLocalInvocationId(state);
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}
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uint32_t EmitBallot(ValueEmitContext& ctx, IR::Value predicate) {
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return ctx.Ballot(predicate);
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}
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uint32_t EmitReadFirstLane(ValueEmitContext& ctx, const IR::Inst& inst) {
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const auto ballot = ctx.Ballot(inst.Arg(1));
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const auto lane = ctx.FirstLane(ballot);
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return ctx.Shuffle(inst, 0, lane);
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}
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uint32_t EmitReadLane(ValueEmitContext& ctx, const IR::Inst& inst) {
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return ctx.Shuffle(inst, 0, ctx.Arg(inst, 1));
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}
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uint32_t EmitWriteLane(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto hit = state.builder.AllocateId();
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state.builder.AddFunction({spv::OpIEqual, TypeBool(state), hit,
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EmitSubgroupLocalInvocationId(state), ctx.Arg(inst, 2)});
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return EmitNative<spv::OpSelect, IR::Type::U32>(ctx, hit, ctx.Arg(inst, 1), ctx.Arg(inst, 0));
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}
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uint32_t EmitPermlane16U32(ValueEmitContext& ctx, const IR::Inst& inst) {
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auto& state = ctx.state;
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const auto flags = inst.Flags<IR::PermlaneFlags>();
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const auto subid = EmitSubgroupLocalInvocationId(state);
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const auto row = state.builder.AllocateId();
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const auto row_value = state.builder.AllocateId();
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const auto lane = state.builder.AllocateId();
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const auto lane8 = state.builder.AllocateId();
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const auto shift = state.builder.AllocateId();
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const auto upper = state.builder.AllocateId();
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const auto selected = state.builder.AllocateId();
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const auto shifted = state.builder.AllocateId();
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const auto index = state.builder.AllocateId();
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const auto target = state.builder.AllocateId();
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), row, subid, ConstantU32(state, 0xfffffff0u)});
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if (flags.x16) {
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state.builder.AddFunction(
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{spv::OpBitwiseXor, TypeU32(state), row_value, row, ConstantU32(state, 16)});
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} else {
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state.builder.AddFunction({spv::OpCopyObject, TypeU32(state), row_value, row});
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}
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), lane, subid, ConstantU32(state, 15)});
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), lane8, lane, ConstantU32(state, 7)});
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state.builder.AddFunction(
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{spv::OpShiftLeftLogical, TypeU32(state), shift, lane8, ConstantU32(state, 2)});
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state.builder.AddFunction(
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{spv::OpUGreaterThanEqual, TypeBool(state), upper, lane, ConstantU32(state, 8)});
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state.builder.AddFunction(
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{spv::OpSelect, TypeU32(state), selected, upper, ctx.Arg(inst, 2), ctx.Arg(inst, 1)});
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state.builder.AddFunction({spv::OpShiftRightLogical, TypeU32(state), shifted, selected, shift});
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state.builder.AddFunction(
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{spv::OpBitwiseAnd, TypeU32(state), index, shifted, ConstantU32(state, 15)});
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state.builder.AddFunction({spv::OpBitwiseOr, TypeU32(state), target, row_value, index});
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const auto shuffled = ctx.Shuffle(inst, 0, target);
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uint32_t result = shuffled;
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if (!flags.fetch_inactive) {
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const auto source_exec = ctx.Shuffle(inst, 3, target);
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result = state.builder.AllocateId();
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state.builder.AddFunction(
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{spv::OpSelect, TypeU32(state), result, source_exec, shuffled, ConstantU32(state, 0)});
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}
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return result;
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}
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uint32_t EmitGetAttribute(ValueEmitContext& ctx, const IR::Inst& inst) {
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return EmitAttribute(ctx, inst.Arg(0).U32(), inst.Arg(1).U32());
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}
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uint32_t EmitGetInterpolationParameter(ValueEmitContext& ctx, const IR::Inst& inst) {
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return EmitInterpolationParameter(ctx, inst.Arg(0).U32(), inst.Arg(1).U32(), inst.Arg(2).U32());
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}
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uint32_t EmitGetShaderBase(ValueEmitContext& ctx) {
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// Guest S_GETPC values stay shader-relative in SPIR-V, matching the runtime ABI. The
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// runtime descriptor evaluator supplies the mapped shader base for host-side planning.
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return ctx.Def(IR::Value(uint64_t {0}));
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}
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void EmitUnreachable(ValueEmitContext& ctx, const IR::Inst& inst) {
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ctx.Fail(inst, "must be lowered before SPIR-V emission");
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Spirv::Emitter
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