From 64186404a39cd3fd67cd9e23d599ad29569dae39 Mon Sep 17 00:00:00 2001 From: nmzik Date: Thu, 22 Oct 2026 01:01:38 +0200 Subject: [PATCH] shader: load the DPP lane id once for both partial write masks --- .../shader/recompiler/backend/spirv/spirvEmitterFlow.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterFlow.cpp b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterFlow.cpp index 6d1926a40..ff542da9e 100644 --- a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterFlow.cpp +++ b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterFlow.cpp @@ -116,12 +116,13 @@ uint32_t EmitDppWriteCondition(ValueEmitContext& ctx, const IR::DppMoveFlags& fl uint32_t exec) { auto& state = ctx.state; uint32_t writable = exec; + uint32_t lane = 0; // Each mask bit enables writes to one bank (4 lanes) or row (16 lanes); a full mask enables all. const auto enable = [&](uint32_t mask, uint32_t group_shift) { if (mask == 0xfu) return; + lane = lane != 0 ? lane : EmitSubgroupLocalInvocationId(state); const auto group = EmitNative( - state, EmitSubgroupLocalInvocationId(state), ConstantU32(state, group_shift), - ConstantU32(state, 2)); + state, lane, ConstantU32(state, group_shift), ConstantU32(state, 2)); const auto bit = EmitNative( state, ConstantU32(state, mask), group, ConstantU32(state, 1)); writable = Binary(state, spv::OpLogicalAnd, TypeBool(state), writable,