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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-22 11:56:58 +02:00
shader: implement s_bfe_i32
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@@ -20,10 +20,10 @@ constexpr OpcodeMap SOP2_OPCODE_LIST[] = {
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{0x1du, Opcode::SXnorB64}, {0x1eu, Opcode::SLshlB32}, {0x1fu, Opcode::SLshlB64},
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{0x20u, Opcode::SLshrB32}, {0x21u, Opcode::SLshrB64}, {0x22u, Opcode::SAshrI32},
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{0x24u, Opcode::SBfmB32}, {0x25u, Opcode::SBfmB64}, {0x26u, Opcode::SMulI32},
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{0x27u, Opcode::SBfeU32}, {0x29u, Opcode::SBfeU64}, {0x2eu, Opcode::SLshl1AddU32},
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{0x2fu, Opcode::SLshl2AddU32}, {0x30u, Opcode::SLshl3AddU32}, {0x31u, Opcode::SLshl4AddU32},
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{0x32u, Opcode::SPackLlB32B16}, {0x33u, Opcode::SPackLhB32B16}, {0x34u, Opcode::SPackHhB32B16},
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{0x35u, Opcode::SMulHiU32},
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{0x27u, Opcode::SBfeU32}, {0x28u, Opcode::SBfeI32}, {0x29u, Opcode::SBfeU64},
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{0x2eu, Opcode::SLshl1AddU32}, {0x2fu, Opcode::SLshl2AddU32}, {0x30u, Opcode::SLshl3AddU32},
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{0x31u, Opcode::SLshl4AddU32}, {0x32u, Opcode::SPackLlB32B16}, {0x33u, Opcode::SPackLhB32B16},
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{0x34u, Opcode::SPackHhB32B16}, {0x35u, Opcode::SMulHiU32},
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};
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constexpr OpcodeMap SOP1_OPCODE_LIST[] = {
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@@ -516,6 +516,7 @@ std::string OpcodeToString(Opcode opcode) {
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case Opcode::SMulHiU32: return "s_mul_hi_u32";
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case Opcode::SMulkI32: return "s_mulk_i32";
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case Opcode::SBfeU32: return "s_bfe_u32";
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case Opcode::SBfeI32: return "s_bfe_i32";
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case Opcode::SBfeU64: return "s_bfe_u64";
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case Opcode::SBfmB32: return "s_bfm_b32";
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case Opcode::SBfmB64: return "s_bfm_b64";
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@@ -100,6 +100,7 @@ enum class Opcode {
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SMulHiU32,
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SMulkI32,
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SBfeU32,
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SBfeI32,
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SBfeU64,
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SBfmB32,
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SBfmB64,
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@@ -515,14 +515,18 @@ bool Translator::TranslateExtendedInteger(const IR::Instruction& inst) {
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result = ir.Emit(IR::ValueOpcode::ShiftLeftLogical64, {right_mask64(count), offset});
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break;
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}
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case IR::Opcode::BitFieldExtractU32: {
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case IR::Opcode::BitFieldExtractU32:
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case IR::Opcode::BitFieldExtractI32: {
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const auto source = ReadU32(inst.src[0]);
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const auto field = ReadU32(inst.src[1]);
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const auto offset = extract(field, imm(0), imm(5), false);
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const auto count =
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IR::U32(ir.Emit(IR::ValueOpcode::UMin32, {extract(field, imm(16), imm(7), false),
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ir.ISub(imm(32), offset)}));
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result = ir.Emit(IR::ValueOpcode::BitFieldUExtract, {source, offset, count});
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const auto opcode = inst.op == IR::Opcode::BitFieldExtractI32
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? IR::ValueOpcode::BitFieldSExtract
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: IR::ValueOpcode::BitFieldUExtract;
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result = ir.Emit(opcode, {source, offset, count});
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break;
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}
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case IR::Opcode::BitFieldExtractU64: {
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@@ -63,6 +63,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::SMulHiU32, Opcode::UMulHighU32},
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{Decoder::Opcode::SMulkI32, Opcode::IMulU32},
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{Decoder::Opcode::SBfeU32, Opcode::BitFieldExtractU32},
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{Decoder::Opcode::SBfeI32, Opcode::BitFieldExtractI32},
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{Decoder::Opcode::SBfeU64, Opcode::BitFieldExtractU64},
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{Decoder::Opcode::SBfmB32, Opcode::BitFieldMaskU32},
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{Decoder::Opcode::SBfmB64, Opcode::BitFieldMaskU64},
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@@ -492,6 +493,7 @@ bool ScalarResultWritesSccNonZero(Decoder::Opcode opcode) {
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case Decoder::Opcode::SLshrB32:
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case Decoder::Opcode::SAshrI32:
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case Decoder::Opcode::SBfeU32:
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case Decoder::Opcode::SBfeI32:
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case Decoder::Opcode::SAndB64:
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case Decoder::Opcode::SAndn2B64:
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case Decoder::Opcode::SNotB64:
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@@ -88,6 +88,7 @@ IR_OPCODE(FindMsbFromHighU64, General, ComposedInteger)
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IR_OPCODE(BitFieldMaskU32, General, ExtendedInteger)
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IR_OPCODE(BitFieldMaskU64, General, ExtendedInteger)
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IR_OPCODE(BitFieldExtractU32, General, ExtendedInteger)
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IR_OPCODE(BitFieldExtractI32, General, ExtendedInteger)
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IR_OPCODE(BitFieldExtractU64, General, ExtendedInteger)
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IR_OPCODE(BitFieldExtract3U32, General, ExtendedInteger)
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IR_OPCODE(BitFieldExtract3I32, General, ExtendedInteger)
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