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https://github.com/KytyPS5/KytyPS5.git
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shader: add FP64 min, max and rounding
Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com>
This commit is contained in:
nmzik
@@ -24486,6 +24486,147 @@ TestCase VectorFractF64CapturedAndEdges() {
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return test;
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}
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TestCase VectorMinMaxF64CapturedAndEdges() {
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using O = ShaderOpcode;
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// MODE.IEEE=0: select the numeric operand, or the second NaN unchanged.
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constexpr uint64_t positive_zero = 0, negative_zero = 0x8000000000000000ull;
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constexpr uint64_t one = 0x3ff0000000000000ull, minus_two = 0xc000000000000000ull;
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constexpr uint64_t qnan = 0x7ff8123456789abcull, snan = 0xfff0000000000042ull;
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constexpr uint64_t infinity = 0x7ff0000000000000ull;
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constexpr std::array<std::array<uint64_t, 4>, 20> cases{{
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{one, minus_two, minus_two, one}, {minus_two, one, minus_two, one},
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{one, one, one, one},
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{positive_zero, negative_zero, negative_zero, positive_zero},
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{negative_zero, positive_zero, negative_zero, positive_zero},
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{negative_zero, negative_zero, negative_zero, negative_zero},
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{positive_zero, positive_zero, positive_zero, positive_zero},
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{qnan, one, one, one}, {one, qnan, one, one},
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{snan, minus_two, minus_two, minus_two}, {minus_two, snan, minus_two, minus_two},
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{qnan, snan, snan, snan}, {snan, qnan, qnan, qnan},
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{infinity, one, one, infinity},
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{infinity | negative_zero, one, infinity | negative_zero, one},
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{0x3fe0000000000000ull, one, 0x3fe0000000000000ull, one},
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{1, negative_zero | 1, negative_zero | 1, 1}, {1, 0, 0, 1},
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{1, 2, 1, 2}, {2, 1, 1, 2}}};
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TestCase test;
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test.name = "VectorMinMaxF64CapturedAndEdges";
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for (const auto &item : cases) {
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for (u32 source = 0; source < 2; source++) {
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test.initial.insert(test.initial.end(), {u32(item[source]), u32(item[source] >> 32)});
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}
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}
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test.expected = test.initial;
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const auto store_pair = [&](u32 reg, uint64_t bits) {
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AppendStoreVgpr(&test.code, reg, static_cast<u32>(test.expected.size()));
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AppendStoreVgpr(&test.code, reg + 1, static_cast<u32>(test.expected.size() + 1));
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test.expected.insert(test.expected.end(), {u32(bits), u32(bits >> 32)});
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};
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for (u32 i = 0; i < cases.size(); i++) {
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for (u32 word = 0; word < 4; word++) {
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AppendVMovU32(&test.code, 30, (i * 4 + word) * 4);
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AppendBufferLoadDword(&test.code, 2 + word, 30);
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}
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AppendVop3(&test.code, 0x166, 7, Vgpr(2), Vgpr(4));
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store_pair(7, cases[i][2]);
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AppendVop3(&test.code, 0x167, 9, Vgpr(2), Vgpr(4));
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store_pair(9, cases[i][3]);
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// CS daced64c72398e80 PCs 0x10c/0x11c clamp the pair to [0, 1].
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test.code.insert(test.code.end(), {0xd5670006u, 0x00020480u,
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0xd5660006u, 0x00020cf2u});
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const auto source = std::bit_cast<double>(cases[i][0]);
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uint64_t clamped = 0;
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if (source > 0) clamped = source < 1 ? cases[i][0] : one;
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store_pair(6, clamped);
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}
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AppendSMovLiteral(&test.code, 8, 0);
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AppendSMovLiteral(&test.code, 9, u32(minus_two >> 32));
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// Scalar source and odd destination pairs; ABS must precede NEG.
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AppendVop3(&test.code, 0x166, 1, 8, 243, 0, 1, 0, false, 0, 1);
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store_pair(1, minus_two);
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AppendVop3(&test.code, 0x167, 1, 8, 243, 0, 1, 0, false, 0, 1);
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store_pair(1, 0xbff0000000000000ull);
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test.code.push_back(EncodeSop1(0x04, 12, 126));
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test.code.push_back(EncodeSop1(0x04, 126, InlineU32(0)));
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AppendVop3(&test.code, 0x166, 1, 242, 242);
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AppendVop3(&test.code, 0x167, 1, 242, 242);
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test.code.push_back(EncodeSop1(0x04, 126, 12));
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store_pair(1, 0xbff0000000000000ull);
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AppendEnd(&test.code);
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test.initial.resize(test.expected.size());
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test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::S_MOV_B64, O::BUFFER_LOAD_DWORD,
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O::V_MIN_F64, O::V_MAX_F64, O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpCapability Float64", "OpTypeFloat 64",
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"SignedZeroInfNanPreserve 64"};
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return test;
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}
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TestCase VectorRoundF64EdgesAndModifiers() {
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using O = ShaderOpcode;
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constexpr std::array<uint64_t, 14> sources{
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0x400a000000000000ull, 0xbff4000000000000ull,
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0x3fd0000000000000ull, 0xbfd0000000000000ull,
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0, 0x8000000000000000ull, 0x4330000000000001ull, 0xc330000000000001ull,
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0x7ff0000000000000ull, 0xfff0000000000000ull,
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0xfff8123456789abcull, 0x7ff0000000000001ull, 1, 0x8000000000000001ull};
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TestCase test;
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test.name = "VectorRoundF64EdgesAndModifiers";
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for (const auto bits : sources) {
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test.initial.insert(test.initial.end(), {u32(bits), u32(bits >> 32)});
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}
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test.expected = test.initial;
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const auto rounded = [](u32 opcode, double value) {
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switch (opcode) {
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case 0x17: return std::trunc(value);
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case 0x18: return std::ceil(value);
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case 0x1a: return std::floor(value);
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default: std::abort();
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}
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};
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const auto store_pair = [&](u32 reg, uint64_t bits) {
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AppendStoreVgpr(&test.code, reg, static_cast<u32>(test.expected.size()));
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AppendStoreVgpr(&test.code, reg + 1, static_cast<u32>(test.expected.size() + 1));
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test.expected.insert(test.expected.end(), {u32(bits), u32(bits >> 32)});
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};
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for (const u32 opcode : {0x17u, 0x18u, 0x1au}) {
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for (u32 i = 0; i < sources.size(); i++) {
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for (u32 word = 0; word < 2; word++) {
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AppendVMovU32(&test.code, 30, (i * 2 + word) * 4);
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AppendBufferLoadDword(&test.code, 2 + word, 30);
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}
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test.code.push_back(EncodeVop1(opcode, 5, Vgpr(2)));
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AppendVop3(&test.code, 0x180 + opcode, 7, Vgpr(2), 0);
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const auto value = std::bit_cast<double>(sources[i]);
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for (const u32 reg : {5u, 7u}) {
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if (std::isnan(value)) {
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// IEEE=false does not promise a particular NaN payload or quiet bit.
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test.code.push_back(EncodeVopc(0x22, Vgpr(reg), reg));
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AppendStoreSgprPair(&test.code, 106, static_cast<u32>(test.expected.size()));
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test.expected.insert(test.expected.end(), {0, 0});
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} else {
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store_pair(reg, std::bit_cast<uint64_t>(rounded(opcode, value)));
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}
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}
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}
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AppendSMovLiteral(&test.code, 8, 0);
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AppendSMovLiteral(&test.code, 9, 0xbff40000u);
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AppendVop3(&test.code, 0x180 + opcode, 1, 8, 0, 0, 1, 0, false, 0, 1);
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const auto expected = std::bit_cast<uint64_t>(rounded(opcode, -1.25));
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store_pair(1, expected);
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test.code.push_back(EncodeSop1(0x04, 12, 126));
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test.code.push_back(EncodeSop1(0x04, 126, InlineU32(0)));
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test.code.push_back(EncodeVop1(opcode, 1, 242));
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test.code.push_back(EncodeSop1(0x04, 126, 12));
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store_pair(1, expected);
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}
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AppendEnd(&test.code);
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test.initial.resize(test.expected.size());
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test.opcodes = {O::V_MOV_B32, O::S_MOV_B32, O::S_MOV_B64, O::BUFFER_LOAD_DWORD,
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O::V_TRUNC_F64, O::V_CEIL_F64, O::V_FLOOR_F64, O::V_CMP_EQ_F64,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpCapability Float64", "OpTypeFloat 64", "Trunc", "Ceil", "Floor"};
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return test;
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}
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TestCase VectorFractF64CapturedChainRuntimeExec() {
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using O = ShaderOpcode;
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TestCase test;
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@@ -34023,6 +34164,8 @@ std::vector<TestCase> MakeCases() {
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cases.push_back(VectorCompare64WaveMasks(64, true));
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AddCase(VectorF64CapturedScreenSpaceShadows);
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AddCase(VectorFractF64CapturedAndEdges);
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AddCase(VectorMinMaxF64CapturedAndEdges);
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AddCase(VectorRoundF64EdgesAndModifiers);
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AddCase(VectorFractF64CapturedChainRuntimeExec);
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AddCase(VectorF64ModesModifiersAndExec);
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AddCase(VectorF64WideningConversions);
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@@ -39371,6 +39514,8 @@ int main(int argc, char **argv) {
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RunCase(&vulkan, VectorCompare64WaveMasks(64));
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RunCase(&vulkan, VectorF64CapturedScreenSpaceShadows());
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RunCase(&vulkan, VectorFractF64CapturedAndEdges());
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RunCase(&vulkan, VectorMinMaxF64CapturedAndEdges());
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RunCase(&vulkan, VectorRoundF64EdgesAndModifiers());
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RunCase(&vulkan, VectorFractF64CapturedChainRuntimeExec());
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RunCase(&vulkan, VectorF64ModesModifiersAndExec());
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return 0;
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@@ -3600,6 +3600,53 @@ void TestNewShaderRecompilerCapturedFractF64() {
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}
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}
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void TestNewShaderRecompilerF64AluEncodings() {
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using namespace ShaderRecompiler::Decoder;
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for (const bool maximum : {false, true}) {
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const std::array<uint32_t, 2> captured = maximum
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? std::array<uint32_t, 2>{0xd5670006u, 0x00020480u}
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: std::array<uint32_t, 2>{0xd5660006u, 0x00020cf2u};
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Instruction decoded;
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DecodeInstruction(captured, 0, decoded);
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Check(decoded.family == Family::VOP3 &&
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decoded.opcode == (maximum ? Opcode::V_MAX_F64 : Opcode::V_MIN_F64) &&
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decoded.opcode_id == (maximum ? 0x167u : 0x166u) && decoded.word_count == 2 &&
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decoded.dst.kind == OperandKind::Vgpr && decoded.dst.reg == 6 &&
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decoded.src0.kind == (maximum ? OperandKind::IntegerInlineConstant
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: OperandKind::FloatInlineConstant) &&
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decoded.src0.value == (maximum ? 0u : 0x3f800000u) &&
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decoded.src1.kind == OperandKind::Vgpr && decoded.src1.reg == (maximum ? 2u : 6u) &&
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!decoded.src0.absolute && !decoded.src0.negate &&
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!decoded.src1.absolute && !decoded.src1.negate &&
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!decoded.dst.clamp && decoded.dst.omod == 0,
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"captured V_MIN/MAX_F64 lost its inline source, register pair, or modifiers");
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}
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for (const auto [opcode, expected] : {
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std::pair{0x17u, Opcode::V_TRUNC_F64}, std::pair{0x18u, Opcode::V_CEIL_F64},
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std::pair{0x1au, Opcode::V_FLOOR_F64}}) {
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for (const bool vop3 : {false, true}) {
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const std::array<uint32_t, 2> words = vop3
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? std::array<uint32_t, 2>{EncodeVop3Word0(0x180 + opcode, 1, 0, 1),
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EncodeVop3Word1(8, 0, 0) | (1u << 29)}
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: std::array<uint32_t, 2>{EncodeVop1(opcode, 1, 258), 0};
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Instruction decoded;
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DecodeInstruction(words, 0, decoded);
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Check(decoded.opcode == expected && decoded.word_count == (vop3 ? 2u : 1u) &&
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decoded.dst.reg == 1 && decoded.src0.reg == (vop3 ? 8u : 2u) &&
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decoded.src0.absolute == vop3 && decoded.src0.negate == vop3,
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"FP64 rounding lost its VOP1/VOP3 encoding, odd pair, or source modifiers");
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}
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for (const uint32_t source : {249u, 250u}) {
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const uint32_t invalid[] = {EncodeVop1(opcode, 1, source),
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source == 249u ? 0x00060604u : EncodeVop1Dpp(4, 0xe4)};
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Instruction decoded;
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DecodeInstruction(invalid, 0, decoded);
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Check(decoded.opcode == Opcode::UNSUPPORTED,
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"FP64 rounding accepted unsupported SDWA or DPP encoding");
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}
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}
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}
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void TestNewShaderRecompilerVop1SdwaBfrev() {
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using namespace ShaderRecompiler::Decoder;
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const uint32_t captured[] = {0x7e0070f9u, 0x00040600u};
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@@ -14742,6 +14789,7 @@ int main() {
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TestNewShaderRecompilerDsWideAndAtomicTranslation();
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TestNewShaderRecompilerCapturedVop1SdwaByteConvert();
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TestNewShaderRecompilerCapturedFractF64();
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TestNewShaderRecompilerF64AluEncodings();
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TestNewShaderRecompilerVop1SdwaBfrev();
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TestNewShaderRecompilerVop1SdwaNotDestination();
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TestNewShaderRecompilerScalarMemoryBindingDomains();
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