mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
shader: reuse operands and remove duplicate helpers
This commit is contained in:
nmzik
@@ -7,6 +7,7 @@
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#include <iterator>
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#include <map>
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#include <set>
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#include <span>
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#include <stack>
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namespace Libs::Graphics::ShaderRecompiler::CFG {
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@@ -861,15 +862,15 @@ void ComputeNaturalLoops(Graph& graph) {
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loop.header = edge.to;
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loop.latch = edge.from;
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loop.continue_block = edge.from;
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loop.body_blocks = body;
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loop.body_blocks = std::move(body);
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for (auto block_id: body) {
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for (auto block_id: loop.body_blocks) {
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const auto* block = graph.FindBlock(block_id);
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if (block == nullptr) {
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continue;
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}
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for (auto succ: block->successors) {
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if (!Contains(body, succ)) {
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if (!Contains(loop.body_blocks, succ)) {
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AddUnique(loop.exit_blocks, succ);
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}
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}
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@@ -1749,7 +1750,7 @@ bool RouteOneSharedArm(Graph& graph, uint32_t original_block_count, uint32_t out
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inner_is_true ? outer->terminator.false_block : outer->terminator.true_block;
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const auto* inner = graph.FindBlock(inner_id);
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if (inner == nullptr || inner->inst_begin == inner->inst_end ||
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inner->predecessors != std::vector<uint32_t> {outer_id} ||
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inner->predecessors.size() != 1u || inner->predecessors.front() != outer_id ||
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inner->terminator.kind != TerminatorKind::ConditionalBranch ||
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IsInnermostLoopControlConditional(graph, *inner)) {
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continue;
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@@ -1941,9 +1942,9 @@ Graph BuildGraph(const Decoder::Program& program) {
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graph, FailureKind::InvalidBranchTarget, UINT32_MAX,
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fmt::format("unsupported dynamic S_SETPC_B64 at pc 0x{:08x}", inst.pc));
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}
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const auto& target_pcs = target_info.indirect
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? target_info.target_pcs
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: std::vector<uint32_t> {target_info.target};
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const auto target_pcs = target_info.indirect
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? std::span<const uint32_t>(target_info.target_pcs)
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: std::span<const uint32_t>(&target_info.target, 1);
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for (const auto target: target_pcs) {
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if (!IsValidTarget(target, instruction_pcs, first_pc, end_pc)) {
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ExitBuildFailure(
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@@ -2103,11 +2104,7 @@ Graph BuildGraph(const Decoder::Program& program) {
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}
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SortUnique(graph.code_table_load_pcs);
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ComputeDominators(graph);
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ComputePostDominators(graph);
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ComputeBackEdges(graph);
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ComputeNaturalLoops(graph);
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ComputeComponents(graph);
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RecomputeAnalyses(graph);
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if (indirect_setpc) {
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graph.irreducible = true;
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@@ -714,57 +714,7 @@ void DecodeVop1Dpp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_in
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ReadLiteralOperands(code, word_index, inst);
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}
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using Vop1ModifierDecodeFn = void (*)(uint32_t pc, std::span<const uint32_t> code,
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uint32_t word_index, uint32_t opcode, uint32_t vdst,
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Instruction& inst);
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struct Vop1ModifierDecoder {
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uint32_t escape = 0;
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Vop1ModifierDecodeFn decode = nullptr;
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};
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constexpr Vop1ModifierDecoder VOP1_MODIFIER_DECODERS[] = {
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{249u, DecodeVop1Sdwa},
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{250u, DecodeVop1Dpp},
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};
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bool TryDecodeVop1Modifier(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
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uint32_t src0, uint32_t opcode, uint32_t vdst, Instruction& inst) {
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for (const auto& decoder: VOP1_MODIFIER_DECODERS) {
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if (decoder.escape == src0) {
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decoder.decode(pc, code, word_index, opcode, vdst, inst);
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return true;
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}
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}
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return false;
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}
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bool IsVop2FloatSourceOpcode(Opcode opcode) {
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switch (opcode) {
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case Opcode::V_ADD_F32:
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case Opcode::V_SUB_F32:
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case Opcode::V_SUBREV_F32:
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case Opcode::V_MUL_F32:
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case Opcode::V_MIN_F32:
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case Opcode::V_MAX_F32:
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case Opcode::V_MAC_F32:
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case Opcode::V_MADMK_F32:
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case Opcode::V_MADAK_F32:
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case Opcode::V_CVT_PKRTZ_F16_F32:
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case Opcode::V_ADD_F16:
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case Opcode::V_SUB_F16:
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case Opcode::V_SUBREV_F16:
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case Opcode::V_MUL_F16:
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case Opcode::V_FMAC_F16:
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case Opcode::V_FMAMK_F16:
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case Opcode::V_FMAAK_F16:
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case Opcode::V_MAX_F16:
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case Opcode::V_MIN_F16: return true;
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default: return false;
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}
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}
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bool IsVop2FloatResultOpcode(Opcode opcode) {
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bool IsVop2FloatOpcode(Opcode opcode) {
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switch (opcode) {
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case Opcode::V_ADD_F32:
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case Opcode::V_SUB_F32:
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@@ -975,12 +925,12 @@ bool ValidateVop2Sdwa(Instruction& inst, uint32_t opcode, const Vop2SdwaFields&
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SetUnsupported(inst, Family::VOP2, opcode, "VOP2 SDWA selector is invalid");
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return false;
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}
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if ((fields.clamp != 0u || fields.omod != 0u) && !IsVop2FloatResultOpcode(inst.opcode)) {
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if ((fields.clamp != 0u || fields.omod != 0u) && !IsVop2FloatOpcode(inst.opcode)) {
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SetUnsupported(inst, Family::VOP2, opcode, "VOP2 SDWA output modifiers are not supported");
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return false;
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}
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if (IsFullWidthVop2Sdwa(fields)) {
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if (!IsVop2FloatSourceOpcode(inst.opcode) && inst.opcode != Opcode::V_CNDMASK_B32 &&
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if (!IsVop2FloatOpcode(inst.opcode) && inst.opcode != Opcode::V_CNDMASK_B32 &&
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(fields.src0_neg != 0u || fields.src0_abs != 0u || fields.src1_neg != 0u ||
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fields.src1_abs != 0u)) {
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SetUnsupported(inst, Family::VOP2, opcode,
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@@ -1098,7 +1048,7 @@ void DecodeVop2Dpp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_in
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inst.src1.negate_hi = inst.src1.negate;
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}
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if (!IsVop2FloatSourceOpcode(inst.opcode) && !packed_fmac &&
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if (!IsVop2FloatOpcode(inst.opcode) && !packed_fmac &&
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(inst.src0.negate || inst.src0.absolute || inst.src1.negate || inst.src1.absolute)) {
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SetUnsupported(inst, Family::VOP2, opcode,
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"VOP2 DPP integer source modifiers are not supported");
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@@ -1107,32 +1057,6 @@ void DecodeVop2Dpp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_in
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FinalizeVop2Instruction(code, word_index, inst);
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}
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using Vop2ModifierDecodeFn = void (*)(uint32_t pc, std::span<const uint32_t> code,
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uint32_t word_index, uint32_t opcode, uint32_t vdst,
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uint32_t vsrc1, Instruction& inst);
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struct Vop2ModifierDecoder {
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uint32_t escape = 0;
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Vop2ModifierDecodeFn decode = nullptr;
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};
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constexpr Vop2ModifierDecoder VOP2_MODIFIER_DECODERS[] = {
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{249u, DecodeVop2Sdwa},
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{250u, DecodeVop2Dpp},
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};
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bool TryDecodeVop2Modifier(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
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uint32_t src0, uint32_t opcode, uint32_t vdst, uint32_t vsrc1,
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Instruction& inst) {
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for (const auto& decoder: VOP2_MODIFIER_DECODERS) {
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if (decoder.escape == src0) {
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decoder.decode(pc, code, word_index, opcode, vdst, vsrc1, inst);
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return true;
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}
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}
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return false;
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}
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struct VopcSdwaFields {
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uint32_t src0 = 0;
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uint32_t sdst = 0;
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@@ -1543,8 +1467,10 @@ void DecodeVop2(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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SetUnsupported(inst, Family::VOP2, opcode, "VOP2 opcode is not implemented");
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return;
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}
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if (TryDecodeVop2Modifier(pc, code, word_index, src0, opcode, vdst, vsrc1, inst)) {
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return;
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switch (src0) {
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case 249u: DecodeVop2Sdwa(pc, code, word_index, opcode, vdst, vsrc1, inst); return;
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case 250u: DecodeVop2Dpp(pc, code, word_index, opcode, vdst, vsrc1, inst); return;
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default: break;
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}
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DecodeVectorGpr(vdst, inst.dst);
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@@ -1575,8 +1501,10 @@ void DecodeVop1(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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inst.src_count = 0;
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return;
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}
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if (TryDecodeVop1Modifier(pc, code, word_index, src0, opcode, vdst, inst)) {
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return;
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switch (src0) {
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case 249u: DecodeVop1Sdwa(pc, code, word_index, opcode, vdst, inst); return;
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case 250u: DecodeVop1Dpp(pc, code, word_index, opcode, vdst, inst); return;
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default: break;
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}
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const bool scalar_dst = UsesScalarDestination(inst.opcode);
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if (scalar_dst) {
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@@ -89,10 +89,10 @@ void Translator::V_CVT_16_F16(const Decoder::Instruction& inst, bool signed_valu
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if (signed_value) {
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const auto converted =
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ConvertF32ToI32Saturated(value, -32768.0f, 32768.0f, 32767.0f, 0xffff8000u, 0x7fffu);
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WriteU16(DestinationOperand(inst), ir.BitwiseAnd(converted, IR::U32(IR::Value(0xffffu))));
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Write16Bits(DestinationOperand(inst), ir.BitwiseAnd(converted, IR::U32(IR::Value(0xffffu))));
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return;
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}
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WriteU16(DestinationOperand(inst),
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Write16Bits(DestinationOperand(inst),
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ConvertF32ToU32Saturated(value, 65536.0f, 65535.0f, 0xffffu));
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}
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@@ -59,7 +59,7 @@ bool Translator::Float16Unary(const Decoder::Instruction& inst, IR::ValueOpcode
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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WriteU16(DestinationOperand(inst), ir.Select(negative, invalid, bits));
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Write16Bits(DestinationOperand(inst), ir.Select(negative, invalid, bits));
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return true;
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}
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@@ -95,7 +95,7 @@ bool Translator::Float16Trig(const Decoder::Instruction& inst, IR::ValueOpcode o
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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WriteU16(DestinationOperand(inst), ir.Select(infinite, invalid, bits));
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Write16Bits(DestinationOperand(inst), ir.Select(infinite, invalid, bits));
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return true;
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}
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@@ -111,7 +111,7 @@ bool Translator::Float16Ternary(const Decoder::Instruction& inst, IR::ValueOpcod
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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const auto& operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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args[index] = mix ? IR::Value(ReadMixF32(operand)) : IR::Value(ReadF16AsF32(operand));
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}
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WriteF16(DestinationOperand(inst), IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})));
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@@ -128,7 +128,7 @@ bool Translator::FloatBinary(const Decoder::Instruction& inst, IR::ValueOpcode o
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bool reverse) {
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std::array<IR::Value, 2> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = SourceAt(inst, reverse ? 1u - index : index);
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const auto& operand = SourceAt(inst, reverse ? 1u - index : index);
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args[index] = ReadOperand(operand, IR::ArgTypeOf(opcode, index));
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {args[0], args[1]}));
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@@ -139,7 +139,7 @@ bool Translator::FloatTernary(const Decoder::Instruction& inst, IR::ValueOpcode
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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const auto& operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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const auto type = IR::ArgTypeOf(opcode, index);
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args[index] = type == IR::Type::F32 && mix ? IR::Value(ReadMixF32(operand))
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: ReadOperand(operand, type);
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@@ -203,9 +203,6 @@ bool Translator::V_CUBEMA_F32(const Decoder::Instruction& inst) {
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}
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bool Translator::FloatCube(const Decoder::Instruction& inst, uint32_t result_kind) {
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const auto select_f32 = [&](IR::U1 condition, IR::F32 true_value, IR::F32 false_value) {
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return IR::F32(ir.Emit(IR::ValueOpcode::SelectF32, {condition, true_value, false_value}));
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};
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const auto x = ReadMixF32(inst.src0);
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const auto y = ReadMixF32(inst.src1);
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const auto z = ReadMixF32(inst.src2);
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@@ -223,18 +220,18 @@ bool Translator::FloatCube(const Decoder::Instruction& inst, uint32_t result_kin
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const auto y_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {y, IR::Value::F32(0.0f)}));
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const auto z_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {z, IR::Value::F32(0.0f)}));
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const auto select_face = [&](IR::F32 x_value, IR::F32 y_value, IR::F32 z_value) {
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return select_f32(z_face, z_value, select_f32(y_face, y_value, x_value));
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return SelectF32(z_face, z_value, SelectF32(y_face, y_value, x_value));
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};
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IR::F32 result;
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switch (result_kind) {
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case 0u:
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result = select_face(
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select_f32(x_neg, IR::F32(IR::Value::F32(1.0f)), IR::F32(IR::Value::F32(0.0f))),
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select_f32(y_neg, IR::F32(IR::Value::F32(3.0f)), IR::F32(IR::Value::F32(2.0f))),
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select_f32(z_neg, IR::F32(IR::Value::F32(5.0f)), IR::F32(IR::Value::F32(4.0f))));
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SelectF32(x_neg, IR::F32(IR::Value::F32(1.0f)), IR::F32(IR::Value::F32(0.0f))),
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SelectF32(y_neg, IR::F32(IR::Value::F32(3.0f)), IR::F32(IR::Value::F32(2.0f))),
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SelectF32(z_neg, IR::F32(IR::Value::F32(5.0f)), IR::F32(IR::Value::F32(4.0f))));
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break;
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case 1u: result = select_face(select_f32(x_neg, z, nz), x, select_f32(z_neg, nx, x)); break;
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case 2u: result = select_face(ny, select_f32(y_neg, nz, z), ny); break;
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case 1u: result = select_face(SelectF32(x_neg, z, nz), x, SelectF32(z_neg, nx, x)); break;
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case 2u: result = select_face(ny, SelectF32(y_neg, nz, z), ny); break;
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case 3u: {
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const auto two = IR::F32(IR::Value::F32(2.0f));
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result = select_face(IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {x, two})),
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@@ -9,7 +9,7 @@ bool Translator::Integer16Shift(const Decoder::Instruction& inst, IR::ValueOpcod
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const auto value = ReadU16AsU32(inst.src1, arithmetic);
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const auto count = ir.BitwiseAnd(ReadU16AsU32(inst.src0, false), IR::U32(IR::Value(15u)));
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const auto result = IR::U32(ir.Emit(opcode, {value, count}));
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WriteU16(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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Write16Bits(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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return true;
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}
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@@ -18,7 +18,7 @@ bool Translator::Integer16Binary(const Decoder::Instruction& inst, IR::ValueOpco
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const auto lhs = ReadU16AsU32(inst.src0, sign);
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const auto rhs = ReadU16AsU32(inst.src1, sign);
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const auto result = IR::U32(ir.Emit(opcode, {lhs, rhs}));
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WriteU16(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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Write16Bits(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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return true;
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}
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@@ -26,7 +26,7 @@ bool Translator::V_MED3_I16(const Decoder::Instruction& inst) {
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const auto result = IR::U32(ir.Emit(
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IR::ValueOpcode::SMedTri32, {ReadU16AsU32(inst.src0, true), ReadU16AsU32(inst.src1, true),
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ReadU16AsU32(inst.src2, true)}));
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WriteU16(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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Write16Bits(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
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return true;
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}
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@@ -143,7 +143,7 @@ bool Translator::SimpleInteger(const Decoder::Instruction& inst, IR::ValueOpcode
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < inst.src_count; index++) {
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const auto arg_type = IR::ArgTypeOf(opcode, index);
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const auto operand = SourceAt(inst, reverse && index < 2u ? 1u - index : index);
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const auto& operand = SourceAt(inst, reverse && index < 2u ? 1u - index : index);
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args[index] = ReadOperand(operand, arg_type == IR::Type::Void ? type : arg_type);
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if (mask_shift_count && index == 1u) {
|
||||
args[index] = ir.BitwiseAnd(IR::U32(args[index]), IR::U32(IR::Value(31u)));
|
||||
@@ -563,10 +563,8 @@ bool Translator::PackB16(const Decoder::Instruction& inst, bool high0, bool high
|
||||
: ReadU32(inst.src0);
|
||||
const auto hi = high1 ? ir.ShiftRightLogical(ReadU32(inst.src1), IR::U32(IR::Value(16u)))
|
||||
: ReadU32(inst.src1);
|
||||
const auto low_bits = ir.BitwiseAnd(lo, IR::U32(IR::Value(0xffffu)));
|
||||
const auto high_bits = ir.ShiftLeftLogical(ir.BitwiseAnd(hi, IR::U32(IR::Value(0xffffu))),
|
||||
IR::U32(IR::Value(16u)));
|
||||
WriteOperand(DestinationOperand(inst), ir.BitwiseOr(low_bits, high_bits));
|
||||
const auto result = PackU16Lanes(lo, hi);
|
||||
WriteOperand(DestinationOperand(inst), result);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -71,16 +71,22 @@ ResourceKind FlatSegmentResourceKind(uint32_t segment) {
|
||||
}
|
||||
}
|
||||
|
||||
bool IsScalarAddressLoad(Decoder::Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Decoder::Opcode::S_LOAD_DWORD:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX2:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX4:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX8:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX16: return true;
|
||||
default: return false;
|
||||
}
|
||||
}
|
||||
|
||||
ResourceKind MemoryKind(const Decoder::Instruction& decoded) {
|
||||
switch (decoded.family) {
|
||||
case Decoder::Family::SMEM:
|
||||
return decoded.opcode == Decoder::Opcode::S_LOAD_DWORD ||
|
||||
decoded.opcode == Decoder::Opcode::S_LOAD_DWORDX2 ||
|
||||
decoded.opcode == Decoder::Opcode::S_LOAD_DWORDX4 ||
|
||||
decoded.opcode == Decoder::Opcode::S_LOAD_DWORDX8 ||
|
||||
decoded.opcode == Decoder::Opcode::S_LOAD_DWORDX16
|
||||
? ResourceKind::ScalarAddress
|
||||
: ResourceKind::ScalarBuffer;
|
||||
return IsScalarAddressLoad(decoded.opcode) ? ResourceKind::ScalarAddress
|
||||
: ResourceKind::ScalarBuffer;
|
||||
case Decoder::Family::MUBUF:
|
||||
case Decoder::Family::MTBUF: return ResourceKind::Buffer;
|
||||
case Decoder::Family::FLAT: return FlatSegmentResourceKind(decoded.memory_segment);
|
||||
@@ -146,16 +152,6 @@ IR::MemoryInfo MemoryInfoFromDecoded(const Decoder::Instruction& decoded) {
|
||||
return memory;
|
||||
}
|
||||
|
||||
bool IsScalarAddressLoad(Decoder::Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Decoder::Opcode::S_LOAD_DWORD:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX2:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX4:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX8:
|
||||
case Decoder::Opcode::S_LOAD_DWORDX16: return true;
|
||||
default: return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsScalarBufferLoad(Decoder::Opcode opcode) {
|
||||
switch (opcode) {
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
|
||||
namespace Libs::Graphics::ShaderRecompiler::Frontend {
|
||||
|
||||
Decoder::Operand Translator::SourceAt(const Decoder::Instruction& inst, uint32_t index) {
|
||||
const Decoder::Operand& Translator::SourceAt(const Decoder::Instruction& inst, uint32_t index) {
|
||||
switch (index) {
|
||||
case 0: return inst.src0;
|
||||
case 1: return inst.src1;
|
||||
@@ -25,7 +25,7 @@ Decoder::Operand Translator::DestinationOperand(const Decoder::Instruction& inst
|
||||
return destination;
|
||||
}
|
||||
for (uint32_t index = 0; index < std::min(inst.src_count, 3u); index++) {
|
||||
const auto source = SourceAt(inst, index);
|
||||
const auto& source = SourceAt(inst, index);
|
||||
if (!source.dpp) {
|
||||
continue;
|
||||
}
|
||||
@@ -440,10 +440,6 @@ void Translator::WriteF16(const Decoder::Operand& operand, IR::F32 value) {
|
||||
Write16Bits(operand, bits);
|
||||
}
|
||||
|
||||
void Translator::WriteU16(const Decoder::Operand& operand, IR::U32 value) {
|
||||
Write16Bits(operand, value);
|
||||
}
|
||||
|
||||
IR::U32 Translator::ReadU32(const Decoder::Operand& operand) {
|
||||
return IR::U32(ReadOperand(operand, IR::Type::U32));
|
||||
}
|
||||
@@ -604,10 +600,6 @@ IR::U1 Translator::ThreadBit(const std::array<IR::U32, 2>& mask) {
|
||||
IR::U32(IR::Value(0u)));
|
||||
}
|
||||
|
||||
IR::U1 Translator::ReadCondition(const Decoder::Operand& operand) {
|
||||
return IR::U1(ReadOperand(operand, IR::Type::U1));
|
||||
}
|
||||
|
||||
IR::U32 Translator::ConditionBit(const Decoder::Operand& operand) {
|
||||
return ir.Select(ReadMask(operand), IR::U32(IR::Value(1u)), IR::U32(IR::Value(0u)));
|
||||
}
|
||||
|
||||
@@ -18,7 +18,7 @@ public:
|
||||
void AddBranchCondition(const CFG::BasicBlock& source, IR::BlockInfo& info);
|
||||
|
||||
private:
|
||||
Decoder::Operand SourceAt(const Decoder::Instruction& inst, uint32_t index);
|
||||
const Decoder::Operand& SourceAt(const Decoder::Instruction& inst, uint32_t index);
|
||||
Decoder::Operand DestinationOperand(const Decoder::Instruction& inst);
|
||||
Decoder::Operand OffsetOperand(const Decoder::Operand& operand, uint32_t offset);
|
||||
Decoder::Operand ScalarDestinationOperand(const Decoder::Operand& operand, uint32_t offset);
|
||||
@@ -35,7 +35,6 @@ private:
|
||||
IR::U32 PackHalf2x16(IR::F32 low, IR::F32 high);
|
||||
void Write16Bits(const Decoder::Operand& operand, IR::U32 value);
|
||||
void WriteF16(const Decoder::Operand& operand, IR::F32 value);
|
||||
void WriteU16(const Decoder::Operand& operand, IR::U32 value);
|
||||
IR::U32 ReadU32(const Decoder::Operand& operand);
|
||||
std::array<IR::U32, 2> ReadU32Pair(const Decoder::Operand& operand);
|
||||
IR::U64 ReadU64(const Decoder::Operand& operand);
|
||||
@@ -48,7 +47,6 @@ private:
|
||||
IR::U32 ReadF16LaneBits(const Decoder::Operand& operand, bool high_lane);
|
||||
std::array<IR::U32, 2> ExtractU64(IR::U64 value);
|
||||
void WriteU32Pair(const Decoder::Operand& operand, const std::array<IR::U32, 2>& value);
|
||||
IR::U1 ReadCondition(const Decoder::Operand& operand);
|
||||
IR::U32 ConditionBit(const Decoder::Operand& operand);
|
||||
IR::U1 ReadMask(const Decoder::Operand& operand);
|
||||
IR::U1 ReadMaskValid(const Decoder::Operand& operand);
|
||||
|
||||
@@ -280,8 +280,7 @@ private:
|
||||
return finish(false);
|
||||
}
|
||||
}
|
||||
if (op == ValueOpcode::GetBufferResource || op == ValueOpcode::GetImageResource ||
|
||||
op == ValueOpcode::GetSamplerResource || op == ValueOpcode::GetAddressResource) {
|
||||
if (IsDescriptorHandle(op)) {
|
||||
size_t expected = 4u;
|
||||
if (op == ValueOpcode::GetImageResource) {
|
||||
expected = 8u;
|
||||
|
||||
Reference in New Issue
Block a user