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graphics: implement RDNA2 buffer atomic OR x2
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@@ -8593,6 +8593,37 @@ void TestNewShaderRecompilerBufferAtomicsGuardedByBounds() {
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"buffer atomic memory barrier was emitted before atomic");
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}
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void TestCapturedBufferAtomicOrX2() {
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const uint32_t shader[] = {
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0xe1680018u, 0x80000000u, // buffer_atomic_or_x2 v[0:1], s[0:3], 0 offset:24
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EncodeSopp(0x01),
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};
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auto options = MakeCompileOptions(ShaderType::Compute);
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options.dump_ir = true;
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auto result = RecompileForTest(shader, options);
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Check(Common::ContainsStr(result.decoded_dump, "BUFFER_ATOMIC_OR_X2"),
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"captured MUBUF instruction did not decode as buffer_atomic_or_x2");
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Check(Common::ContainsStr(result.ir_dump, "BufferAtomicOr64"),
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"buffer_atomic_or_x2 did not lower to a 64-bit buffer atomic");
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Check(!Common::ContainsStr(result.ir_dump, "SetVectorRegister"),
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"GLC=0 buffer_atomic_or_x2 unexpectedly wrote an old value to v0:v1");
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(Common::ContainsStr(source, "OpCapability Int64Atomics"),
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"64-bit buffer atomic SPIR-V lacks Int64Atomics capability");
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Check(Common::ContainsStr(source, "ArrayStride 8"),
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"64-bit buffer atomic storage view does not use eight-byte elements");
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Check(CountSourceOccurrences(source, "Aliased") == 2u,
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"both storage-buffer views must declare that they alias");
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Check(SpirvInstructionOpcodeCount(result.spirv, 241u) == 1u,
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"buffer_atomic_or_x2 must lower to exactly one OpAtomicOr");
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Check(Common::ContainsStr(source, "OpMemoryBarrier"),
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"64-bit buffer atomic SPIR-V lacks its device-memory barrier");
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}
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void TestNewShaderRecompilerBranchConditionForms() {
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struct Case {
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uint32_t opcode;
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@@ -11935,6 +11966,7 @@ int main() {
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TestComputeDispatchWaveSize();
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TestNewShaderRecompilerBufferLoadsGuardedByExec();
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TestNewShaderRecompilerBufferAtomicsGuardedByBounds();
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TestCapturedBufferAtomicOrX2();
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TestNewShaderRecompilerPixelImageSampleLodSelection();
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TestNewShaderRecompilerBranchConditionForms();
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TestNewShaderRecompilerSetpcBranch();
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