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shader: share SMEM load results across emulated wave64 halves

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nmzik
2026-10-20 22:32:48 +02:00
parent 1ce663b5a9
commit 8cc5f5364a
1 changed files with 8 additions and 5 deletions
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src/graphics/shader/recompiler/backend/spirv/spirvEmitterProgram.cpp
+8 -5
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@@ -233,14 +233,17 @@ void Invoke(Return (*emit)(Context&, Args...), ValueEmitContext& ctx, const IR::
} }
void EmitDirectInstruction(ValueEmitContext& ctx, const IR::Inst& inst) { void EmitDirectInstruction(ValueEmitContext& ctx, const IR::Inst& inst) {
if (ctx.half != 0 && (inst.GetOpcode() == IR::ValueOpcode::Ballot || using Op = IR::ValueOpcode;
inst.GetOpcode() == IR::ValueOpcode::ReadFirstLane || const auto op = inst.GetOpcode();
inst.GetOpcode() == IR::ValueOpcode::SubgroupUMinU32)) { if (ctx.half != 0 &&
// These operations combine both emulated halves into one whole-wave result. (op == Op::Ballot || op == Op::ReadFirstLane || op == Op::SubgroupUMinU32 ||
op == Op::ReadConstBuffer ||
(op == Op::LoadAddressU32 && ctx.Memory(inst).kind == IR::ResourceKind::ScalarAddress))) {
// Whole-wave results and SMEM loads (SGPR operands, no EXEC) are identical in both halves.
ctx.Define(inst, ctx.other_half->Result(inst)); ctx.Define(inst, ctx.other_half->Result(inst));
return; return;
} }
switch (inst.GetOpcode()) { switch (op) {
#define VALUE_OPCODE(name, ...) \ #define VALUE_OPCODE(name, ...) \
case IR::ValueOpcode::name: return Invoke(Emit##name, ctx, inst); case IR::ValueOpcode::name: return Invoke(Emit##name, ctx, inst);
#include "graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc" #include "graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc"