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graphics: sign-extend vector bitfield extracts

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This commit is contained in:
nmzik
2026-08-16 14:22:57 +02:00
parent 4e343408dc
commit 93398d6d0f
2 changed files with 20 additions and 20 deletions
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src/graphics/shader/recompiler/frontend/translate/Integer.cpp
+4 -6
View File
@@ -548,12 +548,10 @@ bool Translator::TranslateExtendedInteger(const IR::Instruction& inst) {
const auto count = const auto count =
IR::U32(ir.Emit(IR::ValueOpcode::UMin32, IR::U32(ir.Emit(IR::ValueOpcode::UMin32,
{mask(ReadU32(inst.src[2]), 31u), ir.ISub(imm(32), offset)})); {mask(ReadU32(inst.src[2]), 31u), ir.ISub(imm(32), offset)}));
if (inst.op == IR::Opcode::BitFieldExtract3I32) { const auto opcode = inst.op == IR::Opcode::BitFieldExtract3I32
result = ? IR::ValueOpcode::BitFieldSExtract
ir.BitwiseAnd(ir.ShiftRightArithmetic(source, offset), right_mask32(count)); : IR::ValueOpcode::BitFieldUExtract;
} else { result = ir.Emit(opcode, {source, offset, count});
result = ir.Emit(IR::ValueOpcode::BitFieldUExtract, {source, offset, count});
}
break; break;
} }
case IR::Opcode::BitFieldInsertSelectU32: { case IR::Opcode::BitFieldInsertSelectU32: {
tests/ShaderRecompilerComputeTests.cpp
+16 -14
View File
@@ -12021,7 +12021,7 @@ TestCase VectorVop3IntegerOps() {
0x3f3f3f3fu, 0x3f3f3f3fu,
0x3c3c3c38u, 0x3c3c3c38u,
0x0fu, 0x0fu,
0x0fu, 0xffffffffu,
0x8b8b8b8bu, 0x8b8b8b8bu,
0x44556677u, 0x44556677u,
0x00000f00u, 0x00000f00u,
@@ -12044,27 +12044,29 @@ TestCase VectorVop3IntegerOps() {
O::VSubI32, O::VSubrevI32, O::BufferStoreDword, O::SEndpgm}}; O::VSubI32, O::VSubrevI32, O::BufferStoreDword, O::SEndpgm}};
} }
TestCase VectorBfeI32ArithmeticShiftMasksField() { TestCase VectorBfeI32SignExtendsField() {
using O = ShaderOpcode; using O = ShaderOpcode;
std::vector<u32> code; std::vector<u32> code;
AppendVMovLiteral(&code, 0, 0x80000000u); for (u32 vgpr = 0; vgpr < 6; vgpr++) {
AppendVMovLiteral(&code, 1, 0xfffffff8u); AppendVMovU32(&code, 30, vgpr * sizeof(u32));
AppendVMovU32(&code, 2, 31); AppendBufferLoadDword(&code, vgpr, 30);
AppendVMovU32(&code, 3, 1); }
AppendVMovU32(&code, 4, 3);
AppendVMovU32(&code, 5, 4);
AppendVop3(&code, 0x149, 10, Vgpr(0), Vgpr(2), Vgpr(3)); AppendVop3(&code, 0x149, 10, Vgpr(0), Vgpr(2), Vgpr(3));
AppendVop3(&code, 0x149, 11, Vgpr(1), Vgpr(4), Vgpr(5)); AppendVop3(&code, 0x149, 11, Vgpr(1), Vgpr(4), Vgpr(5));
AppendStoreVgpr(&code, 10, 0); AppendStoreVgpr(&code, 10, 0);
AppendStoreVgpr(&code, 11, 1); AppendStoreVgpr(&code, 11, 1);
AppendEnd(&code); AppendEnd(&code);
return {"VectorBfeI32ArithmeticShiftMasksField", TestCase test;
code, test.name = "VectorBfeI32SignExtendsField";
{}, test.code = std::move(code);
{1, 0x0fu}, test.initial = {0x80000000u, 0xfffffff8u, 31, 1, 3, 4};
{O::VMovB32, O::VBfeI32, O::BufferStoreDword, O::SEndpgm}}; test.expected = {0xffffffffu, 0xffffffffu};
test.opcodes = {O::VMovB32, O::BufferLoadDword, O::VBfeI32,
O::BufferStoreDword, O::SEndpgm};
test.required_spirv = {"OpBitFieldSExtract"};
return test;
} }
TestCase VectorAlignByteUsesFiveBitByteOffset() { TestCase VectorAlignByteUsesFiveBitByteOffset() {
@@ -17655,7 +17657,7 @@ std::vector<TestCase> MakeCases() {
AddCase(Vop2SdwaMinU32PreservesWordDestination); AddCase(Vop2SdwaMinU32PreservesWordDestination);
AddCase(VectorShiftCountsMaskLowBits); AddCase(VectorShiftCountsMaskLowBits);
AddCase(VectorVop3IntegerOps); AddCase(VectorVop3IntegerOps);
AddCase(VectorBfeI32ArithmeticShiftMasksField); AddCase(VectorBfeI32SignExtendsField);
AddCase(VectorAlignByteUsesFiveBitByteOffset); AddCase(VectorAlignByteUsesFiveBitByteOffset);
AddCase(VectorCarryAndBitCountOps); AddCase(VectorCarryAndBitCountOps);
AddCase(VectorMbcntUsesThreadMask); AddCase(VectorMbcntUsesThreadMask);