From 9c263a98861efa02f5a86949e51ebc6b8fd13646 Mon Sep 17 00:00:00 2001 From: nmzik Date: Sun, 9 Aug 2026 05:23:43 +0200 Subject: [PATCH] gpu: accept disabled default clip planes --- .../guest_gpu/command_processor/pm4Handlers.cpp | 10 ++++++++++ src/graphics/guest_gpu/pm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp index ea298c0a4..9e300884a 100644 --- a/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp +++ b/src/graphics/guest_gpu/command_processor/pm4Handlers.cpp @@ -183,6 +183,10 @@ static void HwCtxIgnoreAaMaskRegister([[maybe_unused]] uint32_t cmd_offset, static void HwCtxIgnoreAlphaToMaskRegister([[maybe_unused]] uint32_t value) {} +static void HwCtxIgnoreDisabledUserClipPlane(CommandProcessor& cp, uint32_t value) { + EXIT_NOT_IMPLEMENTED(value != 0 || cp.GetCtx().GetClipControl().user_clip_planes != 0); +} + static void HwCtxIgnoreDrawPayloadControl([[maybe_unused]] uint32_t value) {} static void HwCtxIgnoreObjprimIdControl([[maybe_unused]] uint32_t value) {} @@ -3343,6 +3347,12 @@ void GraphicsInitJmpTablesCxIndirect() { }; } + for (auto cmd_offset = Pm4::PA_CL_UCP_0_X; cmd_offset <= Pm4::PA_CL_UCP_5_W; cmd_offset++) { + g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) { + HwCtxIgnoreDisabledUserClipPlane(cp, value); + }; + } + for (auto cmd_offset = Pm4::PA_SC_VPORT_SCISSOR_0_TL; cmd_offset <= Pm4::PA_SC_VPORT_SCISSOR_15_TL; cmd_offset += 2) { g_hw_ctx_indirect_func[cmd_offset] = [](KYTY_HW_CTX_INDIRECT_ARGS) { diff --git a/src/graphics/guest_gpu/pm4.h b/src/graphics/guest_gpu/pm4.h index 6ce5b53cb..1d31c7dd5 100644 --- a/src/graphics/guest_gpu/pm4.h +++ b/src/graphics/guest_gpu/pm4.h @@ -372,6 +372,7 @@ constexpr uint32_t PA_CL_UCP_0_X = 0x16F; constexpr uint32_t PA_CL_UCP_0_Y = 0x170; constexpr uint32_t PA_CL_UCP_0_Z = 0x171; constexpr uint32_t PA_CL_UCP_0_W = 0x172; +constexpr uint32_t PA_CL_UCP_5_W = 0x186; constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191; constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0; constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;