From a52d1ed4e2f92f4d7eaa062b8e45acb9234b97b3 Mon Sep 17 00:00:00 2001 From: nmzik Date: Thu, 22 Oct 2026 01:09:09 +0200 Subject: [PATCH] shader: drop the 64-bit min/max NaN-lhs select the ordered compare already covers --- .../shader/recompiler/backend/spirv/spirvEmitterAlu.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp index 720faf9d4..5245c6e7c 100644 --- a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp +++ b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp @@ -20,9 +20,8 @@ uint32_t EmitMinMaxF64(EmitterState& state, uint32_t lhs, uint32_t rhs, bool max result = Select(state, TypeF64(state), equal, Unary(state, spv::OpBitcast, TypeF64(state), equal_bits), result); - // Non-IEEE mode selects the other operand for NaN, and lhs when both are NaN. - result = Select(state, TypeF64(state), Unary(state, spv::OpIsNan, TypeBool(state), lhs), - rhs, result); + // Non-IEEE mode selects the other operand for NaN, and lhs when both are NaN. The ordered + // compares already pick rhs for a NaN lhs. return Select(state, TypeF64(state), Unary(state, spv::OpIsNan, TypeBool(state), rhs), lhs, result); }