mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-21 19:36:55 +02:00
graphics: split shader translation into explicit opcode dispatchers
This commit is contained in:
nmzik
@@ -5,22 +5,13 @@
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namespace Libs::Graphics::ShaderRecompiler::Frontend {
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bool Translator::TranslatePackedFloat16(const Decoder::Instruction& inst) {
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IR::ValueOpcode opcode;
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switch (inst.opcode) {
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case Decoder::Opcode::V_PK_ADD_F16: opcode = IR::ValueOpcode::FPAdd32; break;
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case Decoder::Opcode::V_PK_MUL_F16: opcode = IR::ValueOpcode::FPMul32; break;
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case Decoder::Opcode::V_PK_MIN_F16: opcode = IR::ValueOpcode::FPMin32; break;
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case Decoder::Opcode::V_PK_MAX_F16: opcode = IR::ValueOpcode::FPMax32; break;
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case Decoder::Opcode::V_PK_FMA_F16: opcode = IR::ValueOpcode::FPFma32; break;
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case Decoder::Opcode::V_PK_FMAC_F16: opcode = IR::ValueOpcode::FPFma32; break;
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default: return false;
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}
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bool Translator::PackedFloat16(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool quiet_snan) {
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const auto translate_lane = [&](bool high) {
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const auto lhs = ReadF16LaneAsF32(inst.src0, high, true);
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const auto rhs = ReadF16LaneAsF32(inst.src1, high, true);
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IR::F32 result;
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if (inst.opcode == Decoder::Opcode::V_PK_FMAC_F16) {
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if (accumulator) {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs, ReadF16LaneAsF32(inst.dst, high, true)}));
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} else if (inst.src_count == 3u) {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs, ReadF16LaneAsF32(inst.src2, high, true)}));
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@@ -33,9 +24,8 @@ bool Translator::TranslatePackedFloat16(const Decoder::Instruction& inst) {
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raw.omod = 0u;
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raw.clamp = false;
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auto result = PackHalf2x16(translate_lane(false), translate_lane(true));
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if (inst.opcode == Decoder::Opcode::V_PK_MIN_F16 ||
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inst.opcode == Decoder::Opcode::V_PK_MAX_F16) {
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const auto quiet_snan = [&](const Decoder::Operand& operand, bool high) {
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if (quiet_snan) {
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const auto quiet_snan_lane = [&](const Decoder::Operand& operand, bool high) {
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const auto bits = ReadU16LaneAsU32(operand, high, false);
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const auto exponent = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x7c00u)));
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const auto payload = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x01ffu)));
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@@ -44,8 +34,8 @@ bool Translator::TranslatePackedFloat16(const Decoder::Instruction& inst) {
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return std::pair {snan, ir.BitwiseOr(bits, IR::U32(IR::Value(0x0200u)))};
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};
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const auto override_lane = [&](bool high) {
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const auto [lhs_snan, lhs_quiet] = quiet_snan(inst.src0, high);
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const auto [rhs_snan, rhs_quiet] = quiet_snan(inst.src1, high);
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const auto [lhs_snan, lhs_quiet] = quiet_snan_lane(inst.src0, high);
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const auto [rhs_snan, rhs_quiet] = quiet_snan_lane(inst.src1, high);
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const auto normal = high ? ir.ShiftRightLogical(result, IR::U32(IR::Value(16u)))
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: ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu)));
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return ir.Select(lhs_snan, lhs_quiet, ir.Select(rhs_snan, rhs_quiet, normal));
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@@ -56,176 +46,130 @@ bool Translator::TranslatePackedFloat16(const Decoder::Instruction& inst) {
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return true;
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}
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bool Translator::TranslateFloat16Operation(const Decoder::Instruction& inst) {
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IR::ValueOpcode opcode;
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switch (inst.opcode) {
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case Decoder::Opcode::V_ADD_F16: opcode = IR::ValueOpcode::FPAdd32; break;
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case Decoder::Opcode::V_SUB_F16: opcode = IR::ValueOpcode::FPSub32; break;
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case Decoder::Opcode::V_SUBREV_F16: opcode = IR::ValueOpcode::FPSub32; break;
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case Decoder::Opcode::V_MUL_F16: opcode = IR::ValueOpcode::FPMul32; break;
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case Decoder::Opcode::V_MIN_F16: opcode = IR::ValueOpcode::FPMin32; break;
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case Decoder::Opcode::V_MAX_F16: opcode = IR::ValueOpcode::FPMax32; break;
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case Decoder::Opcode::V_FMAC_F16:
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case Decoder::Opcode::V_FMAMK_F16:
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case Decoder::Opcode::V_FMAAK_F16:
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case Decoder::Opcode::V_FMA_F16:
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case Decoder::Opcode::V_MAD_MIXLO_F16: opcode = IR::ValueOpcode::FPFma32; break;
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case Decoder::Opcode::V_MAD_MIXHI_F16: opcode = IR::ValueOpcode::FPFma32; break;
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case Decoder::Opcode::V_RCP_F16: opcode = IR::ValueOpcode::FPRecip32; break;
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case Decoder::Opcode::V_SQRT_F16: opcode = IR::ValueOpcode::FPSqrt; break;
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case Decoder::Opcode::V_RSQ_F16: opcode = IR::ValueOpcode::FPRecipSqrt32; break;
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case Decoder::Opcode::V_LOG_F16: opcode = IR::ValueOpcode::FPLog2; break;
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case Decoder::Opcode::V_EXP_F16: opcode = IR::ValueOpcode::FPExp2; break;
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case Decoder::Opcode::V_FLOOR_F16: opcode = IR::ValueOpcode::FPFloor32; break;
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case Decoder::Opcode::V_CEIL_F16: opcode = IR::ValueOpcode::FPCeil32; break;
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case Decoder::Opcode::V_TRUNC_F16: opcode = IR::ValueOpcode::FPTrunc32; break;
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case Decoder::Opcode::V_RNDNE_F16: opcode = IR::ValueOpcode::FPRoundEven32; break;
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case Decoder::Opcode::V_MIN3_F16: opcode = IR::ValueOpcode::FPMinTri32; break;
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case Decoder::Opcode::V_MAX3_F16: opcode = IR::ValueOpcode::FPMaxTri32; break;
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case Decoder::Opcode::V_MED3_F16: opcode = IR::ValueOpcode::FPMedTri32; break;
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default: return false;
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}
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const bool accumulator = inst.opcode == Decoder::Opcode::V_FMAC_F16;
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const uint32_t source_count = accumulator ? 3u : inst.src_count;
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < source_count; index++) {
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auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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if (inst.opcode == Decoder::Opcode::V_SUBREV_F16 && index < 2u) {
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operand = SourceAt(inst, 1u - index);
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}
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const bool mix = inst.opcode == Decoder::Opcode::V_MAD_MIXLO_F16 ||
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inst.opcode == Decoder::Opcode::V_MAD_MIXHI_F16;
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args[index] = mix ? IR::Value(ReadMixF32(operand)) : IR::Value(ReadF16AsF32(operand));
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}
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IR::F32 result;
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switch (source_count) {
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case 1: result = IR::F32(ir.Emit(opcode, {args[0]})); break;
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case 2: result = IR::F32(ir.Emit(opcode, {args[0], args[1]})); break;
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case 3: result = IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})); break;
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default: EXIT("invalid half-float source count: %u", inst.src_count);
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}
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if (inst.opcode == Decoder::Opcode::V_SQRT_F16 || inst.opcode == Decoder::Opcode::V_RSQ_F16 ||
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inst.opcode == Decoder::Opcode::V_LOG_F16) {
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const auto negative =
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IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {args[0], IR::Value::F32(0.0f)}));
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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WriteU16(DestinationOperand(inst), ir.Select(negative, invalid, bits));
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bool Translator::Float16Unary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool invalid_negative) {
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const auto argument = ReadF16AsF32(inst.src0);
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auto result = IR::F32(ir.Emit(opcode, {argument}));
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if (!invalid_negative) {
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WriteF16(DestinationOperand(inst), result);
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return true;
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}
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WriteF16(DestinationOperand(inst), result);
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const auto negative =
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IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {argument, IR::Value::F32(0.0f)}));
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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WriteU16(DestinationOperand(inst), ir.Select(negative, invalid, bits));
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return true;
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}
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bool Translator::TranslateFloatOperation(const Decoder::Instruction& inst) {
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if (inst.opcode == Decoder::Opcode::V_FREXP_MANT_F32) {
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const auto bits = ReadU32(inst.src0);
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const auto exponent = IR::U32(
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ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(23u), IR::Value(8u)}));
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const auto mantissa = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x007fffffu)));
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const auto sign = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x80000000u)));
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const auto base = ir.BitwiseOr(sign, IR::U32(IR::Value(0x3f000000u)));
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const auto normal = ir.BitwiseOr(base, mantissa);
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const auto msb = IR::U32(ir.Emit(IR::ValueOpcode::FindUMsb32, {mantissa}));
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const auto shift = ir.ISub(IR::U32(IR::Value(23u)), msb);
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const auto fraction =
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ir.BitwiseAnd(ir.ShiftLeftLogical(mantissa, shift), IR::U32(IR::Value(0x007fffffu)));
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const auto subnormal = ir.BitwiseOr(base, fraction);
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const auto zero = ir.IEqual(mantissa, IR::U32(IR::Value(0u)));
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const auto finite = ir.Select(ir.INotEqual(exponent, IR::U32(IR::Value(0u))), normal,
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ir.Select(zero, bits, subnormal));
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const auto result = ir.Select(ir.IEqual(exponent, IR::U32(IR::Value(0xffu))), bits, finite);
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WriteOperand(DestinationOperand(inst), ir.BitCastF32(result));
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return true;
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}
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IR::ValueOpcode opcode {};
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switch (inst.opcode) {
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case Decoder::Opcode::V_RCP_F32: opcode = IR::ValueOpcode::FPRecip32; break;
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case Decoder::Opcode::V_RCP_IFLAG_F32: opcode = IR::ValueOpcode::FPRecipIFlag32; break;
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case Decoder::Opcode::V_FRACT_F32: opcode = IR::ValueOpcode::FPFract32; break;
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case Decoder::Opcode::V_TRUNC_F32: opcode = IR::ValueOpcode::FPTrunc32; break;
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case Decoder::Opcode::V_CEIL_F32: opcode = IR::ValueOpcode::FPCeil32; break;
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case Decoder::Opcode::V_RNDNE_F32: opcode = IR::ValueOpcode::FPRoundEven32; break;
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case Decoder::Opcode::V_FLOOR_F32: opcode = IR::ValueOpcode::FPFloor32; break;
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case Decoder::Opcode::V_EXP_F32: opcode = IR::ValueOpcode::FPExp2; break;
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case Decoder::Opcode::V_LOG_F32: opcode = IR::ValueOpcode::FPLog2; break;
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case Decoder::Opcode::V_RSQ_F32: opcode = IR::ValueOpcode::FPRecipSqrt32; break;
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case Decoder::Opcode::V_SQRT_F32: opcode = IR::ValueOpcode::FPSqrt; break;
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case Decoder::Opcode::V_SIN_F32: opcode = IR::ValueOpcode::FPSin; break;
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case Decoder::Opcode::V_COS_F32: opcode = IR::ValueOpcode::FPCos; break;
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case Decoder::Opcode::V_ADD_F32: opcode = IR::ValueOpcode::FPAdd32; break;
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case Decoder::Opcode::V_SUB_F32: opcode = IR::ValueOpcode::FPSub32; break;
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case Decoder::Opcode::V_SUBREV_F32: opcode = IR::ValueOpcode::FPSub32; break;
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case Decoder::Opcode::V_MUL_F32: opcode = IR::ValueOpcode::FPMul32; break;
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case Decoder::Opcode::V_MIN_F32: opcode = IR::ValueOpcode::FPMin32; break;
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case Decoder::Opcode::V_MAX_F32: opcode = IR::ValueOpcode::FPMax32; break;
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case Decoder::Opcode::V_MAC_F32: opcode = IR::ValueOpcode::FPFma32; break;
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case Decoder::Opcode::V_MADMK_F32:
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case Decoder::Opcode::V_MADAK_F32:
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case Decoder::Opcode::V_MAD_F32:
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case Decoder::Opcode::V_FMA_F32: opcode = IR::ValueOpcode::FPFma32; break;
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case Decoder::Opcode::V_MIN3_F32: opcode = IR::ValueOpcode::FPMinTri32; break;
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case Decoder::Opcode::V_MAX3_F32: opcode = IR::ValueOpcode::FPMaxTri32; break;
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case Decoder::Opcode::V_MED3_F32: opcode = IR::ValueOpcode::FPMedTri32; break;
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case Decoder::Opcode::V_LDEXP_F32: opcode = IR::ValueOpcode::FPLdexp; break;
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default: break;
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}
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if (opcode != IR::ValueOpcode {}) {
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const bool accumulator = inst.opcode == Decoder::Opcode::V_MAC_F32;
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const bool fused = accumulator || inst.opcode == Decoder::Opcode::V_MADMK_F32 ||
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inst.opcode == Decoder::Opcode::V_MADAK_F32 ||
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inst.opcode == Decoder::Opcode::V_MAD_F32 ||
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inst.opcode == Decoder::Opcode::V_FMA_F32;
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const uint32_t source_count = accumulator ? 3u : inst.src_count;
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < source_count; index++) {
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const auto arg_type = IR::ArgTypeOf(opcode, index);
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auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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if (inst.opcode == Decoder::Opcode::V_SUBREV_F32 && index < 2u) {
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operand = SourceAt(inst, 1u - index);
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}
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args[index] = arg_type == IR::Type::F32 ? (fused ? IR::Value(ReadMixF32(operand))
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: ReadOperand(operand, IR::Type::F32))
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: ReadOperand(operand, arg_type);
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}
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IR::Value result;
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switch (source_count) {
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case 1: result = ir.Emit(opcode, {args[0]}); break;
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case 2: result = ir.Emit(opcode, {args[0], args[1]}); break;
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case 3: result = ir.Emit(opcode, {args[0], args[1], args[2]}); break;
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default: EXIT("invalid floating-point source count: %u", inst.src_count);
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}
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WriteOperand(DestinationOperand(inst), result);
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return true;
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}
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bool Translator::Float16Binary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool reverse) {
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const auto lhs = ReadF16AsF32(reverse ? inst.src1 : inst.src0);
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const auto rhs = ReadF16AsF32(reverse ? inst.src0 : inst.src1);
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WriteF16(DestinationOperand(inst), IR::F32(ir.Emit(opcode, {lhs, rhs})));
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return true;
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}
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bool Translator::Float16Ternary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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args[index] = mix ? IR::Value(ReadMixF32(operand)) : IR::Value(ReadF16AsF32(operand));
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}
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WriteF16(DestinationOperand(inst), IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})));
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return true;
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}
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bool Translator::FloatUnary(const Decoder::Instruction& inst, IR::ValueOpcode opcode) {
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const auto type = IR::ArgTypeOf(opcode, 0);
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {ReadOperand(inst.src0, type)}));
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return true;
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}
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bool Translator::FloatBinary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool reverse) {
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std::array<IR::Value, 2> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = SourceAt(inst, reverse ? 1u - index : index);
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args[index] = ReadOperand(operand, IR::ArgTypeOf(opcode, index));
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {args[0], args[1]}));
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return true;
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}
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bool Translator::FloatTernary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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const auto type = IR::ArgTypeOf(opcode, index);
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args[index] = type == IR::Type::F32 && mix ? IR::Value(ReadMixF32(operand))
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: ReadOperand(operand, type);
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {args[0], args[1], args[2]}));
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return true;
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}
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bool Translator::V_FREXP_MANT_F32(const Decoder::Instruction& inst) {
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const auto bits = ReadU32(inst.src0);
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const auto exponent =
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IR::U32(ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(23u), IR::Value(8u)}));
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const auto mantissa = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x007fffffu)));
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const auto sign = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x80000000u)));
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const auto base = ir.BitwiseOr(sign, IR::U32(IR::Value(0x3f000000u)));
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const auto normal = ir.BitwiseOr(base, mantissa);
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const auto msb = IR::U32(ir.Emit(IR::ValueOpcode::FindUMsb32, {mantissa}));
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const auto shift = ir.ISub(IR::U32(IR::Value(23u)), msb);
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const auto fraction =
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ir.BitwiseAnd(ir.ShiftLeftLogical(mantissa, shift), IR::U32(IR::Value(0x007fffffu)));
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const auto subnormal = ir.BitwiseOr(base, fraction);
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const auto zero = ir.IEqual(mantissa, IR::U32(IR::Value(0u)));
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const auto finite = ir.Select(ir.INotEqual(exponent, IR::U32(IR::Value(0u))), normal,
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ir.Select(zero, bits, subnormal));
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const auto result = ir.Select(ir.IEqual(exponent, IR::U32(IR::Value(0xffu))), bits, finite);
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WriteOperand(DestinationOperand(inst), ir.BitCastF32(result));
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return true;
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}
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bool Translator::V_DOT2C_F32_F16(const Decoder::Instruction& inst) {
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auto a = inst.src0;
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a.op_sel = false;
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a.op_sel_hi = true;
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auto b = inst.src1;
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b.op_sel = false;
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b.op_sel_hi = true;
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const auto a_lo = ReadF16LaneAsF32(a, false);
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const auto a_hi = ReadF16LaneAsF32(a, true);
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const auto b_lo = ReadF16LaneAsF32(b, false);
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const auto b_hi = ReadF16LaneAsF32(b, true);
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const auto acc = ReadMixF32(inst.dst);
|
||||
const auto lo = IR::F32(ir.Emit(IR::ValueOpcode::FPFma32, {a_lo, b_lo, acc}));
|
||||
WriteOperand(DestinationOperand(inst), ir.Emit(IR::ValueOpcode::FPFma32, {a_hi, b_hi, lo}));
|
||||
return true;
|
||||
}
|
||||
|
||||
bool Translator::V_CUBEID_F32(const Decoder::Instruction& inst) {
|
||||
return FloatCube(inst, 0u);
|
||||
}
|
||||
|
||||
bool Translator::V_CUBESC_F32(const Decoder::Instruction& inst) {
|
||||
return FloatCube(inst, 1u);
|
||||
}
|
||||
|
||||
bool Translator::V_CUBETC_F32(const Decoder::Instruction& inst) {
|
||||
return FloatCube(inst, 2u);
|
||||
}
|
||||
|
||||
bool Translator::V_CUBEMA_F32(const Decoder::Instruction& inst) {
|
||||
return FloatCube(inst, 3u);
|
||||
}
|
||||
|
||||
bool Translator::FloatCube(const Decoder::Instruction& inst, uint32_t result_kind) {
|
||||
const auto select_f32 = [&](IR::U1 condition, IR::F32 true_value, IR::F32 false_value) {
|
||||
return IR::F32(ir.Emit(IR::ValueOpcode::SelectF32, {condition, true_value, false_value}));
|
||||
};
|
||||
if (inst.opcode == Decoder::Opcode::V_DOT2C_F32_F16) {
|
||||
auto a = inst.src0;
|
||||
a.op_sel = false;
|
||||
a.op_sel_hi = true;
|
||||
auto b = inst.src1;
|
||||
b.op_sel = false;
|
||||
b.op_sel_hi = true;
|
||||
const auto a_lo = ReadF16LaneAsF32(a, false);
|
||||
const auto a_hi = ReadF16LaneAsF32(a, true);
|
||||
const auto b_lo = ReadF16LaneAsF32(b, false);
|
||||
const auto b_hi = ReadF16LaneAsF32(b, true);
|
||||
const auto acc = ReadMixF32(inst.dst);
|
||||
const auto lo = IR::F32(ir.Emit(IR::ValueOpcode::FPFma32, {a_lo, b_lo, acc}));
|
||||
WriteOperand(DestinationOperand(inst), ir.Emit(IR::ValueOpcode::FPFma32, {a_hi, b_hi, lo}));
|
||||
return true;
|
||||
}
|
||||
if (inst.opcode != Decoder::Opcode::V_CUBEID_F32 &&
|
||||
inst.opcode != Decoder::Opcode::V_CUBESC_F32 &&
|
||||
inst.opcode != Decoder::Opcode::V_CUBETC_F32 &&
|
||||
inst.opcode != Decoder::Opcode::V_CUBEMA_F32) {
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto x = ReadMixF32(inst.src0);
|
||||
const auto y = ReadMixF32(inst.src1);
|
||||
const auto z = ReadMixF32(inst.src2);
|
||||
@@ -246,27 +190,23 @@ bool Translator::TranslateFloatOperation(const Decoder::Instruction& inst) {
|
||||
return select_f32(z_face, z_value, select_f32(y_face, y_value, x_value));
|
||||
};
|
||||
IR::F32 result;
|
||||
switch (inst.opcode) {
|
||||
case Decoder::Opcode::V_CUBEID_F32:
|
||||
switch (result_kind) {
|
||||
case 0u:
|
||||
result = select_face(
|
||||
select_f32(x_neg, IR::F32(IR::Value::F32(1.0f)), IR::F32(IR::Value::F32(0.0f))),
|
||||
select_f32(y_neg, IR::F32(IR::Value::F32(3.0f)), IR::F32(IR::Value::F32(2.0f))),
|
||||
select_f32(z_neg, IR::F32(IR::Value::F32(5.0f)), IR::F32(IR::Value::F32(4.0f))));
|
||||
break;
|
||||
case Decoder::Opcode::V_CUBESC_F32:
|
||||
result = select_face(select_f32(x_neg, z, nz), x, select_f32(z_neg, nx, x));
|
||||
break;
|
||||
case Decoder::Opcode::V_CUBETC_F32:
|
||||
result = select_face(ny, select_f32(y_neg, nz, z), ny);
|
||||
break;
|
||||
case Decoder::Opcode::V_CUBEMA_F32: {
|
||||
case 1u: result = select_face(select_f32(x_neg, z, nz), x, select_f32(z_neg, nx, x)); break;
|
||||
case 2u: result = select_face(ny, select_f32(y_neg, nz, z), ny); break;
|
||||
case 3u: {
|
||||
const auto two = IR::F32(IR::Value::F32(2.0f));
|
||||
result = select_face(IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {x, two})),
|
||||
IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {y, two})),
|
||||
IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {z, two})));
|
||||
break;
|
||||
}
|
||||
default: return false;
|
||||
default: EXIT("invalid cube result kind");
|
||||
}
|
||||
WriteOperand(DestinationOperand(inst), result);
|
||||
return true;
|
||||
|
||||
Reference in New Issue
Block a user