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shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP (#952)
* shader: implement 32-bit RDNA2 image atomic compare-and-swap * shader: share atomic emission and correct image barriers --------- Co-authored-by: nmzik <Nmzik@mail.ru>
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@@ -192,6 +192,7 @@ constexpr MimgGatherInfo MIMG_GATHER_OPCODE_LIST[] = {
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constexpr Detail::OpcodeMap MIMG_ATOMIC_OPCODE_LIST[] = {
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{0x0fu, Opcode::IMAGE_ATOMIC_SWAP},
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{0x10u, Opcode::IMAGE_ATOMIC_CMPSWAP},
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{0x11u, Opcode::IMAGE_ATOMIC_ADD},
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{0x14u, Opcode::IMAGE_ATOMIC_SMIN},
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{0x15u, Opcode::IMAGE_ATOMIC_UMIN},
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@@ -359,6 +360,10 @@ void DecodeMimg(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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SetUnsupported(inst, Family::MIMG, opcode,
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"MIMG image gather requires exactly one dmask bit");
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}
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if (inst.opcode == Opcode::IMAGE_ATOMIC_CMPSWAP && inst.dmask != 0x3u) {
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SetUnsupported(inst, Family::MIMG, opcode,
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"MIMG image compare-and-swap requires 32-bit DMASK 0x3");
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}
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const bool supports_d16 = sample != nullptr || gather != nullptr || opcode == 0x00u ||
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opcode == 0x01u || opcode == 0x08u || opcode == 0x09u;
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if (d16 && !supports_d16) {
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@@ -574,6 +574,7 @@ std::string InstructionToString(const Instruction& inst) {
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case Opcode::IMAGE_SAMPLE:
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case Opcode::IMAGE_STORE:
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case Opcode::IMAGE_STORE_MIP:
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case Opcode::IMAGE_ATOMIC_CMPSWAP:
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case Opcode::IMAGE_ATOMIC_SWAP:
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case Opcode::IMAGE_ATOMIC_ADD:
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case Opcode::IMAGE_ATOMIC_SMIN:
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@@ -599,6 +599,7 @@ enum class Opcode {
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IMAGE_STORE,
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IMAGE_STORE_MIP,
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IMAGE_ATOMIC_SWAP,
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IMAGE_ATOMIC_CMPSWAP,
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IMAGE_ATOMIC_ADD,
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IMAGE_ATOMIC_SMIN,
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IMAGE_ATOMIC_UMIN,
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