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https://github.com/KytyPS5/KytyPS5.git
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shader_recompiler: add SSA
This commit is contained in:
nmzik
@@ -0,0 +1,260 @@
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#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail {
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bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
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const auto zero = IR::U32(IR::Value(0u));
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switch (inst.op) {
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case IR::Opcode::SaveexecB32:
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case IR::Opcode::SaveexecB64: {
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const auto old_low = ir.GetExecLo();
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const auto old_high = ir.GetExecHi();
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const auto src_low = ReadRawU32(inst.src[0]);
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const auto src_high = inst.op == IR::Opcode::SaveexecB64
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? ReadRawU32(OffsetOperand(inst.src[0], 1))
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: IR::U32(IR::Value(0u));
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const auto apply = [&](IR::U32 old_value, IR::U32 src_value) {
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switch (inst.saveexec_mode) {
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case IR::SaveexecMode::And: return ir.BitwiseAnd(old_value, src_value);
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case IR::SaveexecMode::Andn1:
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return ir.BitwiseAnd(old_value, ir.BitwiseNot(src_value));
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case IR::SaveexecMode::Orn2:
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return ir.BitwiseOr(ir.BitwiseNot(old_value), src_value);
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}
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return old_value;
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};
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const auto result_low = apply(old_low, src_low);
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const auto result_high =
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inst.op == IR::Opcode::SaveexecB64 ? apply(old_high, src_high) : old_high;
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if (inst.op == IR::Opcode::SaveexecB64) {
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WriteOperand(inst.dst, ir.PackUint2x32(old_low, old_high));
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} else {
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WriteOperand(inst.dst, old_low);
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}
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ir.SetExecLo(result_low);
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ir.SetExecHi(result_high);
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ir.SetExec(ThreadBit(result_low, result_high));
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const auto nonzero = inst.op == IR::Opcode::SaveexecB64
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? ir.BitwiseOr(result_low, result_high)
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: result_low;
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ir.SetScc(ir.INotEqual(nonzero, zero));
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return true;
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}
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case IR::Opcode::ScalarAddCarryU32:
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case IR::Opcode::IAddCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto carry_in = ConditionBit(inst.src[2]);
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const auto add0 = ir.Emit(IR::ValueOpcode::IAddCarry32, {lhs, rhs});
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const auto partial = ir.CompositeExtract(add0, 0);
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const auto carry0 = ir.CompositeExtract(add0, 1);
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const auto add1 = ir.Emit(IR::ValueOpcode::IAddCarry32, {partial, carry_in});
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const auto result = ir.CompositeExtract(add1, 0);
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const auto carry1 = ir.CompositeExtract(add1, 1);
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const auto carry = ir.INotEqual(ir.BitwiseOr(carry0, carry1), IR::U32(IR::Value(0u)));
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WriteOperand(inst.dst, result);
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if (inst.op == IR::Opcode::ScalarAddCarryU32) {
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ir.SetScc(carry);
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} else {
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WriteMask(inst.dst2, carry);
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}
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return true;
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}
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case IR::Opcode::ScalarSubBorrowU32:
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case IR::Opcode::ISubBorrowU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto result = ir.ISub(lhs, rhs);
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const auto borrow = ir.UGreaterThan(rhs, lhs);
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WriteOperand(inst.dst, result);
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if (inst.op == IR::Opcode::ScalarSubBorrowU32) {
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ir.SetScc(borrow);
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} else {
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WriteMask(inst.dst2, borrow);
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}
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return true;
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}
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case IR::Opcode::ScalarSubBorrowCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto borrow_in = ConditionBit(inst.src[2]);
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const auto partial = ir.ISub(lhs, rhs);
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const auto result = ir.ISub(partial, borrow_in);
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const auto borrow0 = ir.UGreaterThan(rhs, lhs);
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const auto borrow1 = ir.UGreaterThan(borrow_in, partial);
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WriteOperand(inst.dst, result);
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ir.SetScc(ir.LogicalOr(borrow0, borrow1));
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return true;
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}
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case IR::Opcode::ScalarSignedAddOverflowI32:
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case IR::Opcode::ScalarSignedSubOverflowI32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const bool subtract = inst.op == IR::Opcode::ScalarSignedSubOverflowI32;
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const auto result = subtract ? ir.ISub(lhs, rhs) : ir.IAdd(lhs, rhs);
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const auto shift = IR::U32(IR::Value(31u));
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const auto lhs_sign = ir.ShiftRightLogical(lhs, shift);
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const auto rhs_sign = ir.ShiftRightLogical(rhs, shift);
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const auto out_sign = ir.ShiftRightLogical(result, shift);
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const auto inputs =
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subtract ? ir.INotEqual(lhs_sign, rhs_sign) : ir.IEqual(lhs_sign, rhs_sign);
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const auto changed = ir.INotEqual(lhs_sign, out_sign);
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WriteOperand(inst.dst, result);
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ir.SetScc(ir.LogicalAnd(inputs, changed));
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return true;
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}
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case IR::Opcode::ScalarShiftLeftAddCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto shift = ReadU32(inst.src[1]);
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const auto rhs = ReadU32(inst.src[2]);
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const auto shifted = ir.ShiftLeftLogical(lhs, shift);
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const auto result = ir.IAdd(shifted, rhs);
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const auto add_carry = ir.ULessThan(result, shifted);
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const auto inverse_shift = ir.ISub(IR::U32(IR::Value(32u)), shift);
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const auto shifted_out = ir.ShiftRightLogical(lhs, inverse_shift);
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const auto shift_carry = ir.INotEqual(shifted_out, zero);
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WriteOperand(inst.dst, result);
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ir.SetScc(ir.LogicalOr(add_carry, shift_carry));
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return true;
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}
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default: return false;
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}
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}
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bool Translator::TranslateControlOperation(const IR::Instruction& inst) {
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switch (inst.op) {
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case IR::Opcode::ControlNop: ir.Emit(IR::ValueOpcode::ControlNop); return true;
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case IR::Opcode::Waitcnt: ir.Emit(IR::ValueOpcode::Waitcnt); return true;
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case IR::Opcode::Barrier: ir.Emit(IR::ValueOpcode::Barrier); return true;
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case IR::Opcode::Sendmsg: ir.Emit(IR::ValueOpcode::Sendmsg); return true;
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case IR::Opcode::TtraceData: ir.Emit(IR::ValueOpcode::TtraceData); return true;
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case IR::Opcode::InstPrefetch: ir.Emit(IR::ValueOpcode::InstPrefetch); return true;
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default: return false;
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}
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}
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bool Translator::TranslateMove(const IR::Instruction& inst) {
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switch (inst.op) {
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case IR::Opcode::MoveU32:
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if (inst.src[0].kind == IR::OperandKind::Register &&
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(inst.src[0].reg.file == IR::RegisterFile::Exec ||
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inst.src[0].reg.file == IR::RegisterFile::Vcc) &&
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inst.dst.kind == IR::OperandKind::Register &&
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(inst.dst.reg.file == IR::RegisterFile::Exec ||
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inst.dst.reg.file == IR::RegisterFile::Vcc)) {
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WriteMask(inst.dst, ReadMask(inst.src[0]));
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} else {
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WriteOperand(inst.dst, ReadOperand(inst.src[0], IR::Type::U32));
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}
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return true;
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case IR::Opcode::MoveF32Bits:
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WriteOperand(inst.dst, ReadOperand(inst.src[0], IR::Type::F32));
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return true;
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case IR::Opcode::MoveU64: {
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const bool scalar_pair = inst.dst.kind == IR::OperandKind::Register &&
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inst.src[0].kind == IR::OperandKind::Register &&
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inst.dst.reg.file == IR::RegisterFile::Scalar &&
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inst.src[0].reg.file == IR::RegisterFile::Scalar;
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WriteOperand(inst.dst, ReadOperand(inst.src[0], IR::Type::U64));
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if (scalar_pair) {
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ir.SetThreadBitScalarReg(
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static_cast<IR::ScalarReg>(inst.dst.reg.index),
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ir.GetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.src[0].reg.index)));
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}
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return true;
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}
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case IR::Opcode::WqmB64: {
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if (!current_per_invocation_masks && inst.dst.kind == IR::OperandKind::Register &&
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inst.dst.reg.file == IR::RegisterFile::Scalar) {
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const auto result =
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ExpandWholeQuadMask(IR::U64(ReadOperand(inst.src[0], IR::Type::U64)));
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WriteOperand(inst.dst, result);
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ir.SetScc(IR::U1(
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ir.Emit(IR::ValueOpcode::INotEqual64, {result, IR::Value(uint64_t {0})})));
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return true;
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}
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const auto result = IR::U1(ir.Emit(IR::ValueOpcode::WqmMask, {ReadMask(inst.src[0])}));
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WriteMask64(inst.dst, result);
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ir.SetScc(result);
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return true;
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}
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default: return false;
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}
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}
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bool Translator::TranslateLaneOperation(const IR::Instruction& inst) {
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const auto lane_mask = IR::U32(IR::Value(current_wave_size == 32u ? 31u : 63u));
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switch (inst.op) {
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case IR::Opcode::MoveRelSourceU32: {
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EXIT_IF(inst.src[0].kind != IR::OperandKind::Register ||
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inst.src[0].reg.file != IR::RegisterFile::Vector);
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const auto base = inst.src[0].reg.index;
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const auto m0 = ir.BitwiseAnd(ReadU32(inst.src[1]), IR::U32(IR::Value(0xffu)));
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auto selected = ir.GetVectorReg(static_cast<IR::VectorReg>(base));
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for (uint32_t index = base + 1u; index < current_vector_limit; index++) {
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const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
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selected =
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ir.Select(match, ir.GetVectorReg(static_cast<IR::VectorReg>(index)), selected);
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}
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WriteOperand(inst.dst, selected);
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return true;
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}
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case IR::Opcode::MoveRelDestU32: {
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EXIT_IF(inst.dst.kind != IR::OperandKind::Register ||
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inst.dst.reg.file != IR::RegisterFile::Vector);
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const auto base = inst.dst.reg.index;
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const auto value = ReadU32(inst.src[0]);
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const auto m0 = ir.BitwiseAnd(ReadU32(inst.src[1]), IR::U32(IR::Value(0xffu)));
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for (uint32_t index = base; index < current_vector_limit; index++) {
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const auto reg = static_cast<IR::VectorReg>(index);
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const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
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const auto write = ir.LogicalAnd(ir.GetExec(), match);
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ir.SetVectorReg(reg, ir.Select(write, value, ir.GetVectorReg(reg)));
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}
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return true;
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}
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case IR::Opcode::ReadFirstLaneU32: {
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const auto result =
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ir.Emit(IR::ValueOpcode::ReadFirstLane, {ReadU32(inst.src[0]), ir.GetExec()});
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WriteOperand(inst.dst, result);
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return true;
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}
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case IR::Opcode::ReadLaneU32: {
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const auto lane = ir.BitwiseAnd(ReadU32(inst.src[1]), lane_mask);
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WriteOperand(inst.dst,
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ir.Emit(IR::ValueOpcode::ReadLane, {ReadU32(inst.src[0]), lane}));
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return true;
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}
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case IR::Opcode::WriteLaneU32: {
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EXIT_IF(inst.dst.kind != IR::OperandKind::Register ||
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inst.dst.reg.file != IR::RegisterFile::Vector);
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const auto reg = static_cast<IR::VectorReg>(inst.dst.reg.index);
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const auto lane = ir.BitwiseAnd(ReadU32(inst.src[1]), lane_mask);
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const auto result = IR::U32(ir.Emit(
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IR::ValueOpcode::WriteLane, {ir.GetVectorReg(reg), ReadU32(inst.src[0]), lane}));
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// V_WRITELANE_B32 ignores EXEC; bypass the ordinary VGPR destination path.
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ir.SetVectorReg(reg, result);
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return true;
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}
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case IR::Opcode::Permlane16B32:
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case IR::Opcode::Permlanex16B32: {
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const IR::PermlaneFlags flags {
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.x16 = inst.op == IR::Opcode::Permlanex16B32,
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.fetch_inactive = inst.dst.op_sel,
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.bound_control = inst.dst.op_sel_hi,
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};
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const auto result = ir.Emit(
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IR::ValueOpcode::Permlane16U32,
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{ReadU32(inst.src[0]), ReadU32(inst.src[1]), ReadU32(inst.src[2]), ir.GetExec()},
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flags);
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auto dst = inst.dst;
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dst.op_sel = false;
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dst.op_sel_hi = false;
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WriteOperand(dst, result);
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return true;
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}
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default: return false;
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}
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail
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