diff --git a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp index aebff1f8e..9a2ae8d14 100644 --- a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp +++ b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterAlu.cpp @@ -255,14 +255,6 @@ uint32_t EmitUMulHi(EmitterState& state, uint32_t arg0, uint32_t arg1) { return EmitMulHigh(state, arg0, arg1, false); } -uint32_t EmitBitCount64(EmitterState& state, uint32_t arg0) { - // Vulkan bit-count operands remain 32-bit, including when counting a U64. - const auto unpacked = Unary(state, spv::OpBitcast, TypeU32Vector(state, 2), arg0); - const auto pair = - ExtractPair(state, Unary(state, spv::OpBitCount, TypeU32Vector(state, 2), unpacked)); - return Binary(state, spv::OpIAdd, TypeU32(state), pair.low, pair.high); -} - uint32_t EmitSMinTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) { return EmitSMin32(state, arg0, EmitSMin32(state, arg1, arg2)); } diff --git a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h index d28a14414..51cefcf86 100644 --- a/src/graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h +++ b/src/graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h @@ -62,7 +62,6 @@ EMIT_NATIVE(IMul32, OpIMul, U32, uint32_t, uint32_t) EMIT_NATIVE(UDiv32, OpUDiv, U32, uint32_t, uint32_t) EMIT_NATIVE(IAdd64, OpIAdd, U64, uint32_t, uint32_t) EMIT_NATIVE(ISub64, OpISub, U64, uint32_t, uint32_t) -EMIT_NATIVE(IMul64, OpIMul, U64, uint32_t, uint32_t) EMIT_NATIVE(IAddCarry32, OpIAddCarry, U32x2, uint32_t, uint32_t) uint32_t EmitSMulHi(EmitterState& state, uint32_t arg0, uint32_t arg1); uint32_t EmitUMulHi(EmitterState& state, uint32_t arg0, uint32_t arg1); @@ -92,7 +91,6 @@ EMIT_NATIVE(BitwiseNot32, OpNot, U32, uint32_t) EMIT_NATIVE(BitwiseAnd64, OpBitwiseAnd, U64, uint32_t, uint32_t) EMIT_NATIVE(BitReverse32, OpBitReverse, U32, uint32_t) EMIT_NATIVE(BitCount32, OpBitCount, U32, uint32_t) -uint32_t EmitBitCount64(EmitterState& state, uint32_t arg0); inline constexpr auto EmitFindILsb32 = EmitGlsl; inline constexpr auto EmitFindUMsb32 = EmitGlsl; uint32_t EmitFindUMsb64(EmitterState& state, uint32_t arg0); @@ -227,10 +225,7 @@ uint32_t EmitGetUserData(EmitterState& state, IR::ScalarReg reg); uint32_t EmitGetDispatchThreadExtent(ValueEmitContext& ctx, const IR::Inst& inst); uint32_t EmitGetBuiltin(ValueEmitContext& ctx, IR::Value kind, IR::Value index); uint32_t EmitUndefU1(EmitterState& state, const IR::Inst& inst); -inline constexpr auto EmitUndefU8 = EmitUndefU1; -inline constexpr auto EmitUndefU16 = EmitUndefU1; inline constexpr auto EmitUndefU32 = EmitUndefU1; -inline constexpr auto EmitUndefU64 = EmitUndefU1; uint32_t EmitDppMoveU32(ValueEmitContext& ctx, const IR::Inst& inst); uint32_t EmitDppUpdateU32(ValueEmitContext& ctx, const IR::Inst& inst); uint32_t EmitWqmU64(EmitterState& state, uint32_t value); diff --git a/src/graphics/shader/recompiler/frontend/translate/Integer.cpp b/src/graphics/shader/recompiler/frontend/translate/Integer.cpp index b5d067400..2a1532d14 100644 --- a/src/graphics/shader/recompiler/frontend/translate/Integer.cpp +++ b/src/graphics/shader/recompiler/frontend/translate/Integer.cpp @@ -277,7 +277,7 @@ void Translator::Integer24(const Decoder::Instruction& inst, bool sign, bool add void Translator::V_MAD_U64_U32(const Decoder::Instruction& inst) { const auto lhs = ReadU32(inst.src0); const auto rhs = ReadU32(inst.src1); - // Keep the 32x32 product in words: native widening IMul64 fails NVIDIA compilation + // Keep the 32x32 product in words: a native widening 64-bit multiply fails NVIDIA compilation // in large vertex shaders (Astro's Playroom). The 64-bit addition stays native. const auto product = ir.ConstructU64( ir.IMul(lhs, rhs), IR::U32(ir.Emit(IR::ValueOpcode::UMulHi, {lhs, rhs}))); diff --git a/src/graphics/shader/recompiler/ir/IREmitter.cpp b/src/graphics/shader/recompiler/ir/IREmitter.cpp index 50db3c27a..6b3c98315 100644 --- a/src/graphics/shader/recompiler/ir/IREmitter.cpp +++ b/src/graphics/shader/recompiler/ir/IREmitter.cpp @@ -6,11 +6,6 @@ IREmitter::IREmitter(Block* value_block): block(value_block) { EXIT_IF(block == nullptr); } -void IREmitter::SetBlock(Block* value_block) { - EXIT_IF(value_block == nullptr); - block = value_block; -} - Value IREmitter::Emit(ValueOpcode opcode, std::initializer_list args, uint64_t flags) { auto& inst = block->AppendNewInst(opcode, args, flags); return TypeOf(opcode) == Type::Void ? Value {} : Value(&inst); @@ -132,16 +127,6 @@ U32 IREmitter::BitCastU32(F32 value) { return U32(Emit(ValueOpcode::BitCastU32F32, {value})); } -F16 IREmitter::BitCastF16(U32 value) { - const auto half = U16(Emit(ValueOpcode::ConvertU16U32, {value})); - return F16(Emit(ValueOpcode::BitCastF16U16, {half})); -} - -U32 IREmitter::BitCastU32(F16 value) { - const auto half = U16(Emit(ValueOpcode::BitCastU16F16, {value})); - return U32(Emit(ValueOpcode::ConvertU32U16, {half})); -} - U64 IREmitter::ConstructU64(U32 low, U32 high) { return U64(Emit(ValueOpcode::CompositeConstructU64, {low, high})); } diff --git a/src/graphics/shader/recompiler/ir/IREmitter.h b/src/graphics/shader/recompiler/ir/IREmitter.h index e429ac04d..62b8e76ec 100644 --- a/src/graphics/shader/recompiler/ir/IREmitter.h +++ b/src/graphics/shader/recompiler/ir/IREmitter.h @@ -12,8 +12,6 @@ class IREmitter { public: explicit IREmitter(Block* block); - void SetBlock(Block* block); - Value Emit(ValueOpcode opcode, std::initializer_list args = {}, uint64_t flags = 0); template @@ -54,8 +52,6 @@ public: F32 BitCastF32(U32 value); U32 BitCastU32(F32 value); - F16 BitCastF16(U32 value); - U32 BitCastU32(F16 value); U64 ConstructU64(U32 low, U32 high); U32 CompositeExtract(Value composite, uint32_t index); diff --git a/src/graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc b/src/graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc index 9e7dacb2e..ff6a44c7e 100644 --- a/src/graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc +++ b/src/graphics/shader/recompiler/ir/opcodes/ValueOpcodes.inc @@ -44,10 +44,7 @@ VALUE_OPCODE(GetM0, U32) VALUE_OPCODE(SetM0, Void, U32) VALUE_OPCODE(UndefU1, U1) -VALUE_OPCODE(UndefU8, U8) -VALUE_OPCODE(UndefU16, U16) VALUE_OPCODE(UndefU32, U32) -VALUE_OPCODE(UndefU64, U64) // Value construction and bit-preserving conversion. VALUE_OPCODE(BitCastU16F16, U16, F16) @@ -104,7 +101,6 @@ VALUE_OPCODE(IAddCarry32, U32x2, U32, U32) VALUE_OPCODE(ISub32, U32, U32, U32) VALUE_OPCODE(ISub64, U64, U64, U64) VALUE_OPCODE(IMul32, U32, U32, U32) -VALUE_OPCODE(IMul64, U64, U64, U64) VALUE_OPCODE(UDiv32, U32, U32, U32) VALUE_OPCODE(SMulHi, U32, U32, U32) VALUE_OPCODE(UMulHi, U32, U32, U32) @@ -122,7 +118,6 @@ VALUE_OPCODE(BitwiseXor32, U32, U32, U32) VALUE_OPCODE(BitwiseNot32, U32, U32) VALUE_OPCODE(BitReverse32, U32, U32) VALUE_OPCODE(BitCount32, U32, U32) -VALUE_OPCODE(BitCount64, U32, U64) VALUE_OPCODE(FindUMsb32, U32, U32) VALUE_OPCODE(FindUMsb64, U32, U64) VALUE_OPCODE(FindILsb32, U32, U32) diff --git a/src/graphics/shader/recompiler/ir/passes/ConstantPropagation.cpp b/src/graphics/shader/recompiler/ir/passes/ConstantPropagation.cpp index 4090202a9..44dba865e 100644 --- a/src/graphics/shader/recompiler/ir/passes/ConstantPropagation.cpp +++ b/src/graphics/shader/recompiler/ir/passes/ConstantPropagation.cpp @@ -511,11 +511,6 @@ void FoldInstruction(Block& block, Block::iterator instruction, ReplaceBinaryIdentity(inst, Type::U32, 1u); } return; - case ValueOpcode::IMul64: - if (!FoldU64(inst, [](uint64_t a, uint64_t b) { return a * b; })) { - ReplaceBinaryIdentity(inst, Type::U64, 1u); - } - return; case ValueOpcode::WqmU64: { const auto value = Arg(inst, 0); if (IsImmediate(value, Type::U64)) { @@ -674,13 +669,6 @@ void FoldInstruction(Block& block, Block::iterator instruction, } return; } - case ValueOpcode::BitCount64: { - const auto value = Arg(inst, 0); - if (IsImmediate(value, Type::U64)) { - Replace(inst, Value(static_cast(std::popcount(value.U64())))); - } - return; - } case ValueOpcode::SMin32: case ValueOpcode::SMax32: FoldU32(inst, [opcode = inst.GetOpcode()](uint32_t a, uint32_t b) { diff --git a/src/graphics/shader/recompiler/ir/passes/SrtWalker.cpp b/src/graphics/shader/recompiler/ir/passes/SrtWalker.cpp index 05e7c3b10..e2f940f11 100644 --- a/src/graphics/shader/recompiler/ir/passes/SrtWalker.cpp +++ b/src/graphics/shader/recompiler/ir/passes/SrtWalker.cpp @@ -138,7 +138,6 @@ bool IsRuntimeUniformOp(ValueOpcode op) { case ValueOpcode::ISub32: case ValueOpcode::ISub64: case ValueOpcode::IMul32: - case ValueOpcode::IMul64: case ValueOpcode::UMulHi: case ValueOpcode::UMin32: case ValueOpcode::UMax32: @@ -259,9 +258,7 @@ private: } return finish(Validate(inst->Arg(1))); } - if (op == ValueOpcode::UndefU1 || op == ValueOpcode::UndefU8 || - op == ValueOpcode::UndefU16 || op == ValueOpcode::UndefU32 || - op == ValueOpcode::UndefU64 || op == ValueOpcode::Void) { + if (op == ValueOpcode::UndefU1 || op == ValueOpcode::UndefU32 || op == ValueOpcode::Void) { return finish(false); } if (op == ValueOpcode::GetUserData) { @@ -832,12 +829,6 @@ bool SrtWalker::EvaluateInst(const Inst& inst, uint64_t& result) { return true; } return false; - case ValueOpcode::IMul64: - if (binary()) { - result = a * b; - return true; - } - return false; case ValueOpcode::UMulHi: if (binary()) { result = (static_cast(static_cast(a)) * static_cast(b)) >> 32u; @@ -1143,10 +1134,7 @@ bool SrtWalker::EvaluateInst(const Inst& inst, uint64_t& result) { } return false; case ValueOpcode::UndefU1: - case ValueOpcode::UndefU8: - case ValueOpcode::UndefU16: - case ValueOpcode::UndefU32: - case ValueOpcode::UndefU64: return false; + case ValueOpcode::UndefU32: return false; default: break; } return false; diff --git a/tests/shaderCfgTests.cpp b/tests/shaderCfgTests.cpp index cedced11f..e546262e6 100644 --- a/tests/shaderCfgTests.cpp +++ b/tests/shaderCfgTests.cpp @@ -10429,14 +10429,12 @@ void TestNewShaderRecompilerNativeU64Translation() { ir.Emit(IR::ValueOpcode::BitwiseAnd64, {base, IR::Value(uint64_t{0xff00ff00ff00ff00ull})}); const auto sum = ir.Emit(IR::ValueOpcode::IAdd64, {masked, base}); - const auto product = ir.Emit(IR::ValueOpcode::IMul64, {sum, base}); const auto shifted = - ir.Emit(IR::ValueOpcode::ShiftRightArithmetic64, {product, lane}); + ir.Emit(IR::ValueOpcode::ShiftRightArithmetic64, {sum, lane}); ir.Emit(IR::ValueOpcode::IEqual64, {shifted, base}); ir.Emit(IR::ValueOpcode::INotEqual64, {shifted, base}); ir.Emit(IR::ValueOpcode::ULessThan64, {shifted, base}); ir.Emit(IR::ValueOpcode::SLessThan64, {shifted, base}); - ir.Emit(IR::ValueOpcode::BitCount64, {shifted}); for (const uint32_t count : {1u, 31u, 32u, 33u, 63u}) { ir.Emit(IR::ValueOpcode::ShiftLeftLogical64, {base, IR::Value(count)}); ir.Emit(IR::ValueOpcode::ShiftRightLogical64, {base, IR::Value(count)}); @@ -10451,7 +10449,6 @@ void TestNewShaderRecompilerNativeU64Translation() { Check(source.find("OpCapability Int64") != std::string::npos && source.find("OpTypeInt 64 0") != std::string::npos && SpirvSourceHasInstructionUsing(source, "OpIAdd", "%ulong") && - SpirvSourceHasInstructionUsing(source, "OpIMul", "%ulong") && SpirvSourceHasInstructionUsing(source, "OpBitwiseAnd", "%ulong"), "U64 arithmetic did not emit native 64-bit scalar instructions"); Check(SpirvInstructionOpcodeCount(spirv, spv::OpIAddCarry) == 0u &&