mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 10:56:58 +02:00
refactor(shader): remove register-state compatibility paths
This commit is contained in:
nmzik
+144
-108
@@ -15,6 +15,7 @@
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#include "graphics/shader/recompiler/frontend/cfg/ShaderCFG.h"
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#include "graphics/shader/recompiler/frontend/decode/ShaderDecoder.h"
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#include "graphics/shader/recompiler/frontend/translate/Translate.h"
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#include "graphics/shader/recompiler/ir/IREmitter.h"
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#include "graphics/shader/recompiler/ir/ShaderIR.h"
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#include "graphics/shader/recompiler/ir/ValueProgram.h"
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#include "graphics/shader/recompiler/ir/passes/ConstantPropagation.h"
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@@ -7506,93 +7507,6 @@ void TestComputeShaderInputWaveSize() {
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"cleared COMPUTE_PGM_RSRC1 W32_EN bit did not decode as wave64");
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}
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void TestNewShaderRecompilerWave32MasksExecHighStores() {
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const uint32_t shader[] = {
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EncodeSop1(0x04, 126, 193), // s_mov_b64 exec, -1
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EncodeSopp(0x01),
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};
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auto options = MakeCompileOptions(ShaderType::Compute);
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options.dump_ir = true;
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options.wave_size = 32;
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ShaderRecompiler::CompileResult result;
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std::string error;
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Check(ShaderRecompiler::TryRecompile(shader, options, result, &error),
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error.c_str());
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Check(Common::ContainsStr(result.decoded_dump, "s_mov_b64 exec_lo, -1"),
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"wave32 EXEC mask regression did not decode s_mov_b64 exec, -1");
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(CountSourceOccurrences(source, "OpStore %exec_hi %uint_0") >= 2u,
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"wave32 EXEC high half was not clamped to zero in SPIR-V stores");
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Check(!Common::ContainsStr(source, "OpStore %exec_hi %uint_4294967295"),
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"wave32 EXEC high half was stored as a full 64-lane mask");
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}
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void TestNewShaderRecompilerWave32VccHighScalarStores() {
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const uint32_t shader[] = {
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EncodeSmem0(0x09, 106, 4),
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0u, // s_buffer_load_dwordx2 vcc_lo
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EncodeSopp(0x01),
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};
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auto options = MakeCompileOptions(ShaderType::Compute);
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options.dump_ir = true;
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options.wave_size = 32;
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ShaderRecompiler::CompileResult result;
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std::string error;
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Check(ShaderRecompiler::TryRecompile(shader, options, result, &error),
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error.c_str());
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Check(Common::ContainsStr(result.ir_dump, "SBufferLoadDword vcc_hi"),
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"wave32 VCC scalar regression did not lower the high VCC dword load");
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(CountSourceOccurrences(source, "OpStore %vcc_hi") >= 2u,
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"wave32 VCC high scalar load did not store to vcc_hi");
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Check(CountSourceOccurrences(source, "OpStore %vcc_hi %uint_0") == 1u,
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"wave32 VCC high scalar load was clamped to zero instead of preserving "
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"data");
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}
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void TestNewShaderRecompilerCompareMaskIsFullWaveBallot() {
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const uint32_t shader[] = {
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EncodeVopc(0xc1, 0 + 256, 1), // v_cmp_lt_u32 vcc, v0, v1
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EncodeSop2(0x0f, 2, 126, 106), // s_and_b64 s[2:3], exec, vcc
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EncodeSop1(0x04, 126, 2), // s_mov_b64 exec, s[2:3]
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EncodeSopp(0x01),
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};
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auto options = MakeCompileOptions(ShaderType::Compute);
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options.dump_ir = true;
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options.wave_size = 32;
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ShaderRecompiler::CompileResult result;
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std::string error;
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Check(ShaderRecompiler::TryRecompile(shader, options, result, &error),
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error.c_str());
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Check(Common::ContainsStr(result.decoded_dump, "v_cmp_lt_u32"),
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"compare-mask ballot regression did not decode V_CMP_LT_U32");
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Check(Common::ContainsStr(result.ir_dump, "CompareLtU32 vcc_lo"),
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"compare-mask ballot regression did not lower compare to VCC");
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Check(
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Common::ContainsStr(result.ir_dump, "BitwiseAndU64 s2, exec_lo, vcc_lo"),
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"compare-mask ballot regression did not consume VCC through scalar mask "
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"ALU");
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(Common::ContainsStr(source, "OpGroupNonUniformBallot"),
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"compare-mask result was not materialized with a subgroup ballot");
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Check(Common::ContainsStr(source, "OpStore %vcc_lo"),
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"compare-mask ballot regression did not store VCC low mask");
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Check(Common::ContainsStr(source, "OpStore %vcc_hi %uint_0"),
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"wave32 compare-mask VCC high half was not cleared");
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}
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void TestNewShaderRecompilerBufferLoadsGuardedByExec() {
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const uint32_t shader[] = {
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EncodeMubuf0(0x0c),
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@@ -7885,9 +7799,119 @@ void TestNewShaderRecompilerExpVertexOutputs() {
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CheckSpirvBinaryValidates(result.spirv);
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}
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void TestTypedEntryStateIsMinimal() {
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using namespace ShaderRecompiler;
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const auto translate = [](ShaderLaneMaskMode lane_mode, uint32_t wave_size) {
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IR::Program source;
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source.stage = ShaderType::Compute;
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source.lane_mask_mode = lane_mode;
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source.wave_size = wave_size;
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source.user_data_count = 0;
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source.blocks.emplace_back();
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source.blocks.front().id = 0;
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source.blocks.front().terminator.kind = CFG::TerminatorKind::Return;
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IR::ValueProgram values;
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ShaderComputeInputInfo compute{};
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std::string error;
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Check(Frontend::TranslateProgram(source, values, nullptr, nullptr, &compute,
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&error),
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error.c_str());
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return values;
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};
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const auto check = [&](ShaderLaneMaskMode lane_mode, uint32_t wave_size) {
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auto values = translate(lane_mode, wave_size);
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uint32_t set_exec = 0;
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uint32_t set_exec_lo = 0;
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uint32_t set_exec_hi = 0;
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IR::Value exec;
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IR::Value exec_lo;
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IR::Value exec_hi;
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for (const auto *block : values.blocks) {
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for (const auto &inst : *block) {
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switch (inst.GetOpcode()) {
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case IR::ValueOpcode::SetExec:
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set_exec++;
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exec = inst.Arg(0).Resolve();
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break;
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case IR::ValueOpcode::SetExecLo:
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set_exec_lo++;
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exec_lo = inst.Arg(0).Resolve();
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break;
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case IR::ValueOpcode::SetExecHi:
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set_exec_hi++;
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exec_hi = inst.Arg(0).Resolve();
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break;
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case IR::ValueOpcode::SetScalarRegister:
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case IR::ValueOpcode::SetThreadBitScalarRegister:
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case IR::ValueOpcode::SetVectorRegister:
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case IR::ValueOpcode::SetScc:
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case IR::ValueOpcode::SetVcc:
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case IR::ValueOpcode::SetVccLo:
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case IR::ValueOpcode::SetVccHi:
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case IR::ValueOpcode::SetM0:
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Check(false, "minimal typed entry contains redundant state writes");
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break;
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default:
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break;
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}
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}
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}
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Check(set_exec == 1u && set_exec_lo == 1u && set_exec_hi == 1u &&
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exec.IsImmediate() && exec.U1(),
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"typed entry does not define EXEC exactly once");
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if (lane_mode == ShaderLaneMaskMode::PerInvocation) {
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Check(exec_lo.IsImmediate() && exec_lo.U32() == 1u &&
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exec_hi.IsImmediate() && exec_hi.U32() == 0u,
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"per-invocation entry EXEC is not the local {1,0} mask");
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} else {
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Check(exec_lo.IsImmediate() && exec_lo.U32() == 0xffffffffu &&
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exec_hi.IsImmediate() &&
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exec_hi.U32() == (wave_size == 32u ? 0u : 0xffffffffu),
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"native entry EXEC does not match the guest wave width");
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}
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IR::RewriteToSsa(values.blocks);
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IR::RemoveIdentities(values.blocks);
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IR::EliminateDeadCode(values.blocks);
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std::string error;
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Check(IR::ValidateValueProgram(values, true, &error), error.c_str());
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};
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check(ShaderLaneMaskMode::NativeWave, 32u);
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check(ShaderLaneMaskMode::NativeWave, 64u);
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check(ShaderLaneMaskMode::PerInvocation, 64u);
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}
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void TestFinalSsaRejectsRegisterStatePseudos() {
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using namespace ShaderRecompiler::IR;
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const auto check_rejected = [](bool setter) {
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ValueProgram program;
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program.block_storage.push_back(std::make_unique<Block>());
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program.blocks.push_back(program.block_storage.back().get());
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program.block_info.emplace_back();
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IREmitter ir(program.blocks.front());
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if (setter) {
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ir.SetScalarReg(ScalarReg{0}, U32(Value(1u)));
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} else {
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ir.Emit(ValueOpcode::ReferenceU32, {ir.GetScalarReg(ScalarReg{0})});
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}
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std::string error;
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Check(!ValidateValueProgram(program, true, &error) &&
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Common::ContainsStr(error, "register-state pseudo"),
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"final SSA accepted a register-state pseudo operation");
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};
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check_rejected(false);
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check_rejected(true);
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}
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void TestNewShaderRecompilerZeroInitialRegisterState() {
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const uint32_t shader[] = {
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EncodeVop1(0x01, 0, 0), // v_mov_b32 v0, s0
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EncodeVop1(0x01, 0, 100), // v_mov_b32 v0, s100
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EncodeExp0(0x0c, 0xf),
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EncodeExp1(0, 1, 2, 3), // POS0
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EncodeSopp(0x01),
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@@ -7901,14 +7925,31 @@ void TestNewShaderRecompilerZeroInitialRegisterState() {
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Check(ShaderRecompiler::TryRecompile(shader, options, result, &error),
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error.c_str());
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Check(!Common::ContainsStr(result.ir_dump, "UndefU32"),
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"typed prologue left guest registers undefined");
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"SSA initial state left guest registers undefined");
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const auto source = DisassembleSpirvBinary(result.spirv);
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Check(!Common::ContainsStr(source, "OpUndef"),
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"zero-initialized guest registers became SPIR-V undef values");
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Check(!Common::ContainsStr(source, "%s100") &&
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!Common::ContainsStr(source, "%v0"),
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"final SPIR-V retained a guest register mirror");
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CheckSpirvBinaryValidates(result.spirv);
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const uint32_t explicit_zero_shader[] = {
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EncodeSMovB32(100, 128), // s_mov_b32 s100, 0
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EncodeVop1(0x01, 0, 100), // v_mov_b32 v0, s100
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EncodeExp0(0x0c, 0xf),
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EncodeExp1(0, 1, 2, 3), // POS0
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EncodeSopp(0x01),
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};
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ShaderRecompiler::CompileResult explicit_zero;
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Check(ShaderRecompiler::TryRecompile(explicit_zero_shader, options,
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explicit_zero, &error),
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error.c_str());
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Check(result.spirv == explicit_zero.spirv,
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"implicit and explicit zero register state emitted different SPIR-V");
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}
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void TestNewShaderRecompilerVertexSystemVgprs() {
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void TestNewShaderRecompilerVertexSystemInputsWithoutMirrors() {
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using StageInputKind = ShaderRecompiler::IR::StageInputKind;
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const uint32_t shader[] = {
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@@ -7932,10 +7973,6 @@ void TestNewShaderRecompilerVertexSystemVgprs() {
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"vertex shader missing VertexIndex input");
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Check(ProgramHasInput(result.program, StageInputKind::InstanceIndex),
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"vertex shader missing InstanceIndex input");
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Check(Common::ContainsStr(result.ir_dump, "MoveU32 v0, v5"),
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"vertex shader did not keep v5 as a guest VGPR source");
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Check(Common::ContainsStr(result.ir_dump, "MoveU32 v1, v8"),
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"vertex shader did not keep v8 as a guest VGPR source");
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CheckSpirvBinaryValidates(result.spirv);
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const auto source = DisassembleSpirvBinary(result.spirv);
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@@ -7943,10 +7980,9 @@ void TestNewShaderRecompilerVertexSystemVgprs() {
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"vertex SPIR-V does not load gl_VertexIndex");
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Check(CountSourceOccurrences(source, "OpLoad %int %gl_InstanceIndex") == 1u,
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"vertex SPIR-V does not load gl_InstanceIndex");
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Check(CountSourceOccurrences(source, "OpStore %v5") >= 2u,
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"vertex SPIR-V does not seed guest v5 from gl_VertexIndex");
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Check(CountSourceOccurrences(source, "OpStore %v8") >= 2u,
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"vertex SPIR-V does not seed guest v8 from gl_InstanceIndex");
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Check(!Common::ContainsStr(source, "%v5") &&
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!Common::ContainsStr(source, "%v8"),
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"vertex system values were routed through guest VGPR mirrors");
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}
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void TestNewShaderRecompilerVertexExportUsesLaneExecMask() {
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@@ -7988,9 +8024,9 @@ void TestNewShaderRecompilerVertexExportUsesLaneExecMask() {
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"per-invocation vertex export lost its EXEC guard");
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}
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void TestNewShaderRecompilerPerInvocationMasks() {
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void TestNewShaderRecompilerPerInvocationMasksWithoutMirrors() {
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const uint32_t local_shader[] = {
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EncodeVopc(0xc1, 0 + 256, 1), // v_cmp_lt_u32 vcc, v0, v1
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EncodeVopc(0xc1, 5 + 256, 8), // v_cmp_lt_u32 vcc, v5, v8
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EncodeSop2(0x0f, 2, 126, 106), // s_and_b64 s[2:3], exec, vcc
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EncodeSop1(0x24, 4, 126), // s_and_saveexec_b64 s[4:5], exec
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EncodeSop2(0x25, 126, 132, 128), // s_bfm_b64 exec, 4, 0
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@@ -8016,17 +8052,13 @@ void TestNewShaderRecompilerPerInvocationMasks() {
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"per-invocation VCC producer still materialized a shared subgroup mask");
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Check(!Common::ContainsStr(source, "OpLoad %uint %gl_SubgroupInvocationID"),
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"per-invocation BFM EXEC prefix still selected native subgroup lanes");
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Check(Common::ContainsStr(source, "OpLogicalAnd") &&
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Common::ContainsStr(source, "OpLogicalNot"),
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"per-invocation wide mask ALU did not use Boolean operations");
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Check(Common::ContainsStr(source, "OpStore %vcc_lo") &&
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Common::ContainsStr(source, "OpStore %vcc_hi %uint_0"),
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"per-invocation comparison did not store a local Boolean VCC pair");
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Check(Common::ContainsStr(result.ir_dump, "SaveexecB64 s4, exec_lo"),
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"per-invocation SAVEEXEC regression did not reach IR");
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Check(!Common::ContainsStr(source, "%vcc_lo") &&
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!Common::ContainsStr(source, "%vcc_hi"),
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"per-invocation comparison retained VCC register mirrors");
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const uint32_t wqm_shader[] = {
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EncodeSop1(0x0a, 2, 126), // s_wqm_b64 s[2:3], exec
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EncodeVop1(0x01, 0, 2), // v_mov_b32 v0, s2
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EncodeExp0(0x0c, 0xf),
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EncodeExp1(0, 1, 2, 3), // POS0
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EncodeSopp(0x01),
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@@ -9760,8 +9792,12 @@ int main() {
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TestNewShaderRecompilerSetpcBranch();
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TestNewShaderRecompilerSetpcJumpTable();
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TestNewShaderRecompilerSetpcDwordJumpTable();
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TestTypedEntryStateIsMinimal();
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TestFinalSsaRejectsRegisterStatePseudos();
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TestNewShaderRecompilerZeroInitialRegisterState();
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TestNewShaderRecompilerVertexSystemInputsWithoutMirrors();
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TestNewShaderRecompilerVertexExportUsesLaneExecMask();
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TestNewShaderRecompilerPerInvocationMasksWithoutMirrors();
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TestNewShaderRecompilerPerInvocationU64Complement();
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TestNewShaderRecompilerExpPixelOutputs();
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TestRenderTargetReverseExportMapping();
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