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https://github.com/KytyPS5/KytyPS5.git
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shader: clamp V_FRACT_F16/F32/F64 results below one
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@@ -1,6 +1,7 @@
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#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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#include <array>
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#include <bit>
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#include <utility>
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namespace Libs::Graphics::ShaderRecompiler::Frontend {
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@@ -118,6 +119,33 @@ void Translator::FloatUnary(const Decoder::Instruction& inst, IR::ValueOpcode op
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {ReadOperand(inst.src0, type)}));
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}
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void Translator::V_FRACT(const Decoder::Instruction& inst, IR::Type type) {
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// x - floor(x) rounds to 1.0 for a tiny negative x; v_fract returns the largest value below
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// one instead. The ordered compare lets NaN through.
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const auto destination = DestinationOperand(inst);
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if (type == IR::Type::F64) {
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const auto result = ir.Emit(IR::ValueOpcode::FPFract64, {ReadOperand(inst.src0, type)});
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const auto below_one = ir.Emit(IR::ValueOpcode::BitCastF64U64,
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{IR::Value(uint64_t {0x3fefffffffffffff})});
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const auto above = ir.Emit(IR::ValueOpcode::FPOrdGreaterThan64, {result, below_one});
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WriteOperand(destination, ir.Emit(IR::ValueOpcode::SelectF64, {above, below_one, result}));
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return;
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}
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const bool half = type == IR::Type::F16;
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const auto source = half ? ReadF16AsF32(inst.src0) : IR::F32(ReadOperand(inst.src0, type));
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const auto result = IR::F32(ir.Emit(IR::ValueOpcode::FPFract32, {source}));
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// Clamp in the destination precision: 0x3f7fe000 is the half 0x3bff.
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const auto below_one =
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IR::F32(IR::Value::F32(std::bit_cast<float>(half ? 0x3f7fe000u : 0x3f7fffffu)));
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const auto above = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThan32, {result, below_one}));
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const auto clamped = SelectF32(above, below_one, result);
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if (half) {
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WriteF16(destination, clamped);
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} else {
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WriteOperand(destination, clamped);
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}
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}
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void Translator::FloatBinary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool reverse) {
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std::array<IR::Value, 2> args;
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@@ -153,6 +153,7 @@ private:
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void Float16Ternary(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool accumulator,
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bool mix);
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void FloatUnary(const Decoder::Instruction& inst, IR::ValueOpcode opcode);
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void V_FRACT(const Decoder::Instruction& inst, IR::Type type);
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void FloatBinary(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool reverse);
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void FloatTernary(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool accumulator,
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bool mix);
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@@ -563,7 +563,7 @@ void Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_CEIL_F16: return Float16Unary(inst, IR::ValueOpcode::FPCeil32, false);
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case O::V_TRUNC_F16: return Float16Unary(inst, IR::ValueOpcode::FPTrunc32, false);
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case O::V_RNDNE_F16: return Float16Unary(inst, IR::ValueOpcode::FPRoundEven32, false);
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case O::V_FRACT_F16: return Float16Unary(inst, IR::ValueOpcode::FPFract32, false);
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case O::V_FRACT_F16: return V_FRACT(inst, IR::Type::F16);
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case O::V_SIN_F16: return Float16Trig(inst, IR::ValueOpcode::FPSin);
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case O::V_COS_F16: return Float16Trig(inst, IR::ValueOpcode::FPCos);
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case O::V_MIN3_F16: return Float16Ternary(inst, IR::ValueOpcode::FPMinTri32, false, false);
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@@ -574,8 +574,8 @@ void Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_RCP_F32: return FloatUnary(inst, IR::ValueOpcode::FPRecip32);
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case O::V_RCP_F64: return FloatUnary(inst, IR::ValueOpcode::FPRecip64);
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case O::V_RCP_IFLAG_F32: return FloatUnary(inst, IR::ValueOpcode::FPRecipIFlag32);
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case O::V_FRACT_F32: return FloatUnary(inst, IR::ValueOpcode::FPFract32);
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case O::V_FRACT_F64: return FloatUnary(inst, IR::ValueOpcode::FPFract64);
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case O::V_FRACT_F32: return V_FRACT(inst, IR::Type::F32);
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case O::V_FRACT_F64: return V_FRACT(inst, IR::Type::F64);
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case O::V_TRUNC_F32: return FloatUnary(inst, IR::ValueOpcode::FPTrunc32);
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case O::V_TRUNC_F64: return FloatUnary(inst, IR::ValueOpcode::FPTrunc64);
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case O::V_CEIL_F32: return FloatUnary(inst, IR::ValueOpcode::FPCeil32);
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