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shader: add missing RDNA2 ALU opcodes

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Add missing scalar and vector opcodes with compute tests.

Original work by @Pouare514 in #176.

Co-authored-by: Pouare514 <julienaulycee@gmail.com>
This commit is contained in:
nmzik
2026-09-02 01:55:48 +04:00
parent 04b404f3c9
commit e9425e101d
10 changed files with 175 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/graphics/shader/recompiler/frontend/decode/ScalarAluOps.cpp
+6 -1
View File
@@ -27,7 +27,8 @@ constexpr OpcodeMap SOP2_OPCODE_LIST[] = {
{0x22u, Opcode::S_ASHR_I32}, {0x24u, Opcode::S_BFM_B32},
{0x25u, Opcode::S_BFM_B64}, {0x26u, Opcode::S_MUL_I32},
{0x27u, Opcode::S_BFE_U32}, {0x28u, Opcode::S_BFE_I32},
{0x29u, Opcode::S_BFE_U64}, {0x2eu, Opcode::S_LSHL1_ADD_U32},
{0x29u, Opcode::S_BFE_U64}, {0x2cu, Opcode::S_ABSDIFF_I32},
{0x2eu, Opcode::S_LSHL1_ADD_U32},
{0x2fu, Opcode::S_LSHL2_ADD_U32}, {0x30u, Opcode::S_LSHL3_ADD_U32},
{0x31u, Opcode::S_LSHL4_ADD_U32}, {0x32u, Opcode::S_PACK_LL_B32_B16},
{0x33u, Opcode::S_PACK_LH_B32_B16}, {0x34u, Opcode::S_PACK_HH_B32_B16},
@@ -48,7 +49,9 @@ constexpr OpcodeMap SOP1_OPCODE_LIST[] = {
{0x15u, Opcode::S_FLBIT_I32_B32},
{0x16u, Opcode::S_FLBIT_I32_B64},
{0x1bu, Opcode::S_BITSET0_B32},
{0x1cu, Opcode::S_BITSET0_B64},
{0x1du, Opcode::S_BITSET1_B32},
{0x1eu, Opcode::S_BITSET1_B64},
{0x1fu, Opcode::S_GETPC_B64},
{0x20u, Opcode::S_SETPC_B64},
{0x24u, Opcode::S_AND_SAVEEXEC_B64},
@@ -93,6 +96,7 @@ constexpr OpcodeMap SOPP_OPCODE_LIST[] = {
{0x0au, Opcode::S_BARRIER},
{0x0cu, Opcode::S_WAITCNT},
{0x0eu, Opcode::S_SLEEP},
{0x0fu, Opcode::S_SETPRIO},
{0x10u, Opcode::S_SENDMSG},
{0x12u, Opcode::S_TRAP},
{0x16u, Opcode::S_TTRACEDATA},
@@ -276,6 +280,7 @@ void DecodeSopp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
: static_cast<int32_t>(static_cast<int16_t>(simm));
inst.src_count = (inst.opcode == Opcode::S_NOP || inst.opcode == Opcode::S_WAITCNT ||
inst.opcode == Opcode::S_WAITCNT_DEPCTR || inst.opcode == Opcode::S_SLEEP ||
inst.opcode == Opcode::S_SETPRIO ||
inst.opcode == Opcode::S_SENDMSG || inst.opcode == Opcode::S_TRAP ||
inst.opcode == Opcode::S_TTRACEDATA || inst.opcode == Opcode::S_INST_PREFETCH)
? 1
src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.cpp
+3
View File
@@ -479,6 +479,8 @@ std::string InstructionToString(const Instruction& inst) {
case Opcode::S_FLBIT_I32_B32:
case Opcode::S_FF1_I32_B32:
case Opcode::S_FF1_I32_B64:
case Opcode::S_BITSET0_B64:
case Opcode::S_BITSET1_B64:
case Opcode::S_NOT_B64:
case Opcode::S_WQM_B64:
case Opcode::S_QUADMASK_B64:
@@ -505,6 +507,7 @@ std::string InstructionToString(const Instruction& inst) {
case Opcode::S_WAITCNT:
case Opcode::S_WAITCNT_DEPCTR:
case Opcode::S_SLEEP:
case Opcode::S_SETPRIO:
case Opcode::S_TRAP:
case Opcode::S_SENDMSG:
case Opcode::S_TTRACEDATA:
src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.h
+5
View File
@@ -40,6 +40,7 @@ enum class Opcode {
S_MOV_B64,
S_MOVK_I32,
S_ABS_I32,
S_ABSDIFF_I32,
S_BREV_B32,
S_BCNT1_I32_B32,
S_BCNT1_I32_B64,
@@ -69,6 +70,8 @@ enum class Opcode {
S_BITCMP1_B32,
S_BITSET0_B32,
S_BITSET1_B32,
S_BITSET0_B64,
S_BITSET1_B64,
S_MIN_I32,
S_MAX_I32,
S_MIN_U32,
@@ -108,6 +111,7 @@ enum class Opcode {
S_BFM_B64,
S_CSELECT_B32,
S_CSELECT_B64,
S_SETPRIO,
S_PACK_LL_B32_B16,
S_PACK_LH_B32_B16,
S_PACK_HH_B32_B16,
@@ -282,6 +286,7 @@ enum class Opcode {
V_MAD_MIXHI_F16,
V_ADD_NC_U32,
V_ADDC_U32,
V_SUB_CO_CI_U32,
V_SUBREV_CO_CI_U32,
V_SUB_NC_U32,
V_SUBREV_NC_U32,
src/graphics/shader/recompiler/frontend/decode/VectorAluOps.cpp
+3
View File
@@ -61,6 +61,7 @@ constexpr Vop2OpcodeInfo VOP2_OPCODE_LIST[] = {
{0x24u, Opcode::V_MBCNT_HI_U32_B32},
{0x25u, Opcode::V_ADD_NC_U32, Vop2SdwaProfile::IntegerPartialDestination},
{0x28u, Opcode::V_ADDC_U32, Vop2SdwaProfile::IntegerFullDestination},
{0x29u, Opcode::V_SUB_CO_CI_U32},
{0x2au, Opcode::V_SUBREV_CO_CI_U32},
{0x26u, Opcode::V_SUB_NC_U32, Vop2SdwaProfile::IntegerPartialDestination},
{0x27u, Opcode::V_SUBREV_NC_U32, Vop2SdwaProfile::IntegerFullDestination},
@@ -1033,6 +1034,7 @@ void FinalizeVop2Instruction(std::span<const uint32_t> code, uint32_t word_index
inst.src_count = 3;
break;
case Opcode::V_ADDC_U32:
case Opcode::V_SUB_CO_CI_U32:
case Opcode::V_SUBREV_CO_CI_U32:
inst.dst2.kind = OperandKind::VccLo;
inst.src2.kind = OperandKind::VccLo;
@@ -1643,6 +1645,7 @@ void DecodeVop3(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
SetRawWords(inst, code, word_index, 2);
const bool carry_in_out = (inst.opcode == Opcode::V_ADDC_U32 && opcode == 0x128u) ||
(inst.opcode == Opcode::V_SUB_CO_CI_U32 && opcode == 0x129u) ||
(inst.opcode == Opcode::V_SUBREV_CO_CI_U32 && opcode == 0x12au);
const bool vop3b_carry_out = IsVop3BCarryOutOpcode(inst.opcode);
const bool vop3b_mad_u64 = IsVop3BMadU64Opcode(inst.opcode);