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shader: V_MAD_I16

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This commit is contained in:
nmzik
2026-09-19 04:43:48 +04:00
parent 5b7d3343cf
commit ea6aae8577
6 changed files with 84 additions and 3 deletions
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src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.h
+1
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@@ -228,6 +228,7 @@ enum class Opcode {
V_CVT_PKRTZ_F16_F32,
V_CVT_PK_U8_F32,
V_MAD_F32,
V_MAD_I16,
V_MAD_I32_I24,
V_MAD_U32_U24,
V_MAD_U64_U32,
src/graphics/shader/recompiler/frontend/decode/VectorAluOps.cpp
+5 -3
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@@ -312,6 +312,7 @@ constexpr OpcodeMap VOP3_OPCODE_LIST[] = {
{0x345u, Opcode::V_XAD_U32},
{0x346u, Opcode::V_LSHL_ADD_U32},
{0x347u, Opcode::V_ADD_LSHL_U32},
{0x35eu, Opcode::V_MAD_I16},
{0x360u, Opcode::V_READLANE_B32},
{0x361u, Opcode::V_WRITELANE_B32},
{0x362u, Opcode::V_LDEXP_F32},
@@ -424,7 +425,7 @@ bool IsNativeVop3F16TernaryOpcode(Opcode opcode) {
}
bool IsNativeVop3I16TernaryOpcode(Opcode opcode) {
return opcode == Opcode::V_MED3_I16;
return opcode == Opcode::V_MED3_I16 || opcode == Opcode::V_MAD_I16;
}
bool IsNativeVop3B16BinaryOpcode(Opcode opcode) {
@@ -1362,7 +1363,8 @@ bool SupportsNativeVop3ResultModifiers(Opcode opcode) {
}
bool SupportsNativeVop3Clamp(Opcode opcode) {
return SupportsNativeVop3ResultModifiers(opcode) || UsesInexactClampControl(opcode);
return SupportsNativeVop3ResultModifiers(opcode) || UsesInexactClampControl(opcode) ||
opcode == Opcode::V_MAD_I16;
}
bool HasUnsupportedNativeVop3Modifiers(Opcode opcode, bool permlane, bool mad_mix,
@@ -1383,7 +1385,7 @@ bool HasUnsupportedNativeVop3Modifiers(Opcode opcode, bool permlane, bool mad_mi
return opcode != Opcode::V_FMA_F16 && (clamp != 0u || omod != 0u);
}
if (IsNativeVop3I16TernaryOpcode(opcode)) {
return abs != 0u || clamp != 0u || omod != 0u || neg != 0u;
return abs != 0u || (clamp != 0u && !clamp_modifier) || omod != 0u || neg != 0u;
}
if (IsNativeVop3B16BinaryOpcode(opcode)) {
return abs != 0u || clamp != 0u || omod != 0u || neg != 0u;
src/graphics/shader/recompiler/frontend/translate/Integer.cpp
+12
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@@ -22,6 +22,18 @@ bool Translator::Integer16Binary(const Decoder::Instruction& inst, IR::ValueOpco
return true;
}
bool Translator::V_MAD_I16(const Decoder::Instruction& inst) {
const auto lhs = ReadU16AsU32(inst.src0, true);
const auto rhs = ReadU16AsU32(inst.src1, true);
auto result = ir.IAdd(ir.IMul(lhs, rhs), ReadU16AsU32(inst.src2, true));
if (inst.dst.clamp) {
result = IR::U32(ir.Emit(IR::ValueOpcode::SMax32, {result, IR::Value(0xffff8000u)}));
result = IR::U32(ir.Emit(IR::ValueOpcode::SMin32, {result, IR::Value(0x7fffu)}));
}
Write16Bits(DestinationOperand(inst), ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu))));
return true;
}
bool Translator::V_MED3_I16(const Decoder::Instruction& inst) {
const auto result = IR::U32(ir.Emit(
IR::ValueOpcode::SMedTri32, {ReadU16AsU32(inst.src0, true), ReadU16AsU32(inst.src1, true),
src/graphics/shader/recompiler/frontend/translate/Translator.h
+1
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@@ -164,6 +164,7 @@ private:
bool FloatCube(const Decoder::Instruction& inst, uint32_t result_kind);
bool Integer16Shift(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool arithmetic);
bool Integer16Binary(const Decoder::Instruction& inst, IR::ValueOpcode opcode, bool sign);
bool V_MAD_I16(const Decoder::Instruction& inst);
bool V_MED3_I16(const Decoder::Instruction& inst);
bool PackedInteger16Shift(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
bool arithmetic);
src/graphics/shader/recompiler/frontend/translate/Vector.cpp
+1
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@@ -328,6 +328,7 @@ bool Translator::EmitVector(const Decoder::Instruction& inst) {
case O::V_SUB_NC_U16:
case O::V_SUB_NC_I16: return Integer16Binary(inst, IR::ValueOpcode::ISub32, false);
case O::V_MUL_LO_U16: return Integer16Binary(inst, IR::ValueOpcode::IMul32, false);
case O::V_MAD_I16: return V_MAD_I16(inst);
case O::V_MED3_I16: return V_MED3_I16(inst);
case O::V_MIN_I16: return Integer16Binary(inst, IR::ValueOpcode::SMin32, true);
case O::V_MAX_I16: return Integer16Binary(inst, IR::ValueOpcode::SMax32, true);