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https://github.com/KytyPS5/KytyPS5.git
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shader: mask ALIGNBYTE offsets to the two-bit selector
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com> Co-authored-by: TheCruZ <thecruzwtf@gmail.com>
This commit is contained in:
@@ -483,10 +483,11 @@ void Translator::S_BITCMP_B64(const Decoder::Instruction& inst, bool expected) {
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WriteCompareResult(inst.dst, ir.IEqual(bit, IR::U32(IR::Value(expected ? 1u : 0u))));
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WriteCompareResult(inst.dst, ir.IEqual(bit, IR::U32(IR::Value(expected ? 1u : 0u))));
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}
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}
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void Translator::V_ALIGNBIT_B32(const Decoder::Instruction& inst) {
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void Translator::V_ALIGN_B32(const Decoder::Instruction& inst, bool byte_offset) {
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const auto hi = ReadU32(inst.src0);
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const auto hi = ReadU32(inst.src0);
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const auto lo = ReadU32(inst.src1);
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const auto lo = ReadU32(inst.src1);
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const auto shift = ir.BitwiseAnd(ReadU32(inst.src2), IR::U32(IR::Value(31u)));
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auto shift = ir.BitwiseAnd(ReadU32(inst.src2), IR::U32(IR::Value(byte_offset ? 3u : 31u)));
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if (byte_offset) shift = ir.ShiftLeftLogical(shift, IR::U32(IR::Value(3u)));
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const auto lo_part = ir.ShiftRightLogical(lo, shift);
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const auto lo_part = ir.ShiftRightLogical(lo, shift);
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const auto inverse =
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const auto inverse =
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ir.BitwiseAnd(ir.ISub(IR::U32(IR::Value(32u)), shift), IR::U32(IR::Value(31u)));
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ir.BitwiseAnd(ir.ISub(IR::U32(IR::Value(32u)), shift), IR::U32(IR::Value(31u)));
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@@ -496,21 +497,6 @@ void Translator::V_ALIGNBIT_B32(const Decoder::Instruction& inst) {
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WriteOperand(DestinationOperand(inst), ir.BitwiseOr(lo_part, hi_part));
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WriteOperand(DestinationOperand(inst), ir.BitwiseOr(lo_part, hi_part));
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}
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}
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void Translator::V_ALIGNBYTE_B32(const Decoder::Instruction& inst) {
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const auto hi = ReadU32(inst.src0);
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const auto lo = ReadU32(inst.src1);
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const auto byte_offset = ir.BitwiseAnd(ReadU32(inst.src2), IR::U32(IR::Value(31u)));
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const auto bit_offset = ir.ShiftLeftLogical(byte_offset, IR::U32(IR::Value(3u)));
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const auto concatenated = ir.ConstructU64(lo, hi);
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const auto shifted =
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IR::U64(ir.Emit(IR::ValueOpcode::ShiftRightLogical64,
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{concatenated, ir.BitwiseAnd(bit_offset, IR::U32(IR::Value(63u)))}));
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const auto in_range =
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IR::U1(ir.Emit(IR::ValueOpcode::ULessThan32, {byte_offset, IR::Value(8u)}));
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WriteOperand(DestinationOperand(inst),
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ir.Select(in_range, ExtractU64(shifted)[0], IR::U32(IR::Value(0u))));
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}
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void Translator::V_LSHL_ADD_U32(const Decoder::Instruction& inst) {
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void Translator::V_LSHL_ADD_U32(const Decoder::Instruction& inst) {
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const auto shift = ir.BitwiseAnd(ReadU32(inst.src1), IR::U32(IR::Value(31u)));
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const auto shift = ir.BitwiseAnd(ReadU32(inst.src1), IR::U32(IR::Value(31u)));
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const auto result = ir.IAdd(ir.ShiftLeftLogical(ReadU32(inst.src0), shift), ReadU32(inst.src2));
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const auto result = ir.IAdd(ir.ShiftLeftLogical(ReadU32(inst.src0), shift), ReadU32(inst.src2));
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@@ -208,8 +208,7 @@ private:
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void V_BFI_B32(const Decoder::Instruction& inst);
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void V_BFI_B32(const Decoder::Instruction& inst);
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void S_BITCMP_B32(const Decoder::Instruction& inst, bool expected);
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void S_BITCMP_B32(const Decoder::Instruction& inst, bool expected);
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void S_BITCMP_B64(const Decoder::Instruction& inst, bool expected);
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void S_BITCMP_B64(const Decoder::Instruction& inst, bool expected);
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void V_ALIGNBIT_B32(const Decoder::Instruction& inst);
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void V_ALIGN_B32(const Decoder::Instruction& inst, bool byte_offset);
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void V_ALIGNBYTE_B32(const Decoder::Instruction& inst);
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void V_LSHL_ADD_U32(const Decoder::Instruction& inst);
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void V_LSHL_ADD_U32(const Decoder::Instruction& inst);
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void V_ADD_LSHL_U32(const Decoder::Instruction& inst);
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void V_ADD_LSHL_U32(const Decoder::Instruction& inst);
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void V_XAD_U32(const Decoder::Instruction& inst);
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void V_XAD_U32(const Decoder::Instruction& inst);
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@@ -592,8 +592,8 @@ void Translator::EmitVector(const Decoder::Instruction& inst) {
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case O::V_BFE_U32: return V_BFE_U32(inst, false);
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case O::V_BFE_U32: return V_BFE_U32(inst, false);
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case O::V_BFE_I32: return V_BFE_U32(inst, true);
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case O::V_BFE_I32: return V_BFE_U32(inst, true);
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case O::V_BFI_B32: return V_BFI_B32(inst);
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case O::V_BFI_B32: return V_BFI_B32(inst);
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case O::V_ALIGNBIT_B32: return V_ALIGNBIT_B32(inst);
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case O::V_ALIGNBIT_B32: return V_ALIGN_B32(inst, false);
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case O::V_ALIGNBYTE_B32: return V_ALIGNBYTE_B32(inst);
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case O::V_ALIGNBYTE_B32: return V_ALIGN_B32(inst, true);
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case O::V_LSHL_ADD_U32: return V_LSHL_ADD_U32(inst);
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case O::V_LSHL_ADD_U32: return V_LSHL_ADD_U32(inst);
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case O::V_ADD_LSHL_U32: return V_ADD_LSHL_U32(inst);
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case O::V_ADD_LSHL_U32: return V_ADD_LSHL_U32(inst);
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case O::V_XAD_U32: return V_XAD_U32(inst);
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case O::V_XAD_U32: return V_XAD_U32(inst);
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@@ -21243,27 +21243,32 @@ TestCase VectorBfeI32SignExtendsField() {
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return test;
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return test;
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}
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}
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TestCase VectorAlignByteUsesFiveBitByteOffset() {
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TestCase VectorAlignByteUsesTwoBitByteOffset() {
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using O = ShaderOpcode;
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using O = ShaderOpcode;
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std::vector<u32> code;
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std::vector<u32> code;
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AppendVMovLiteral(&code, 0, 0x11223344u);
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AppendVMovLiteral(&code, 0, 0x11223344u);
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AppendVMovLiteral(&code, 1, 0x55667788u);
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AppendVMovLiteral(&code, 1, 0x55667788u);
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constexpr u32 offsets[] = {0, 1, 3, 4, 5, 7, 8, 31};
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const std::vector<u32> offsets = {0, 1, 2, 3, 4, 5, 7, 8, 31, 32, 0xffffffffu};
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for (u32 i = 0; i < static_cast<u32>(std::size(offsets)); i++) {
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for (u32 i = 0; i < static_cast<u32>(std::size(offsets)); i++) {
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AppendVMovU32(&code, 2, offsets[i]);
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AppendVMovU32(&code, 2, i * sizeof(u32));
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AppendBufferLoadDword(&code, 2, 2);
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AppendVop3(&code, 0x14f, 10u + i, Vgpr(0), Vgpr(1), Vgpr(2));
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AppendVop3(&code, 0x14f, 10u + i, Vgpr(0), Vgpr(1), Vgpr(2));
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AppendStoreVgpr(&code, 10u + i, i);
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AppendStoreVgpr(&code, 10u + i, i);
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}
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}
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AppendEnd(&code);
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AppendEnd(&code);
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return {
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TestCase test{
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"VectorAlignByteUsesFiveBitByteOffset",
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"VectorAlignByteUsesTwoBitByteOffset",
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code,
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code,
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{},
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offsets,
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{0x55667788u, 0x44556677u, 0x22334455u, 0x11223344u, 0x00112233u,
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{0x55667788u, 0x44556677u, 0x33445566u, 0x22334455u, 0x55667788u,
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0x00000011u, 0u, 0u},
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0x44556677u, 0x22334455u, 0x55667788u, 0x22334455u, 0x55667788u,
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{O::V_MOV_B32, O::V_ALIGNBYTE_B32, O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
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0x22334455u},
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{O::V_MOV_B32, O::BUFFER_LOAD_DWORD, O::V_ALIGNBYTE_B32,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
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test.forbidden_spirv = {"OpTypeInt 64"};
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return test;
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}
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}
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TestCase VectorCarryAndBitCountOps() {
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TestCase VectorCarryAndBitCountOps() {
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@@ -32485,7 +32490,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(VectorVop3LshlrevB64Captured);
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AddCase(VectorVop3LshlrevB64Captured);
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AddCase(VectorVop3IntegerOps);
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AddCase(VectorVop3IntegerOps);
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AddCase(VectorBfeI32SignExtendsField);
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AddCase(VectorBfeI32SignExtendsField);
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AddCase(VectorAlignByteUsesFiveBitByteOffset);
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AddCase(VectorAlignByteUsesTwoBitByteOffset);
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AddCase(VectorCarryAndBitCountOps);
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AddCase(VectorCarryAndBitCountOps);
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AddCase(VectorMbcntUsesThreadMask);
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AddCase(VectorMbcntUsesThreadMask);
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AddCase(VectorAddcWritesPerLaneCarryOut);
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AddCase(VectorAddcWritesPerLaneCarryOut);
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@@ -37926,7 +37931,8 @@ int main(int argc, char **argv) {
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}
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}
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if (argc == 2 && std::strcmp(argv[1], "--alignbyte-only") == 0) {
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if (argc == 2 && std::strcmp(argv[1], "--alignbyte-only") == 0) {
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VulkanHarness vulkan;
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VulkanHarness vulkan;
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RunCase(&vulkan, VectorAlignByteUsesFiveBitByteOffset());
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RunCase(&vulkan, VectorAlignByteUsesTwoBitByteOffset());
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RunCase(&vulkan, VectorVop3IntegerOps());
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return 0;
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return 0;
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}
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}
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if (argc == 2 && std::strcmp(argv[1], "--zero-shift-only") == 0) {
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if (argc == 2 && std::strcmp(argv[1], "--zero-shift-only") == 0) {
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