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https://github.com/KytyPS5/KytyPS5.git
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tests: cover tessellation patch constants, predicated mul24 addresses, and forward-branch joins
This commit is contained in:
nmzik
@@ -84,6 +84,7 @@
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#include <cstring>
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#include <initializer_list>
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#include <limits>
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#include <map>
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#include <memory>
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#include <mutex>
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#include <numeric>
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@@ -43692,6 +43693,58 @@ void CheckPs5GameExampleImageClearRuntimeShape() {
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std::printf("[host] %-32s ok\n", "Ps5GameExampleImageClear");
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}
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struct TessellationStage {
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// Immediate byte addresses of the lowered accesses, per attribute kind.
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std::map<ShaderRecompiler::IR::TessellationAttribute, std::set<u32>> addresses;
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std::string assembly;
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};
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TessellationStage CompileTessellationStage(const char *name, const std::vector<u32> &code,
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ShaderType stage,
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const ShaderTessellationInputInfo &tess) {
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using namespace ShaderRecompiler;
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ShaderVertexInputInfo vertex;
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vertex.logical_stage = stage;
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vertex.tess = tess;
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CompileOptions options;
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options.stage = stage;
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options.input_info.vertex = &vertex;
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auto translated = TranslateProgram(code, options);
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TessellationStage result;
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for (const auto *block : translated.program.blocks) {
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for (const auto &inst : *block) {
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if ((inst.GetOpcode() == IR::ValueOpcode::GetTessellationAttribute ||
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inst.GetOpcode() == IR::ValueOpcode::SetTessellationAttribute) &&
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inst.Arg(1).IsImmediate()) {
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result.addresses[static_cast<IR::TessellationAttribute>(inst.Arg(0).U32())].insert(
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inst.Arg(1).U32());
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}
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}
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}
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auto compiled = CompileProgram(std::move(translated), options, {});
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ValidateSpirv(name, compiled.spirv);
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spvtools::SpirvTools tools(SPV_ENV_VULKAN_1_2);
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Require(name, "disassembly", tools.Disassemble(compiled.spirv, &result.assembly),
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"failed to disassemble tessellation shader");
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return result;
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}
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// Whether a Patch uvec4[vectors] variable of a storage class sits at a Location.
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bool HasPatchInterface(const std::string &assembly, const std::string &storage, u32 vectors,
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u32 location) {
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const auto variable = " = OpVariable %_ptr_" + storage + "__arr_v4uint_uint_" +
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std::to_string(vectors) + " " + storage + "\n";
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const auto end = assembly.find(variable);
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if (end == std::string::npos) {
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return false;
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}
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const auto begin = assembly.rfind('%', end);
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const auto id = assembly.substr(begin, end - begin);
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return assembly.find("OpDecorate " + id + " Patch\n") != std::string::npos &&
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assembly.find("OpDecorate " + id + " Location " + std::to_string(location) + "\n") !=
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std::string::npos;
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}
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void CheckTessellationProgram(const char *name, u32 ls_stride, u32 hs_stride) {
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using namespace ShaderRecompiler;
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const bool multiplied_stride = hs_stride == 112;
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@@ -43700,8 +43753,7 @@ void CheckTessellationProgram(const char *name, u32 ls_stride, u32 hs_stride) {
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const u32 relative_patch = multiplied_stride ? 28 : 32;
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const u32 output_address = multiplied_stride ? 31 : 35;
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const u32 input_address = multiplied_stride ? 25 : 29;
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std::array<std::vector<u32>, 3> code;
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auto &local = code[0];
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std::vector<u32> local, control, evaluation;
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// The fused LS addresses one control point using its v3 ordinal.
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local.push_back(EncodeVop2(0x0b, local_address, 255u, 3));
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local.push_back(ls_stride);
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@@ -43710,7 +43762,6 @@ void CheckTessellationProgram(const char *name, u32 ls_stride, u32 hs_stride) {
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local.push_back(EncodeSop1(0x20, 0, 6));
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local.push_back(0xffffffffu); // Shader footer is not executable after LS handoff.
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auto &control = code[1];
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AppendVop3(&control, 0x365, 0, 193u, InlineU32(0));
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AppendVop3(&control, 0x366, 0, 193u, Vgpr(0));
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control.push_back(EncodeSopp(0x0a));
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@@ -43769,7 +43820,6 @@ void CheckTessellationProgram(const char *name, u32 ls_stride, u32 hs_stride) {
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}
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AppendEnd(&control);
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auto &evaluation = code[2];
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AppendVop3(&evaluation, 0x169, 24, 255u, Vgpr(7));
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evaluation.push_back(3 * hs_stride);
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evaluation.push_back(EncodeMubuf0(0x0d, 28));
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@@ -43790,91 +43840,187 @@ void CheckTessellationProgram(const char *name, u32 ls_stride, u32 hs_stride) {
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tess.ls_stride == ls_stride && tess.hs_stride == hs_stride,
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"captured LS and HS address arithmetic must produce distinct strides");
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constexpr std::array stages{ShaderType::Local, ShaderType::TessellationControl,
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ShaderType::TessellationEvaluation};
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for (u32 stage = 0; stage < stages.size(); stage++) {
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ShaderVertexInputInfo vertex;
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vertex.logical_stage = stages[stage];
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vertex.tess = tess;
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CompileOptions options;
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options.stage = stages[stage];
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options.input_info.vertex = &vertex;
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auto translated = TranslateProgram(code[stage], options);
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std::set<u32> local_offsets, evaluation_offsets, factor_offsets, patch_offsets;
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for (const auto *block : translated.program.blocks) {
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for (const auto &inst : *block) {
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if (inst.GetOpcode() != IR::ValueOpcode::GetTessellationAttribute &&
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inst.GetOpcode() != IR::ValueOpcode::SetTessellationAttribute) {
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continue;
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}
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if (!inst.Arg(1).IsImmediate()) {
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continue;
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}
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switch (static_cast<IR::TessellationAttribute>(inst.Arg(0).U32())) {
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case IR::TessellationAttribute::LocalOutput:
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local_offsets.insert(inst.Arg(1).U32());
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break;
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case IR::TessellationAttribute::EvaluationInput:
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evaluation_offsets.insert(inst.Arg(1).U32());
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break;
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case IR::TessellationAttribute::Factor:
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factor_offsets.insert(inst.Arg(1).U32());
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break;
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case IR::TessellationAttribute::PatchOutput:
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patch_offsets.insert(inst.Arg(1).U32());
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break;
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default:
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break;
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}
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}
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}
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Require(name, "separate DS offsets", stage != 0 || local_offsets == std::set<u32>{4, 12},
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"DS_WRITE2 must preserve both independently encoded offsets");
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Require(name, "offchip component addressing",
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stage != 2 ||
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evaluation_offsets == std::set<u32>{28, 2 * hs_stride + 28},
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"TES control point and component offsets must survive lowering");
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Require(name, "triangle factor layout",
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stage != 1 || factor_offsets == std::set<u32>{0, 4, 8, 12},
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"the four packed guest factors must retain their order");
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Require(name, "predicated patch addresses",
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stage != 1 || patch_offsets == std::set<u32>{0x7fc0, 0x7fd0, 0x7fe0, 0x7ff0},
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"CP0 patch stores must use the address assigned on their active predicate");
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auto result = CompileProgram(std::move(translated), options, {});
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ValidateSpirv(name, result.spirv);
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spvtools::SpirvTools tools(SPV_ENV_VULKAN_1_2);
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std::string assembly;
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Require(name, "disassembly", tools.Disassemble(result.spirv, &assembly),
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"failed to disassemble tessellation shader");
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Require(name, "native local inputs",
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stage != 0 || (assembly.find("VertexIndex") != std::string::npos &&
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assembly.find("InstanceIndex") != std::string::npos),
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"LS v2/v5 must read native vertex/instance indices");
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Require(name, "control point lane",
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stage != 1 || (assembly.find("InvocationId") != std::string::npos &&
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assembly.find("SubgroupLocalInvocationId") == std::string::npos),
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"HS lane masks must use control point invocation IDs");
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Require(name, "control point barrier",
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stage != 1 || (assembly.find("OpMemoryModel Logical GLSL450") != std::string::npos &&
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assembly.find("OpControlBarrier %uint_2 %uint_4 %uint_0") != std::string::npos),
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"HS barriers must match GLSL450 control point synchronization semantics");
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Require(name, "factor builtins",
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stage != 1 || (assembly.find("TessLevelOuter") != std::string::npos &&
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assembly.find("TessLevelInner") != std::string::npos),
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"triangle factors require outer[4] and inner[2] Vulkan builtins");
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Require(name, "native domain and winding",
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stage != 2 || (assembly.find("TessCoord") != std::string::npos &&
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assembly.find("Triangles") != std::string::npos &&
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assembly.find("SpacingFractionalOdd") != std::string::npos &&
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assembly.find("VertexOrderCw") != std::string::npos),
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"TES must preserve guest triangle domain, partitioning, and winding");
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}
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Require(name, "patch constant range", tess.patch_base == 0x7fc0u && tess.patch_size == 52u,
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"CP0 patch stores must reflect the HS patch constant range");
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using Attribute = IR::TessellationAttribute;
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auto ls = CompileTessellationStage(name, local, ShaderType::Local, tess);
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auto hs = CompileTessellationStage(name, control, ShaderType::TessellationControl, tess);
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auto ds = CompileTessellationStage(name, evaluation, ShaderType::TessellationEvaluation, tess);
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Require(name, "separate DS offsets", ls.addresses[Attribute::LocalOutput] == std::set<u32>{4, 12},
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"DS_WRITE2 must preserve both independently encoded offsets");
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Require(name, "offchip component addressing",
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ds.addresses[Attribute::EvaluationInput] == std::set<u32>{28, 2 * hs_stride + 28},
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"TES control point and component offsets must survive lowering");
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Require(name, "triangle factor layout",
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hs.addresses[Attribute::Factor] == std::set<u32>{0, 4, 8, 12},
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"the four packed guest factors must retain their order");
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Require(name, "predicated patch addresses",
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hs.addresses[Attribute::PatchOutput] == std::set<u32>{0x7fc0, 0x7fd0, 0x7fe0, 0x7ff0},
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"CP0 patch stores must use the address assigned on their active predicate");
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Require(name, "native local inputs",
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ls.assembly.find("VertexIndex") != std::string::npos &&
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ls.assembly.find("InstanceIndex") != std::string::npos,
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"LS v2/v5 must read native vertex/instance indices");
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Require(name, "control point lane",
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hs.assembly.find("InvocationId") != std::string::npos &&
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hs.assembly.find("SubgroupLocalInvocationId") == std::string::npos,
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"HS lane masks must use control point invocation IDs");
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Require(name, "control point barrier",
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hs.assembly.find("OpMemoryModel Logical GLSL450") != std::string::npos &&
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hs.assembly.find("OpControlBarrier %uint_2 %uint_4 %uint_0") != std::string::npos,
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"HS barriers must match GLSL450 control point synchronization semantics");
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Require(name, "factor builtins",
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hs.assembly.find("TessLevelOuter") != std::string::npos &&
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hs.assembly.find("TessLevelInner") != std::string::npos,
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"triangle factors require outer[4] and inner[2] Vulkan builtins");
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Require(name, "native domain and winding",
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ds.assembly.find("TessCoord") != std::string::npos &&
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ds.assembly.find("Triangles") != std::string::npos &&
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ds.assembly.find("SpacingFractionalOdd") != std::string::npos &&
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ds.assembly.find("VertexOrderCw") != std::string::npos,
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"TES must preserve guest triangle domain, partitioning, and winding");
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std::printf("[host] %-32s ok\n", name);
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}
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// PPSA25468: CP0 writes patch constants below the 32 KiB offchip ring end
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// through mul24 addresses that reuse data VGPRs under nested EXEC masks, and
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// the TES reads them back.
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void CheckTessellationPatchConstants() {
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using namespace ShaderRecompiler;
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using Attribute = IR::TessellationAttribute;
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constexpr const char *name = "TessellationPatchConstants";
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constexpr u32 ls_stride = 48, hs_stride = 80, patch_stride = 0xf0;
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std::vector<u32> local;
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// One 128-bit DS store writes the LS record.
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local.push_back(EncodeVop2(0x0b, 20, 255u, 3)); // v_mul_u32_u24 v20, ls_stride, v3
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local.push_back(ls_stride);
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local.push_back(EncodeDs0(0xdf, 16)); // ds_write_b128 v20, v[2:5] offset:16
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local.push_back(EncodeDs1(0, 2, 20));
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local.push_back(EncodeSop1(0x20, 0, 6));
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const auto make_control = [&](bool divergent) {
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std::vector<u32> control;
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AppendVop3(&control, 0x365, 0, 193u, InlineU32(0));
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AppendVop3(&control, 0x366, 0, 193u, Vgpr(0));
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control.push_back(EncodeVopc(0xd1, 249u, 3));
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control.push_back(EncodeVopcSdwa(0, 0, 0, 6, 1, 0, 0, 0, 0, 0, 0, 0, 1));
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const auto skip_control = control.size();
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control.push_back(0u); // s_cbranch_execz
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AppendVop3(&control, 0x148, 16, Vgpr(1), InlineU32(8), InlineU32(5));
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control.push_back(EncodeVop2(0x1b, 50, 255u, 1)); // v_and_b32 v50, 0xff, v1
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control.push_back(0xffu);
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control.push_back(EncodeVop2(0x0b, 0, 255u, 16)); // v_mul_u32_u24 v0, hs_stride, v16
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control.push_back(hs_stride);
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AppendVop3(&control, 0x169, 1, Vgpr(16), 255u); // v_mul_lo_u32 v1, v16, ls_stride
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control.push_back(ls_stride);
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AppendVop3(&control, 0x143, 17, 255u, Vgpr(50), Vgpr(0));
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control.push_back(3 * hs_stride);
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AppendVop3(&control, 0x143, 14, 255u, Vgpr(50), Vgpr(1));
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control.push_back(3 * ls_stride);
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// ds_read2_b32 v[10:11], v14 offset0:4 offset1:5
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control.push_back(EncodeDs0(0x37, (5u << 8u) | 4u));
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control.push_back(EncodeDs1(10, 0, 14));
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control.push_back(EncodeMubuf0(0x1d, 16));
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control.push_back(EncodeMubuf1(10, 2, 17, 2));
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// v17 stays affine at the forward branch's join unless the paths diverge.
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control.push_back(EncodeVopc(0x01, InlineU32(0), 10)); // v_cmp_lt_f32 vcc, 0, v10
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const auto skip_scale = control.size();
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control.push_back(0u); // s_cbranch_vccz
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control.push_back(EncodeVop1(0x01, 12, 242u)); // v_mov_b32 v12, 1.0
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if (divergent) {
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control.push_back(EncodeVop2(0x25, 17, InlineU32(4), 17)); // v_add_nc_u32 v17, 4, v17
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}
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control[skip_scale] = EncodeSopp(0x06, control.size() - skip_scale - 1u);
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control.push_back(EncodeMubuf0(0x1c, 24));
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control.push_back(EncodeMubuf1(12, 2, 17, 2));
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// CP0 reuses data VGPR v10 for the ring address 0x8000 - (patch + 1) * 0xf0.
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control.push_back(EncodeVopc(0xd4, InlineU32(1), 16)); // v_cmpx_gt_u32 1, v16
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const auto skip_patch = control.size();
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control.push_back(0u); // s_cbranch_execz
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control.push_back(EncodeVop2(0x25, 10, InlineU32(1), 50)); // v_add_nc_u32 v10, 1, v50
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control.push_back(EncodeVop2(0x0b, 10, 255u, 10)); // v_mul_u32_u24 v10, 0xf0, v10
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control.push_back(patch_stride);
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control.push_back(EncodeVop2(0x26, 10, 255u, 10)); // v_sub_nc_u32 v10, 0x8000, v10
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control.push_back(0x8000u);
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control.push_back(EncodeVopc(0x01, InlineU32(0), 11)); // v_cmp_lt_f32 vcc, 0, v11
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control.push_back(EncodeSop1(0x24, 0, 106)); // s_and_saveexec_b64 s[0:1], vcc
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const auto skip_nested = control.size();
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control.push_back(0u); // s_cbranch_execz
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control.push_back(EncodeMubuf0(0x1c, 0)); // buffer_store_dword v11, v10, s[8:11], s2 offen
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control.push_back(EncodeMubuf1(11, 2, 10, 2));
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control[skip_nested] = EncodeSopp(0x08, control.size() - skip_nested - 1u);
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control.push_back(EncodeSop1(0x04, 126, 0)); // s_mov_b64 exec, s[0:1]
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// buffer_store_dwordx3 v[11:13], v10, s[8:11], s2 offen offset:16
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control.push_back(EncodeMubuf0(0x1f, 16));
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control.push_back(EncodeMubuf1(11, 2, 10, 2));
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control[skip_control] = EncodeSopp(0x08, control.size() - skip_control - 1u);
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control[skip_patch] = EncodeSopp(0x08, control.size() - skip_patch - 1u);
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AppendEnd(&control);
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return control;
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};
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const auto control = make_control(false);
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std::vector<u32> evaluation;
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AppendVop3(&evaluation, 0x169, 24, 255u, Vgpr(7));
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evaluation.push_back(3 * hs_stride);
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evaluation.push_back(EncodeVop2(0x25, 2, InlineU32(1), 7));
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evaluation.push_back(EncodeVop2(0x0b, 2, 255u, 2));
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evaluation.push_back(patch_stride);
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evaluation.push_back(EncodeVop2(0x26, 2, 255u, 2));
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evaluation.push_back(0x8000u);
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evaluation.push_back(EncodeMubuf0(0x0d, hs_stride + 16)); // CP1 dwords 4-5
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evaluation.push_back(EncodeMubuf1(10, 2, 24, 4));
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evaluation.push_back(EncodeMubuf0(0x0d, 16)); // patch constant dwords 4-5
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evaluation.push_back(EncodeMubuf1(12, 2, 2, 4));
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evaluation.push_back(EncodeVop2(0x03, 10, Vgpr(12), 10)); // v_add_f32 v10, v12, v10
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evaluation.push_back(EncodeVop2(0x03, 11, Vgpr(13), 11));
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evaluation.push_back(EncodeExp0(0x0c, 0xf));
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evaluation.push_back(EncodeExp1(5, 6, 10, 11));
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AppendEnd(&evaluation);
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ShaderTessellationInputInfo tess{.input_control_points = 3,
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.output_control_points = 3,
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.domain = 1,
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.partitioning = 2,
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.output_topology = 2};
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AnalyzeTessellationPrograms(local, control, tess);
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Require(name, "reflected interface",
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tess.ls_stride == ls_stride && tess.hs_stride == hs_stride &&
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tess.patch_base == 0x7f10u && tess.patch_size == 28u,
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"b128 LS records, joined HS paths and CP0 patch stores must reflect the layout");
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auto ls = CompileTessellationStage(name, local, ShaderType::Local, tess);
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auto hs = CompileTessellationStage(name, control, ShaderType::TessellationControl, tess);
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auto ds = CompileTessellationStage(name, evaluation, ShaderType::TessellationEvaluation, tess);
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Require(name, "128-bit LS record",
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ls.addresses[Attribute::LocalOutput] == std::set<u32>{16, 20, 24, 28},
|
||||
"DS_WRITE_B128 must lower to four consecutive LS outputs");
|
||||
Require(name, "predicated patch outputs",
|
||||
hs.addresses[Attribute::PatchOutput] == std::set<u32>{0x7f10, 0x7f20, 0x7f24, 0x7f28},
|
||||
"CP0 mul24 addresses under nested EXEC masks must reach patch constants");
|
||||
Require(name, "patch inputs",
|
||||
ds.addresses[Attribute::PatchInput] == std::set<u32>{0x7f20, 0x7f24} &&
|
||||
ds.addresses[Attribute::EvaluationInput] ==
|
||||
std::set<u32>{hs_stride + 16, hs_stride + 20},
|
||||
"TES patch constant reads must not alias control point inputs");
|
||||
Require(name, "matching patch interface",
|
||||
HasPatchInterface(hs.assembly, "Output", 2, 5) &&
|
||||
HasPatchInterface(ds.assembly, "Input", 2, 5),
|
||||
"HS and TES patch variables must share their Location and type");
|
||||
std::printf("[host] %-32s ok\n", name);
|
||||
#if KYTY_PLATFORM != KYTY_PLATFORM_WINDOWS
|
||||
ExpectFatal("TessellationDivergentJoin", [&] {
|
||||
ShaderTessellationInputInfo info{.input_control_points = 3, .output_control_points = 3};
|
||||
AnalyzeTessellationPrograms(local, make_control(true), info);
|
||||
});
|
||||
#endif
|
||||
}
|
||||
|
||||
void CheckTessellationPrograms() {
|
||||
CheckTessellationProgram("TessellationShiftedStride", 124, 128);
|
||||
CheckTessellationProgram("TessellationMultipliedStride", 108, 112);
|
||||
CheckTessellationPatchConstants();
|
||||
}
|
||||
|
||||
void CheckEmbeddedFetchVertexOffset() {
|
||||
|
||||
Reference in New Issue
Block a user