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shader: implement RDNA2 scalar quad-mask reduction

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This commit is contained in:
nmzik
2026-08-20 07:39:56 +02:00
parent bac6bf65af
commit fbdc1e8714
7 changed files with 56 additions and 2 deletions
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src/graphics/shader/recompiler/frontend/decode/ScalarAluOps.cpp
+1
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@@ -52,6 +52,7 @@ constexpr OpcodeMap SOP1_OPCODE_LIST[] = {
{0x20u, Opcode::S_SETPC_B64},
{0x24u, Opcode::S_AND_SAVEEXEC_B64},
{0x28u, Opcode::S_ORN2_SAVEEXEC_B64},
{0x2du, Opcode::S_QUADMASK_B64},
{0x34u, Opcode::S_ABS_I32},
{0x37u, Opcode::S_ANDN1_SAVEEXEC_B64},
{0x3bu, Opcode::S_BITREPLICATE_B64_B32},
src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.cpp
+1
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@@ -498,6 +498,7 @@ std::string InstructionToString(const Instruction& inst) {
case Opcode::S_FF1_I32_B64:
case Opcode::S_NOT_B64:
case Opcode::S_WQM_B64:
case Opcode::S_QUADMASK_B64:
case Opcode::S_AND_SAVEEXEC_B32:
case Opcode::S_ANDN1_SAVEEXEC_B32:
case Opcode::S_AND_SAVEEXEC_B64:
src/graphics/shader/recompiler/frontend/decode/ShaderDecoder.h
+1
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@@ -47,6 +47,7 @@ enum class Opcode {
S_FF1_I32_B64,
S_FLBIT_I32_B64,
S_BITREPLICATE_B64_B32,
S_QUADMASK_B64,
S_GETPC_B64,
S_SETPC_B64,
S_AND_SAVEEXEC_B32,
src/graphics/shader/recompiler/frontend/translate/Integer.cpp
+15
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@@ -469,6 +469,21 @@ bool Translator::TranslateExtendedInteger(const IR::Instruction& inst) {
replicate(ir.ShiftRightLogical(source, imm(16))));
break;
}
case IR::Opcode::QuadmaskB64: {
const auto compact = [&](IR::U32 value) {
auto bits = ir.BitwiseOr(value, ir.ShiftRightLogical(value, imm(1)));
bits = ir.BitwiseOr(bits, ir.ShiftRightLogical(bits, imm(2)));
bits = mask(bits, 0x11111111u);
bits = mask(ir.BitwiseOr(bits, ir.ShiftRightLogical(bits, imm(3))), 0x03030303u);
bits = mask(ir.BitwiseOr(bits, ir.ShiftRightLogical(bits, imm(6))), 0x000f000fu);
return mask(ir.BitwiseOr(bits, ir.ShiftRightLogical(bits, imm(12))), 0xffu);
};
const auto source = ReadU32Pair(inst.src[0]);
const auto quads =
ir.BitwiseOr(compact(source[0]), ir.ShiftLeftLogical(compact(source[1]), imm(8)));
result = ir.ConstructU64(quads, imm(0));
break;
}
case IR::Opcode::BitFieldMaskU32: {
const auto count = mask(ReadU32(inst.src[0]), 31u);
const auto offset = mask(ReadU32(inst.src[1]), 31u);
src/graphics/shader/recompiler/ir/opcodes/ShaderIROpcodes.cpp
+5 -2
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@@ -28,6 +28,7 @@ constexpr LowerMap LOWER_OPS[] = {
{Decoder::Opcode::S_FF1_I32_B64, Opcode::FindLsbU64},
{Decoder::Opcode::S_FLBIT_I32_B64, Opcode::FindMsbFromHighU64},
{Decoder::Opcode::S_BITREPLICATE_B64_B32, Opcode::BitReplicateB64B32},
{Decoder::Opcode::S_QUADMASK_B64, Opcode::QuadmaskB64},
{Decoder::Opcode::S_NOT_B32, Opcode::BitwiseNotU32},
{Decoder::Opcode::S_NOT_B64, Opcode::BitwiseNotU64},
{Decoder::Opcode::S_ADD_U32, Opcode::IAddU32},
@@ -511,7 +512,8 @@ bool ScalarResultWritesSccNonZero(Decoder::Opcode opcode) {
case Decoder::Opcode::S_LSHL_B64:
case Decoder::Opcode::S_LSHR_B64:
case Decoder::Opcode::S_BFE_U64:
case Decoder::Opcode::S_WQM_B64: return true;
case Decoder::Opcode::S_WQM_B64:
case Decoder::Opcode::S_QUADMASK_B64: return true;
default: return false;
}
}
@@ -530,7 +532,8 @@ bool ScalarResultIs64Bit(Decoder::Opcode opcode) {
case Decoder::Opcode::S_LSHL_B64:
case Decoder::Opcode::S_LSHR_B64:
case Decoder::Opcode::S_BFE_U64:
case Decoder::Opcode::S_WQM_B64: return true;
case Decoder::Opcode::S_WQM_B64:
case Decoder::Opcode::S_QUADMASK_B64: return true;
default: return false;
}
}
src/graphics/shader/recompiler/ir/opcodes/ShaderIROpcodes.inc
+1
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@@ -78,6 +78,7 @@ IR_OPCODE(BitReverseU32, General, SimpleInteger)
IR_OPCODE(BitCountU32, General, SimpleInteger)
IR_OPCODE(BitCountU64, General, SimpleInteger)
IR_OPCODE(BitReplicateB64B32, General, ExtendedInteger)
IR_OPCODE(QuadmaskB64, General, ExtendedInteger)
IR_OPCODE(BitCountAddU32, General, ExtendedInteger)
IR_OPCODE(MaskedBitCountLowU32, General, ExtendedInteger)
IR_OPCODE(MaskedBitCountHighU32, General, ExtendedInteger)