mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 19:07:01 +02:00
shader: remove second IR layer
This commit is contained in:
nmzik
@@ -1,23 +1,52 @@
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#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail {
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namespace Libs::Graphics::ShaderRecompiler::Frontend {
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namespace {
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bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
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bool IsExecOrVcc(const Decoder::Operand& operand) {
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switch (operand.kind) {
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case Decoder::OperandKind::ExecLo:
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case Decoder::OperandKind::ExecHi:
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case Decoder::OperandKind::VccLo:
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case Decoder::OperandKind::VccHi: return true;
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default: return false;
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}
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}
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Decoder::Operand ConditionOperand(Decoder::OperandKind kind) {
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Decoder::Operand operand;
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operand.kind = kind;
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return operand;
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}
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} // namespace
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bool Translator::TranslateStateOperation(const Decoder::Instruction& inst) {
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const auto zero = IR::U32(IR::Value(0u));
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switch (inst.op) {
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case IR::Opcode::SaveexecB32:
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case IR::Opcode::SaveexecB64: {
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switch (inst.opcode) {
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case Decoder::Opcode::S_AND_SAVEEXEC_B32:
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case Decoder::Opcode::S_ANDN1_SAVEEXEC_B32:
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case Decoder::Opcode::S_AND_SAVEEXEC_B64:
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case Decoder::Opcode::S_ANDN1_SAVEEXEC_B64:
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case Decoder::Opcode::S_ORN2_SAVEEXEC_B64: {
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const auto old = ir.GetExec();
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const auto src = ReadMask(inst.src[0]);
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const auto src = ReadMask(inst.src0);
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IR::U1 result;
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switch (inst.saveexec_mode) {
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case IR::SaveexecMode::And: result = ir.LogicalAnd(old, src); break;
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case IR::SaveexecMode::Andn1:
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switch (inst.opcode) {
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case Decoder::Opcode::S_AND_SAVEEXEC_B32:
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case Decoder::Opcode::S_AND_SAVEEXEC_B64: result = ir.LogicalAnd(old, src); break;
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case Decoder::Opcode::S_ANDN1_SAVEEXEC_B32:
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case Decoder::Opcode::S_ANDN1_SAVEEXEC_B64:
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result = ir.LogicalAnd(old, ir.LogicalNot(src));
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break;
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case IR::SaveexecMode::Orn2: result = ir.LogicalOr(ir.LogicalNot(old), src); break;
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case Decoder::Opcode::S_ORN2_SAVEEXEC_B64:
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result = ir.LogicalOr(ir.LogicalNot(old), src);
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break;
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default: EXIT("invalid saveexec opcode");
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}
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if (inst.op == IR::Opcode::SaveexecB64) {
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if (inst.opcode == Decoder::Opcode::S_AND_SAVEEXEC_B64 ||
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inst.opcode == Decoder::Opcode::S_ANDN1_SAVEEXEC_B64 ||
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inst.opcode == Decoder::Opcode::S_ORN2_SAVEEXEC_B64) {
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WriteMask64(inst.dst, old);
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} else {
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WriteMask(inst.dst, old);
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@@ -29,63 +58,75 @@ bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
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ir.SetScc(result);
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return true;
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}
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case IR::Opcode::ScalarAddCarryU32:
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case IR::Opcode::IAddCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto carry_in = ConditionBit(inst.src[2]);
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case Decoder::Opcode::S_ADD_U32:
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case Decoder::Opcode::S_ADDC_U32:
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case Decoder::Opcode::V_ADD_I32:
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case Decoder::Opcode::V_ADDC_U32: {
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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const auto carry_in = inst.opcode == Decoder::Opcode::S_ADDC_U32
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? ConditionBit(ConditionOperand(Decoder::OperandKind::Scc))
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: inst.opcode == Decoder::Opcode::V_ADDC_U32
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? ConditionBit(inst.src2)
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: zero;
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const auto add0 = ir.Emit(IR::ValueOpcode::IAddCarry32, {lhs, rhs});
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const auto partial = ir.CompositeExtract(add0, 0);
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const auto carry0 = ir.CompositeExtract(add0, 1);
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const auto add1 = ir.Emit(IR::ValueOpcode::IAddCarry32, {partial, carry_in});
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const auto result = ir.CompositeExtract(add1, 0);
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const auto carry1 = ir.CompositeExtract(add1, 1);
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const auto carry = ir.INotEqual(ir.BitwiseOr(carry0, carry1), IR::U32(IR::Value(0u)));
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WriteOperand(inst.dst, result);
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if (inst.op == IR::Opcode::ScalarAddCarryU32) {
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const auto carry = ir.INotEqual(ir.BitwiseOr(carry0, carry1), zero);
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WriteOperand(DestinationOperand(inst), result);
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if (inst.opcode == Decoder::Opcode::S_ADD_U32 ||
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inst.opcode == Decoder::Opcode::S_ADDC_U32) {
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ir.SetScc(carry);
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} else {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), carry));
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}
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return true;
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}
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case IR::Opcode::ScalarSubBorrowU32:
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case IR::Opcode::ISubBorrowU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto result = ir.ISub(lhs, rhs);
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const auto borrow = ir.UGreaterThan(rhs, lhs);
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WriteOperand(inst.dst, result);
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if (inst.op == IR::Opcode::ScalarSubBorrowU32) {
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case Decoder::Opcode::S_SUB_U32:
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case Decoder::Opcode::V_SUB_I32:
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case Decoder::Opcode::V_SUBREV_I32: {
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const bool reverse = inst.opcode == Decoder::Opcode::V_SUBREV_I32;
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const auto lhs = ReadU32(reverse ? inst.src1 : inst.src0);
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const auto rhs = ReadU32(reverse ? inst.src0 : inst.src1);
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const auto result = ir.ISub(lhs, rhs);
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const auto borrow = ir.UGreaterThan(rhs, lhs);
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WriteOperand(DestinationOperand(inst), result);
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if (inst.opcode == Decoder::Opcode::S_SUB_U32) {
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ir.SetScc(borrow);
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} else {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), borrow));
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}
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return true;
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}
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case IR::Opcode::ScalarSubBorrowCarryU32:
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case IR::Opcode::ISubBorrowCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const auto borrow_in = ConditionBit(inst.src[2]);
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case Decoder::Opcode::S_SUBB_U32:
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case Decoder::Opcode::V_SUBREV_CO_CI_U32: {
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const bool vector = inst.opcode == Decoder::Opcode::V_SUBREV_CO_CI_U32;
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const auto lhs = ReadU32(vector ? inst.src1 : inst.src0);
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const auto rhs = ReadU32(vector ? inst.src0 : inst.src1);
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const auto borrow_in = vector
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? ConditionBit(inst.src2)
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: ConditionBit(ConditionOperand(Decoder::OperandKind::Scc));
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const auto partial = ir.ISub(lhs, rhs);
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const auto result = ir.ISub(partial, borrow_in);
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const auto borrow0 = ir.UGreaterThan(rhs, lhs);
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const auto borrow1 = ir.UGreaterThan(borrow_in, partial);
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WriteOperand(inst.dst, result);
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const auto borrow = ir.LogicalOr(borrow0, borrow1);
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if (inst.op == IR::Opcode::ScalarSubBorrowCarryU32) {
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ir.SetScc(borrow);
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} else {
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const auto borrow = ir.LogicalOr(borrow0, borrow1);
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WriteOperand(DestinationOperand(inst), result);
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if (vector) {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), borrow));
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} else {
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ir.SetScc(borrow);
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}
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return true;
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}
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case IR::Opcode::ScalarSignedAddOverflowI32:
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case IR::Opcode::ScalarSignedSubOverflowI32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto rhs = ReadU32(inst.src[1]);
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const bool subtract = inst.op == IR::Opcode::ScalarSignedSubOverflowI32;
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case Decoder::Opcode::S_ADD_I32:
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case Decoder::Opcode::S_SUB_I32: {
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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const bool subtract = inst.opcode == Decoder::Opcode::S_SUB_I32;
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const auto result = subtract ? ir.ISub(lhs, rhs) : ir.IAdd(lhs, rhs);
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const auto shift = IR::U32(IR::Value(31u));
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const auto lhs_sign = ir.ShiftRightLogical(lhs, shift);
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@@ -94,116 +135,201 @@ bool Translator::TranslateStateOperation(const IR::Instruction& inst) {
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const auto inputs =
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subtract ? ir.INotEqual(lhs_sign, rhs_sign) : ir.IEqual(lhs_sign, rhs_sign);
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const auto changed = ir.INotEqual(lhs_sign, out_sign);
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WriteOperand(inst.dst, result);
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WriteOperand(DestinationOperand(inst), result);
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ir.SetScc(ir.LogicalAnd(inputs, changed));
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return true;
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}
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case IR::Opcode::ScalarShiftLeftAddCarryU32: {
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const auto lhs = ReadU32(inst.src[0]);
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const auto shift = ReadU32(inst.src[1]);
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const auto rhs = ReadU32(inst.src[2]);
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const auto shifted = ir.ShiftLeftLogical(lhs, shift);
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const auto result = ir.IAdd(shifted, rhs);
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const auto add_carry = ir.ULessThan(result, shifted);
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const auto inverse_shift = ir.ISub(IR::U32(IR::Value(32u)), shift);
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const auto shifted_out = ir.ShiftRightLogical(lhs, inverse_shift);
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const auto shift_carry = ir.INotEqual(shifted_out, zero);
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WriteOperand(inst.dst, result);
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case Decoder::Opcode::S_LSHL1_ADD_U32:
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case Decoder::Opcode::S_LSHL2_ADD_U32:
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case Decoder::Opcode::S_LSHL3_ADD_U32:
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case Decoder::Opcode::S_LSHL4_ADD_U32: {
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const uint32_t shift_amount = 1u + static_cast<uint32_t>(inst.opcode) -
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static_cast<uint32_t>(Decoder::Opcode::S_LSHL1_ADD_U32);
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const auto lhs = ReadU32(inst.src0);
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const auto shift = IR::U32(IR::Value(shift_amount));
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const auto rhs = ReadU32(inst.src1);
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const auto shifted = ir.ShiftLeftLogical(lhs, shift);
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const auto result = ir.IAdd(shifted, rhs);
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const auto add_carry = ir.ULessThan(result, shifted);
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const auto inverse_shift = ir.ISub(IR::U32(IR::Value(32u)), shift);
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const auto shifted_out = ir.ShiftRightLogical(lhs, inverse_shift);
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const auto shift_carry = ir.INotEqual(shifted_out, zero);
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WriteOperand(DestinationOperand(inst), result);
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ir.SetScc(ir.LogicalOr(add_carry, shift_carry));
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return true;
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}
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default: return false;
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}
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}
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bool Translator::TranslateControlOperation(const IR::Instruction& inst) {
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switch (inst.op) {
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case IR::Opcode::ControlNop: ir.Emit(IR::ValueOpcode::ControlNop); return true;
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case IR::Opcode::Waitcnt: ir.Emit(IR::ValueOpcode::Waitcnt); return true;
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case IR::Opcode::Barrier: ir.Emit(IR::ValueOpcode::Barrier); return true;
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case IR::Opcode::Sendmsg: ir.Emit(IR::ValueOpcode::Sendmsg); return true;
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case IR::Opcode::TtraceData: ir.Emit(IR::ValueOpcode::TtraceData); return true;
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case IR::Opcode::InstPrefetch: ir.Emit(IR::ValueOpcode::InstPrefetch); return true;
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default: return false;
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}
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}
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bool Translator::TranslateMove(const IR::Instruction& inst) {
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switch (inst.op) {
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case IR::Opcode::MoveU32:
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if (inst.src[0].kind == IR::OperandKind::Register &&
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(inst.src[0].reg.file == IR::RegisterFile::Exec ||
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inst.src[0].reg.file == IR::RegisterFile::Vcc) &&
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inst.dst.kind == IR::OperandKind::Register &&
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(inst.dst.reg.file == IR::RegisterFile::Exec ||
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inst.dst.reg.file == IR::RegisterFile::Vcc)) {
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WriteMask(inst.dst, ReadMask(inst.src[0]));
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} else {
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WriteOperand(inst.dst, ReadOperand(inst.src[0], IR::Type::U32));
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case Decoder::Opcode::S_MIN_I32:
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case Decoder::Opcode::S_MAX_I32:
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case Decoder::Opcode::S_MIN_U32:
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case Decoder::Opcode::S_MAX_U32: {
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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IR::ValueOpcode value_opcode;
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IR::ValueOpcode compare_opcode;
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switch (inst.opcode) {
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case Decoder::Opcode::S_MIN_I32:
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value_opcode = IR::ValueOpcode::SMin32;
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compare_opcode = IR::ValueOpcode::SLessThan32;
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break;
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case Decoder::Opcode::S_MAX_I32:
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value_opcode = IR::ValueOpcode::SMax32;
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compare_opcode = IR::ValueOpcode::SGreaterThan32;
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break;
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case Decoder::Opcode::S_MIN_U32:
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value_opcode = IR::ValueOpcode::UMin32;
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compare_opcode = IR::ValueOpcode::ULessThan32;
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break;
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case Decoder::Opcode::S_MAX_U32:
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value_opcode = IR::ValueOpcode::UMax32;
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compare_opcode = IR::ValueOpcode::UGreaterThan32;
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break;
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default: EXIT("invalid scalar min/max opcode");
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(value_opcode, {lhs, rhs}));
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ir.SetScc(IR::U1(ir.Emit(compare_opcode, {lhs, rhs})));
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return true;
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case IR::Opcode::MoveF32Bits:
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WriteOperand(inst.dst, ReadOperand(inst.src[0], IR::Type::F32));
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return true;
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case IR::Opcode::MoveU64: {
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const auto is_exec_or_vcc = [](const IR::Operand& operand) {
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return operand.kind == IR::OperandKind::Register &&
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(operand.reg.file == IR::RegisterFile::Exec ||
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operand.reg.file == IR::RegisterFile::Vcc);
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};
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if (is_exec_or_vcc(inst.dst) || is_exec_or_vcc(inst.src[0])) {
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WriteMask64(inst.dst, ReadMask(inst.src[0]));
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}
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default: return false;
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}
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}
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bool Translator::TranslateControlOperation(const Decoder::Instruction& inst) {
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switch (inst.opcode) {
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case Decoder::Opcode::V_NOP: return true;
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case Decoder::Opcode::S_NOP:
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case Decoder::Opcode::S_SETREG_B32:
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case Decoder::Opcode::S_SLEEP:
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case Decoder::Opcode::S_TRAP: ir.Emit(IR::ValueOpcode::ControlNop); return true;
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case Decoder::Opcode::S_WAITCNT:
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case Decoder::Opcode::S_WAITCNT_DEPCTR: ir.Emit(IR::ValueOpcode::Waitcnt); return true;
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case Decoder::Opcode::S_BARRIER: ir.Emit(IR::ValueOpcode::Barrier); return true;
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case Decoder::Opcode::S_SENDMSG: ir.Emit(IR::ValueOpcode::Sendmsg); return true;
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case Decoder::Opcode::S_TTRACEDATA: ir.Emit(IR::ValueOpcode::TtraceData); return true;
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case Decoder::Opcode::S_INST_PREFETCH: ir.Emit(IR::ValueOpcode::InstPrefetch); return true;
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default: return false;
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}
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}
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bool Translator::TranslateMove(const Decoder::Instruction& inst, std::string* error) {
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switch (inst.opcode) {
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case Decoder::Opcode::S_GETPC_B64: {
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const auto base = IR::U64(ir.Emit(IR::ValueOpcode::GetShaderBase));
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const auto address = IR::U64(ir.Emit(
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IR::ValueOpcode::IAdd64, {base, IR::Value(static_cast<uint64_t>(inst.pc) + 4u)}));
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if (inst.dst.kind == Decoder::OperandKind::Null) {
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return true;
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}
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const bool scalar_copy = inst.dst.kind == IR::OperandKind::Register &&
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inst.src[0].kind == IR::OperandKind::Register &&
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inst.dst.reg.file == IR::RegisterFile::Scalar &&
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inst.src[0].reg.file == IR::RegisterFile::Scalar;
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IR::U1 source_mask;
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IR::U1 source_mask_valid;
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if (scalar_copy) {
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const auto src = static_cast<IR::ScalarReg>(inst.src[0].reg.index);
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source_mask = ir.GetThreadBitScalarReg(src);
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source_mask_valid = ir.GetScalarMaskTag(src);
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auto high = PlainOperand(inst.dst);
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switch (inst.dst.kind) {
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case Decoder::OperandKind::Sgpr:
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if (inst.dst.reg < 105u) {
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high.reg++;
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} else if (inst.dst.reg == 105u) {
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high.kind = Decoder::OperandKind::VccLo;
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high.reg = 0u;
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} else {
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if (error != nullptr) {
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*error = "S_GETPC_B64 destination does not name a valid scalar pair";
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}
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return false;
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}
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break;
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case Decoder::OperandKind::VccLo: high.kind = Decoder::OperandKind::VccHi; break;
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case Decoder::OperandKind::M0: high.kind = Decoder::OperandKind::Null; break;
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case Decoder::OperandKind::ExecLo: high.kind = Decoder::OperandKind::ExecHi; break;
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default:
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if (error != nullptr) {
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*error = "S_GETPC_B64 destination does not name a valid scalar pair";
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}
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return false;
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}
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WriteU32Pair(inst.dst, ReadU32Pair(inst.src[0]));
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if (scalar_copy) {
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ir.SetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.dst.reg.index),
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source_mask);
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ir.SetScalarMaskTag(static_cast<IR::ScalarReg>(inst.dst.reg.index),
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source_mask_valid);
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const auto words = ExtractU64(address);
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WriteOperand(inst.dst, words[0]);
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WriteOperand(high, words[1]);
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return true;
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}
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case Decoder::Opcode::S_CSELECT_B32: {
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const auto result = ir.Select(ir.GetScc(), ReadU32(inst.src0), ReadU32(inst.src1));
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WriteOperand(DestinationOperand(inst), result);
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return true;
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}
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case Decoder::Opcode::S_CSELECT_B64: {
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const auto condition = ir.GetScc();
|
||||
const auto lhs = ReadU32Pair(inst.src0);
|
||||
const auto rhs = ReadU32Pair(inst.src1);
|
||||
const auto selected_mask = IR::U1(ir.Emit(
|
||||
IR::ValueOpcode::SelectU1, {condition, ReadMask(inst.src0), ReadMask(inst.src1)}));
|
||||
const auto selected_mask_valid =
|
||||
IR::U1(ir.Emit(IR::ValueOpcode::SelectU1,
|
||||
{condition, ReadMaskValid(inst.src0), ReadMaskValid(inst.src1)}));
|
||||
if (IsExecOrVcc(inst.dst)) {
|
||||
WriteMask64(inst.dst, selected_mask);
|
||||
return true;
|
||||
}
|
||||
WriteU32Pair(inst.dst, {ir.Select(condition, lhs[0], rhs[0]),
|
||||
ir.Select(condition, lhs[1], rhs[1])});
|
||||
if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
|
||||
const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg);
|
||||
ir.SetThreadBitScalarReg(dst, selected_mask);
|
||||
ir.SetScalarMaskTag(dst, selected_mask_valid);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::WqmB64: {
|
||||
const auto is_exec_or_vcc = [](const IR::Operand& operand) {
|
||||
return operand.kind == IR::OperandKind::Register &&
|
||||
(operand.reg.file == IR::RegisterFile::Exec ||
|
||||
operand.reg.file == IR::RegisterFile::Vcc);
|
||||
};
|
||||
if (!is_exec_or_vcc(inst.dst) && !is_exec_or_vcc(inst.src[0])) {
|
||||
const auto mask_valid = ReadMaskValid(inst.src[0]);
|
||||
case Decoder::Opcode::S_MOV_B32:
|
||||
case Decoder::Opcode::S_MOVK_I32:
|
||||
case Decoder::Opcode::V_MOV_B32:
|
||||
if (IsExecOrVcc(inst.src0) && IsExecOrVcc(inst.dst)) {
|
||||
WriteMask(inst.dst, ReadMask(inst.src0));
|
||||
} else if (inst.opcode == Decoder::Opcode::V_MOV_B32 &&
|
||||
(inst.src0.negate || inst.src0.absolute)) {
|
||||
WriteOperand(DestinationOperand(inst), ReadOperand(inst.src0, IR::Type::F32));
|
||||
} else {
|
||||
WriteOperand(DestinationOperand(inst), ReadOperand(inst.src0, IR::Type::U32));
|
||||
}
|
||||
return true;
|
||||
case Decoder::Opcode::S_MOV_B64: {
|
||||
if (IsExecOrVcc(inst.dst) || IsExecOrVcc(inst.src0)) {
|
||||
WriteMask64(inst.dst, ReadMask(inst.src0));
|
||||
return true;
|
||||
}
|
||||
const bool scalar_copy = inst.dst.kind == Decoder::OperandKind::Sgpr &&
|
||||
inst.src0.kind == Decoder::OperandKind::Sgpr;
|
||||
IR::U1 source_mask;
|
||||
IR::U1 source_mask_valid;
|
||||
if (scalar_copy) {
|
||||
source_mask = ir.GetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.src0.reg));
|
||||
source_mask_valid = ir.GetScalarMaskTag(static_cast<IR::ScalarReg>(inst.src0.reg));
|
||||
}
|
||||
WriteU32Pair(inst.dst, ReadU32Pair(inst.src0));
|
||||
if (scalar_copy) {
|
||||
ir.SetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.dst.reg), source_mask);
|
||||
ir.SetScalarMaskTag(static_cast<IR::ScalarReg>(inst.dst.reg), source_mask_valid);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
case Decoder::Opcode::S_WQM_B64: {
|
||||
if (!IsExecOrVcc(inst.dst) && !IsExecOrVcc(inst.src0)) {
|
||||
const auto mask_valid = ReadMaskValid(inst.src0);
|
||||
const auto invocation_result =
|
||||
IR::U1(ir.Emit(IR::ValueOpcode::WqmMask, {ReadMask(inst.src[0])}));
|
||||
IR::U1(ir.Emit(IR::ValueOpcode::WqmMask, {ReadMask(inst.src0)}));
|
||||
const auto result = IR::U64(
|
||||
ir.Emit(IR::ValueOpcode::WqmU64, {ReadOperand(inst.src[0], IR::Type::U64)}));
|
||||
WriteOperand(inst.dst, result);
|
||||
if (inst.dst.kind == IR::OperandKind::Register &&
|
||||
inst.dst.reg.file == IR::RegisterFile::Scalar) {
|
||||
const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg.index);
|
||||
ir.Emit(IR::ValueOpcode::WqmU64, {ReadOperand(inst.src0, IR::Type::U64)}));
|
||||
WriteOperand(DestinationOperand(inst), result);
|
||||
if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
|
||||
const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg);
|
||||
ir.SetThreadBitScalarReg(dst, invocation_result);
|
||||
ir.SetScalarMaskTag(dst, mask_valid);
|
||||
const auto raw_nonzero = IR::U1(
|
||||
ir.Emit(IR::ValueOpcode::INotEqual64, {result, IR::Value(uint64_t {0})}));
|
||||
ir.SetScc(IR::U1(ir.Emit(
|
||||
IR::ValueOpcode::SelectU1, {mask_valid, invocation_result, raw_nonzero})));
|
||||
ir.SetScc(IR::U1(ir.Emit(IR::ValueOpcode::SelectU1,
|
||||
{mask_valid, invocation_result, raw_nonzero})));
|
||||
} else {
|
||||
ir.SetScc(IR::U1(
|
||||
ir.Emit(IR::ValueOpcode::INotEqual64, {result, IR::Value(uint64_t {0})})));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
const auto result = IR::U1(ir.Emit(IR::ValueOpcode::WqmMask, {ReadMask(inst.src[0])}));
|
||||
const auto result = IR::U1(ir.Emit(IR::ValueOpcode::WqmMask, {ReadMask(inst.src0)}));
|
||||
WriteMask64(inst.dst, result);
|
||||
ir.SetScc(result);
|
||||
return true;
|
||||
@@ -212,29 +338,56 @@ bool Translator::TranslateMove(const IR::Instruction& inst) {
|
||||
}
|
||||
}
|
||||
|
||||
bool Translator::TranslateLaneOperation(const IR::Instruction& inst) {
|
||||
bool Translator::TranslateLaneOperation(const Decoder::Instruction& inst, std::string* error) {
|
||||
const auto lane_mask = IR::U32(IR::Value(current_wave_size == 32u ? 31u : 63u));
|
||||
switch (inst.op) {
|
||||
case IR::Opcode::MoveRelSourceU32: {
|
||||
EXIT_IF(inst.src[0].kind != IR::OperandKind::Register ||
|
||||
inst.src[0].reg.file != IR::RegisterFile::Vector);
|
||||
const auto base = inst.src[0].reg.index;
|
||||
const auto m0 = ir.BitwiseAnd(ReadU32(inst.src[1]), IR::U32(IR::Value(0xffu)));
|
||||
switch (inst.opcode) {
|
||||
case Decoder::Opcode::V_MOVRELS_B32: {
|
||||
if (inst.dst.kind != Decoder::OperandKind::Vgpr ||
|
||||
inst.src0.kind != Decoder::OperandKind::Vgpr) {
|
||||
if (error != nullptr) {
|
||||
*error = "V_MOVRELS_B32 requires VGPR source and destination";
|
||||
}
|
||||
return false;
|
||||
}
|
||||
if (inst.dst.sdwa_sel != 6u || inst.dst.omod != 0u || inst.dst.clamp ||
|
||||
inst.src0.sdwa_sel != 6u || inst.src0.sdwa_sext || inst.src0.negate ||
|
||||
inst.src0.absolute || inst.src0.dpp) {
|
||||
if (error != nullptr) {
|
||||
*error = "V_MOVRELS_B32 modifiers are not implemented";
|
||||
}
|
||||
return false;
|
||||
}
|
||||
const auto base = inst.src0.reg;
|
||||
const auto m0 = ir.BitwiseAnd(ReadU32(ConditionOperand(Decoder::OperandKind::M0)),
|
||||
IR::U32(IR::Value(0xffu)));
|
||||
auto selected = ir.GetVectorReg(static_cast<IR::VectorReg>(base));
|
||||
for (uint32_t index = base + 1u; index < current_vector_limit; index++) {
|
||||
const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
|
||||
selected =
|
||||
ir.Select(match, ir.GetVectorReg(static_cast<IR::VectorReg>(index)), selected);
|
||||
}
|
||||
WriteOperand(inst.dst, selected);
|
||||
WriteOperand(DestinationOperand(inst), selected);
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::MoveRelDestU32: {
|
||||
EXIT_IF(inst.dst.kind != IR::OperandKind::Register ||
|
||||
inst.dst.reg.file != IR::RegisterFile::Vector);
|
||||
const auto base = inst.dst.reg.index;
|
||||
const auto value = ReadU32(inst.src[0]);
|
||||
const auto m0 = ir.BitwiseAnd(ReadU32(inst.src[1]), IR::U32(IR::Value(0xffu)));
|
||||
case Decoder::Opcode::V_MOVRELD_B32: {
|
||||
if (inst.dst.kind != Decoder::OperandKind::Vgpr) {
|
||||
if (error != nullptr) {
|
||||
*error = "V_MOVRELD_B32 requires VGPR destination";
|
||||
}
|
||||
return false;
|
||||
}
|
||||
if (inst.dst.sdwa_sel != 6u || inst.dst.omod != 0u || inst.dst.clamp ||
|
||||
inst.src0.sdwa_sel != 6u || inst.src0.sdwa_sext || inst.src0.negate ||
|
||||
inst.src0.absolute || inst.src0.dpp) {
|
||||
if (error != nullptr) {
|
||||
*error = "V_MOVRELD_B32 modifiers are not implemented";
|
||||
}
|
||||
return false;
|
||||
}
|
||||
const auto base = inst.dst.reg;
|
||||
const auto value = ReadU32(inst.src0);
|
||||
const auto m0 = ir.BitwiseAnd(ReadU32(ConditionOperand(Decoder::OperandKind::M0)),
|
||||
IR::U32(IR::Value(0xffu)));
|
||||
for (uint32_t index = base; index < current_vector_limit; index++) {
|
||||
const auto reg = static_cast<IR::VectorReg>(index);
|
||||
const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
|
||||
@@ -243,41 +396,38 @@ bool Translator::TranslateLaneOperation(const IR::Instruction& inst) {
|
||||
}
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::ReadFirstLaneU32: {
|
||||
case Decoder::Opcode::V_READFIRSTLANE_B32: {
|
||||
const auto result =
|
||||
ir.Emit(IR::ValueOpcode::ReadFirstLane, {ReadU32(inst.src[0]), ir.GetExec()});
|
||||
WriteOperand(inst.dst, result);
|
||||
ir.Emit(IR::ValueOpcode::ReadFirstLane, {ReadU32(inst.src0), ir.GetExec()});
|
||||
WriteOperand(DestinationOperand(inst), result);
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::ReadLaneU32: {
|
||||
const auto lane = ir.BitwiseAnd(ReadU32(inst.src[1]), lane_mask);
|
||||
WriteOperand(inst.dst,
|
||||
ir.Emit(IR::ValueOpcode::ReadLane, {ReadU32(inst.src[0]), lane}));
|
||||
case Decoder::Opcode::V_READLANE_B32: {
|
||||
const auto lane = ir.BitwiseAnd(ReadU32(inst.src1), lane_mask);
|
||||
WriteOperand(DestinationOperand(inst),
|
||||
ir.Emit(IR::ValueOpcode::ReadLane, {ReadU32(inst.src0), lane}));
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::WriteLaneU32: {
|
||||
EXIT_IF(inst.dst.kind != IR::OperandKind::Register ||
|
||||
inst.dst.reg.file != IR::RegisterFile::Vector);
|
||||
const auto reg = static_cast<IR::VectorReg>(inst.dst.reg.index);
|
||||
const auto lane = ir.BitwiseAnd(ReadU32(inst.src[1]), lane_mask);
|
||||
const auto result = IR::U32(ir.Emit(
|
||||
IR::ValueOpcode::WriteLane, {ir.GetVectorReg(reg), ReadU32(inst.src[0]), lane}));
|
||||
// V_WRITELANE_B32 ignores EXEC; bypass the ordinary VGPR destination path.
|
||||
case Decoder::Opcode::V_WRITELANE_B32: {
|
||||
EXIT_IF(inst.dst.kind != Decoder::OperandKind::Vgpr);
|
||||
const auto reg = static_cast<IR::VectorReg>(inst.dst.reg);
|
||||
const auto lane = ir.BitwiseAnd(ReadU32(inst.src1), lane_mask);
|
||||
const auto result = IR::U32(ir.Emit(IR::ValueOpcode::WriteLane,
|
||||
{ir.GetVectorReg(reg), ReadU32(inst.src0), lane}));
|
||||
ir.SetVectorReg(reg, result);
|
||||
return true;
|
||||
}
|
||||
case IR::Opcode::Permlane16B32:
|
||||
case IR::Opcode::Permlanex16B32: {
|
||||
case Decoder::Opcode::V_PERMLANE16_B32:
|
||||
case Decoder::Opcode::V_PERMLANEX16_B32: {
|
||||
const IR::PermlaneFlags flags {
|
||||
.x16 = inst.op == IR::Opcode::Permlanex16B32,
|
||||
.x16 = inst.opcode == Decoder::Opcode::V_PERMLANEX16_B32,
|
||||
.fetch_inactive = inst.dst.op_sel,
|
||||
.bound_control = inst.dst.op_sel_hi,
|
||||
};
|
||||
const auto result = ir.Emit(
|
||||
IR::ValueOpcode::Permlane16U32,
|
||||
{ReadU32(inst.src[0]), ReadU32(inst.src[1]), ReadU32(inst.src[2]), ir.GetExec()},
|
||||
flags);
|
||||
auto dst = inst.dst;
|
||||
{ReadU32(inst.src0), ReadU32(inst.src1), ReadU32(inst.src2), ir.GetExec()}, flags);
|
||||
auto dst = DestinationOperand(inst);
|
||||
dst.op_sel = false;
|
||||
dst.op_sel_hi = false;
|
||||
WriteOperand(dst, result);
|
||||
@@ -287,4 +437,4 @@ bool Translator::TranslateLaneOperation(const IR::Instruction& inst) {
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Libs::Graphics::ShaderRecompiler::Frontend::Detail
|
||||
} // namespace Libs::Graphics::ShaderRecompiler::Frontend
|
||||
|
||||
Reference in New Issue
Block a user