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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-28 05:46:56 +01:00
shader: remove second IR layer
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@@ -6,7 +6,7 @@
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#include "graphics/guest_gpu/gpu_defs.h"
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#include "graphics/shader/recompiler/frontend/cfg/ShaderCFG.h"
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#include "graphics/shader/recompiler/frontend/decode/ShaderDecoder.h"
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#include "graphics/shader/recompiler/ir/opcodes/Opcodes.h"
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#include "graphics/shader/recompiler/ir/Block.h"
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#include "graphics/shader/recompiler/ir/opcodes/ValueOpcodes.h"
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#include "graphics/shader/shader.h"
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@@ -19,47 +19,6 @@
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namespace Libs::Graphics::ShaderRecompiler::IR {
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struct ValueProgram;
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enum class RegisterFile { Scalar, Vector, Vcc, Exec, Scc, M0 };
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struct Register {
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RegisterFile file = RegisterFile::Scalar;
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uint32_t index = 0;
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bool operator==(const Register& other) const {
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return file == other.file && index == other.index;
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}
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};
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enum class OperandKind { Register, ImmediateU32, PcRelativeU32, PcRelativeHighU32, Null };
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struct Operand {
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OperandKind kind = OperandKind::Null;
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Register reg;
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uint32_t imm = 0;
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bool float_inline = false;
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bool sext_64 = false;
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uint32_t sdwa_sel = 6;
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uint32_t sdwa_dst_unused = 2;
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uint32_t omod = 0;
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bool sdwa_sext = false;
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bool op_sel = false;
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bool op_sel_hi = false;
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bool negate = false;
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bool negate_hi = false;
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bool absolute = false;
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bool clamp = false;
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uint32_t dpp_ctrl = 0;
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uint32_t dpp_row_mask = 0xf;
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uint32_t dpp_bank_mask = 0xf;
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bool dpp_fetch_inactive = false;
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bool dpp_bound_ctrl = false;
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bool dpp = false;
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bool operator==(const Operand& other) const = default;
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};
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enum class ResourceKind {
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None,
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ScalarBuffer,
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@@ -144,44 +103,6 @@ struct ExportInfo {
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bool operator==(const ExportInfo& other) const = default;
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};
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struct InputInfo {
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uint32_t attr = 0;
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uint32_t chan = 0;
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uint32_t component_count = 1;
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uint32_t interpolation_mode = 3;
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bool operator==(const InputInfo& other) const = default;
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};
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enum class SaveexecMode { And, Orn2, Andn1 };
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struct Instruction {
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uint32_t pc = 0;
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Opcode op = Opcode::MoveU32;
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Operand dst;
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Operand dst2;
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Operand src[4];
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uint32_t src_count = 0;
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MemoryInfo memory;
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ExportInfo export_info;
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InputInfo input_info;
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SaveexecMode saveexec_mode = SaveexecMode::And;
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bool operator==(const Instruction& other) const = default;
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};
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struct BasicBlock {
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uint32_t id = 0;
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uint32_t start_pc = 0;
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uint32_t end_pc = 0;
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uint32_t inst_begin = 0;
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uint32_t inst_end = 0;
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std::vector<uint32_t> predecessors;
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std::vector<uint32_t> successors;
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CFG::Terminator terminator;
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std::vector<Instruction> instructions;
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};
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struct DescriptorValue {
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std::array<uint32_t, 8> dwords = {};
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uint32_t dword_count = 0;
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@@ -522,6 +443,7 @@ struct ShaderInfo {
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std::vector<SampledResourcePair> sampled_pairs;
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std::vector<StageInput> inputs;
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std::vector<StageOutput> outputs;
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std::array<uint8_t, 32> vertex_fetch_components {};
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int32_t vertex_offset_sgpr = -1;
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bool has_bitwise_xor = false;
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@@ -539,7 +461,50 @@ struct SpirvRequirements {
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bool pixel_valid_mask = false;
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};
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struct BlockInfo {
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uint32_t id = 0;
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uint32_t start_pc = 0;
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uint32_t end_pc = 0;
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CFG::Terminator terminator;
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Value condition;
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Value indirect_target;
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};
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struct DescriptorSource {
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struct IndirectImage {
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uint32_t material_source = 0;
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uint32_t heap_source = 0;
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uint32_t selector_stride = 0;
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uint32_t selector_offset = 0;
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uint32_t key_arg = 0;
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bool operator==(const IndirectImage& other) const = default;
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};
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std::array<Value, 8> dwords {};
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uint32_t dword_count = 0;
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std::optional<IndirectImage> indirect_image;
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bool operator==(const DescriptorSource& other) const = default;
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};
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struct SrtRead {
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Value value;
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uint32_t flat_offset = 0;
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uint32_t use_pc = 0;
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bool operator==(const SrtRead& other) const = default;
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};
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struct Program {
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Program() = default;
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~Program();
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Program(const Program&) = delete;
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Program& operator=(const Program&) = delete;
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Program(Program&&) noexcept = default;
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Program& operator=(Program&& other) noexcept;
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ShaderType stage = ShaderType::Unknown;
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uint64_t shader_hash = 0;
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uint32_t wave_size = 64;
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@@ -549,8 +514,17 @@ struct Program {
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bool dispatcher_fallback = false;
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CFG::FailureKind cfg_failure_kind = CFG::FailureKind::None;
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std::string fallback_reason;
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std::vector<BasicBlock> blocks;
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std::shared_ptr<ValueProgram> values;
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std::vector<std::unique_ptr<Block>> block_storage;
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BlockList blocks;
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std::vector<BlockInfo> block_info;
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// Decoded MIMG/VMEM metadata carries details such as RDNA2 NSA address registers and
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// storage-image swizzles. Typed memory instructions carry a dense index into these shader-local
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// tables until those fields are consumed by emission.
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std::vector<MemoryInfo> memory_info;
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std::vector<ExportInfo> export_info;
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std::vector<DescriptorSource> descriptor_sources;
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std::vector<SrtRead> srt_reads;
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std::vector<Value> dynamic_reads;
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bool srt_plan_complete = false;
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ShaderInfo info;
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bool resource_tracking_complete = false;
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@@ -561,15 +535,13 @@ struct Program {
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std::optional<SpirvRequirements> spirv_requirements;
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};
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bool LowerProgram(const Decoder::Program& decoded, const CFG::Graph& cfg, ShaderType stage,
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uint32_t wave_size, Program& program, std::string* error);
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std::string RegisterToString(Register reg);
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std::string OperandToString(const Operand& operand);
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std::string ExportTargetKindToString(ExportTargetKind kind);
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std::string InstructionToString(const Instruction& inst);
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std::string ProgramToString(const Program& program);
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bool ValidateProgram(const Program& program, bool require_ssa, std::string* error);
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void ResolveControlFlowIdentities(Program& program);
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bool EquivalentValue(const Program& program, Value left, Value right);
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Value ResolveInvariantPhi(const Program& program, Value value);
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} // namespace Libs::Graphics::ShaderRecompiler::IR
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#endif /* EMULATOR_INCLUDE_EMULATOR_GRAPHICS_SHADER_RECOMPILER_SHADERIR_H_ */
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