1be9568a02
shader: implement RDNA2 frexp exponent
2026-08-18 03:53:44 +02:00
8ce06ccdf6
shader: route nested shared regions
2026-08-18 03:53:44 +02:00
1dbac4fd79
shader: repair nested merge structurization
2026-08-18 03:53:44 +02:00
d80fbea51d
shader: resolve subtractive dword SETPC tables
2026-08-18 03:53:44 +02:00
e7c8bcb3a4
recompiler: deduplication cleanup
2026-08-18 03:53:44 +02:00
0f3540b1ff
shader: unify stage input metadata
2026-08-18 03:53:44 +02:00
44302cbf96
shader: implement RDNA2 V_MED3_I16
2026-08-18 03:53:44 +02:00
2a1a8e72e3
shader: preserve exec-masked FLAT address roots
2026-08-18 03:53:44 +02:00
93398d6d0f
graphics: sign-extend vector bitfield extracts
2026-08-18 03:53:43 +02:00
4e343408dc
graphics: size compute LDS from shader state
2026-08-18 03:53:43 +02:00
1375d650a7
graphics: support RDNA2 dependency waits
2026-08-18 03:53:43 +02:00
d7f1bcaa19
graphics: support signed 16-bit integer packing
2026-08-18 03:53:43 +02:00
2bb396f58f
graphics: support SDWA arithmetic right shifts
2026-08-18 03:53:43 +02:00
430de9bd15
graphics: support dynamic indirect image tables
2026-08-18 03:53:43 +02:00
1c4171c9eb
graphics: accept SDWA byte conversion sources
2026-08-18 03:53:43 +02:00
443bbcbf90
graphics: separate scalar address bindings
2026-08-18 03:53:43 +02:00
83ee040b4d
graphics: specialize invariant indirect image tables
2026-08-18 03:53:43 +02:00
980d89f739
graphics: support dynamic storage mip writes
2026-08-18 03:53:43 +02:00
5e27a28ab0
shader: fix missing homogeneous semantics
2026-08-18 03:53:42 +02:00
484433b180
shader: fix V_ADD_NC_U32
2026-08-18 03:53:42 +02:00
7556a74f19
shader: implement s_bfe_i32
2026-08-18 03:53:42 +02:00
b4809e7170
Fix SPIR-V float control contract (Preserve FP32 Inf and NaN)
2026-08-18 03:53:42 +02:00
0df20eb300
fix opcode regression
2026-08-18 03:53:42 +02:00
5bfdf4267e
Optimize decoder
2026-08-18 03:53:42 +02:00
f3cdf217ea
shader: evaluate unsigned min in runtime descriptors
2026-08-18 03:53:42 +02:00
f453a752bb
shader: snapshot wide SMEM sources before writes
2026-08-18 03:53:42 +02:00
28a913894d
graphics: implement RDNA2 64-bit first-set-bit
2026-08-18 03:53:42 +02:00
0ffacf22e6
graphics: accept phi-mediated SRT cycles
2026-08-18 03:53:42 +02:00
13e87a8e58
graphics: implement RDNA2 alignbyte shader opcode
2026-08-18 03:53:42 +02:00
09fec6815f
shader: handle disabled RDNA2 traps
2026-08-18 03:53:42 +02:00
00bd19194a
shader: mask vector carry outputs by exec
2026-08-18 03:53:42 +02:00
4a7bc55afa
shader: implement RDNA2 subrev borrow
2026-08-18 03:53:42 +02:00
9c316e6988
shader: implement RDNA2 v_cmp_gt_u64
2026-08-18 03:53:42 +02:00
b42380ced6
shader_recompiler: add SSA
2026-08-18 03:53:41 +02:00
21aa7b66ce
graphics: replace raw GPU enum values with typed formats
2026-08-11 16:12:38 +02:00
67cfec9063
shader: remove redundant runtime descriptor provenance walks (perf)
2026-08-07 18:08:40 +02:00
ac64d202af
shader: implement BUFFER_ATOMIC_FMAX
2026-08-05 02:59:28 +02:00
df44ad3fac
shader: implement BUFFER_ATOMIC_FMIN, unhandled IR opcode now fails
2026-08-05 02:59:28 +02:00
0a2f4814ac
refactor(shader): centralize opcode metadata and lookup paths
2026-08-05 02:59:28 +02:00
9a3468e3a0
shader: implement V_MIN_U32
2026-08-05 02:59:28 +02:00
73da43a7be
shader: implement V_CNDMASK_B32
2026-08-05 02:59:28 +02:00
aa88d94755
shader: implement V_SUB_NC_U32
2026-08-05 02:59:27 +02:00
822ca3c10b
shader: implement S_CMP_EQ_U64
2026-08-05 02:59:27 +02:00
2b6fd699e7
shader: implement V_CMP_EQ_I64
2026-08-05 02:59:27 +02:00
53feb6cb19
graphics: log image descriptor specialization mismatches
2026-08-03 04:02:35 +02:00
86a586025f
renderer: expand rectangle lists with tessellation
...
Remove the legacy NGG rectangle workaround and its configuration toggle.
2026-08-03 00:35:02 +02:00
44d7f2a3e8
shader cfg: handle shared early exits
...
Duplicate small shared exit tails so each selection gets its own merge block. This keeps overlapping early-exit ladders on structured SPIR-V and adds a regression test.
2026-08-02 03:16:08 +02:00
2dcb90066c
shader cfg: normalize loop structure
...
Give loops one header and one continue path before SPIR-V generation. This handles conditional headers and multiple latches without falling back to a dispatcher.
2026-08-02 03:15:26 +02:00
51a33cc363
shader cfg: handle loop control branches
...
Keep simple break, continue, and repeat branches in structured control flow. Split conflicting merge blocks and add regression tests for nested loop exits.
2026-08-02 03:14:39 +02:00
43f30d3ab2
graphics: shader: ignore unused sampler border state
...
* Sampler dword 3 only matters when a clamp mode uses border color
(values >= 4). When no border mode is active, dword 3 is unused
but can still vary across loop iterations due to wave-lane spills.
This makes resource tracking think the descriptor is dynamic and
fail with "unsupported GPU selection".
* Fix by zeroing dword 3 when all clamp modes are non-border.
Signed-off-by: Claxten <claxten10@gmail.com >
2026-08-02 02:42:15 +02:00
nmzik