7492cb9577
shader: emulate DS_ORDERED_COUNT as a GDS atomic ( #1117 )
...
* feat(shader): emulate DS_ORDERED_COUNT as a GDS atomic
* fix(shader): issue one ordered-count atomic per wave
* shader: correct ordered-count addressing and wave results
Use the M0 base and pixel packer offset for the GDS counter. Broadcast the
previous value to every lane and preserve the counter when EXEC is empty.
Add GPU regressions for add/exchange with full, partial, and empty EXEC in
wave32 and wave64. The targeted DS and buffer atomic suite passes 63 cases.
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-07 01:45:37 +04:00
1195af2510
decoder: add V_CMPX_U_F32 ( #1120 )
...
feat(decoder): add V_CMPX_U_F32
2026-10-07 01:16:23 +04:00
5601861d67
shader: implement RDNA2 scalar 16-bit sign extension
2026-10-06 14:53:17 +04:00
9caec9f2c8
shader: preserve RDNA2 DLC coherence for flat address loads
2026-10-06 14:53:17 +04:00
5b826c6e4a
shader: emit native 64-bit operations where compatible
2026-10-05 20:41:03 +04:00
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
1d55272467
shader: support V_CMPX_NE_U16
2026-10-05 09:25:19 +04:00
2b1b7ed0e4
shader: FLAT opcode=0x24
2026-10-05 08:48:20 +04:00
af3011cd69
shader: add missing 64-bit integer image atomics
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:12:06 +04:00
d8be245c22
shader: separate legacy FP32 MAD rounding from fused FMA
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:11:48 +04:00
8274e517b2
shader: add FP64 min, max and rounding
...
Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
98557a83b6
shader: implement RDNA2 DS masked OR through shared atomic updates
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
efbaa17f71
shader: preserve raw EXEC and VCC bits in 64-bit scalar selects
2026-10-04 18:39:34 +04:00
dbf66b7f4f
shader: support RDNA2 BVH64 ray intersections with shared traversal
2026-10-04 18:39:34 +04:00
c17fa5b936
shader: implement RDNA2 DS forward lane permute
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
b8946fef94
shader: translate RDNA2 signed 64-bit not-equal comparisons
2026-10-04 18:39:34 +04:00
f18679e0cd
shader: mask ALIGNBYTE offsets to the two-bit selector
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
2026-10-04 18:39:34 +04:00
284d58d1d5
shader: implement RDNA2 double-precision fractional part
2026-10-04 18:39:34 +04:00
e4aca7a60b
shader: initialize EXEC from requested dispatch thread extents
...
Co-authored-by: TheCruZ <thecruzwtf@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
2026-10-04 18:39:34 +04:00
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
bd611bfe15
Honor explicit gather LOD with shared image mip selection
...
Co-authored-by: YuhiAida <21134775+YuhiAida@users.noreply.github.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-03 14:19:33 +04:00
ef4c5baf3a
Implement RDNA2 64-bit image atomic maximum
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-03 14:19:32 +04:00
b3e419ff11
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP ( #952 )
...
* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-02 01:15:53 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
11001c97f7
shader: add distinct mesh shader type
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
...
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
581dad7dd3
shader: implement RDNA2 FP64 equality comparisons
...
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-02 00:51:15 +04:00
64dcbe0ea1
shader: decode the combined conditional-debug branch
...
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
2026-10-02 00:51:15 +04:00
bc193f5272
shader: V_CMPX_LT_I16 + fix SDWA with SEXT
2026-09-30 20:49:20 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
35c4dca2ce
shader: add V_CMPX_NLE_F16 opcode
2026-09-29 19:13:33 +04:00
0a5774be7b
shader: support FP64 conversions used by FighterZ ( #884 )
...
shader: support float and unsigned widening to FP64
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-28 17:39:31 +04:00
0791f921f6
UFC 5 in-game ( #883 )
...
* shader: release descriptor dependencies
* shader: simplify shared-exit control flow
* shader: fix scalar memory loads
* shader: fix LDS counter bounds
* renderer: skip inactive pixel shaders
* shader: respect FP32 mode in comparisons
* renderer: fix sampler border colors
* shader: resolve descriptors from control flow
* shader: resolve descriptors before resource planning
* shader: handle scalar guards for image bounds
* shader: handle reduced guards for image loops
* shader: fix wave guards and material indices
* shader: preserve scalar buffer offset alignment and carry
* shader: prove masked loop bounds across iteration transitions
* shader: preserve source and IR before resource tracking failures
* shader: track material keys selected from active lanes
* shader: remove obsolete post-dominator analysis
* shader: follow bounds guards through control-flow joins
2026-09-28 16:03:05 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
...
Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
cf268af839
Shader: implement RDNA2 image atomic float maximum
...
Shader: implement RDNA2 image atomic float minimum
Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: frans <francois.att@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
2026-09-26 15:15:35 +04:00
3585cd8f03
shader: simplify translator dispatch to void handlers
2026-09-25 14:27:09 +04:00
ff54608569
shader: add V_CMPX_O_F32 opcode
2026-09-25 14:27:09 +04:00
5a705dd15f
shader: support V_CMPX_EQ_U16 ( #816 )
...
* shader: support V_CMPX_EQ_U16
Decode gfx11 VOPC 0xba and lower it as an unsigned 16-bit equality
compare with CMPX EXEC-mask semantics.
🤖 Generated with Codebuff 🤖
Co-Authored-By: Codebuff <noreply@codebuff.com >
* shader: correct CMPX EQ U16 runtime expectations
Remove the added CFG tests and correct two EXEC expectations in the compute regression case.
---------
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
Co-authored-by: Codebuff <noreply@codebuff.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-25 02:27:44 +04:00
dc9280d75d
shader: add GLC/DLC buffer cache policy support
...
Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
e43c242683
shader: add S_MEMREALTIME opcode
...
Co-authored-by: Maxime Allanic <maxime@allanic.me >
Co-authored-by: Mac <me@itsmemac.com >
2026-09-24 20:46:04 +04:00
fcf0f3b67e
shader: fold the lane test after a pixel shader's entry s_wqm ( #801 )
...
Preserve live lane predicates through RDNA2 whole-quad expansion
Keep the source-live predicate when WQM expands a scalar mask, so entry masks remain known live without an instruction pre-scan. Preserve scalar mask values, SCC, half writes, and raw-source behavior.
Cover entry pixel masks, cross-half copies, and scalar/high-word sources with existing shader regression suites.
Co-authored-by: nmzik <Nmzik@mail.ru >
Co-authored-by: Douglas <douglasproducoes21@gmail.com >
2026-09-24 12:02:19 +04:00
3dc3fd0197
shader: implement DS_INC_U32 and DS_DEC_U32 ( #790 )
2026-09-24 00:45:12 +04:00
fc86509aac
shader: support DS_WRITE_B8_D16_HI ( #794 )
...
Decode GFX10 DS opcode 0xa0 as DS_WRITE_B8_D16_HI (next to
DS_WRITE_B16_D16_HI at 0xa1) and lower it through the existing 8-bit
shared-memory write. The stored byte is bits 23:16 of the data VGPR,
selected with SDWA BYTE_2 on src1.
Add captured-instruction decode coverage (from GTA V, PPSA04264) and a
runtime regression that writes one byte of a distinctive source value
into a pre-filled LDS dword.
2026-09-24 00:44:39 +04:00
7d7267cc56
Translate NGG mesh prolog with guest wave32 width
2026-09-23 22:50:51 +04:00
476204cd4b
Initialize native NGG vertex launch state and wave size
2026-09-22 11:11:36 +04:00
549495575c
shader: add S_BITCMP0_B64 and S_BITCMP1_B64 ( #688 )
...
* shader: add S_BITCMP0_B64 and S_BITCMP1_B64
* test: move S_BITCMP_B64 coverage to compute suite
* test: use the existing compute CTest entry for bit comparisons
* test: remove the dedicated S_BITCMP_B64 command-line selector
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-20 19:36:12 +04:00
ea6aae8577
shader: V_MAD_I16
2026-09-19 04:43:48 +04:00
5b7d3343cf
shader: V_CMP_NLT_F16
2026-09-18 12:25:13 +04:00
394e638905
shader: V_MUL_LO_U16
2026-09-18 11:21:57 +04:00
95d3d9d3ad
shader: fix packed integer negation
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-09-18 09:11:55 +04:00
NeySlim