e93b4b0378
shader: support returning 32-bit LDS compare-exchange (DS_CMPST_RTN_B32) ( #1578 )
...
* shader: support DS_CMPST_RTN_B32
Assassin's Creed Valhalla (PPSA01490, #281 ) stops on DS opcode 0x30 in a
compute shader. DS compares DATA and stores DATA2, the opposite of
BUFFER_ATOMIC_CMPSWAP, so the 32-bit atomic path swaps the two for this
opcode, as the 64-bit form does.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com >
* shader: reject unsupported GDS compare-store variant
---------
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com >
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-17 04:37:16 +02:00
02ead0e2e1
shader: 64-bit buffer atomic add (BUFFER_ATOMIC_ADD_X2)
2026-10-17 04:09:54 +02:00
dd429ef858
shader: decode high-half formatted buffer stores
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:00 +02:00
bc2664cefa
shader: decode comparison gathers with explicit LOD
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-15 22:28:00 +02:00
2f6ee0e91d
shader: support RDNA2 high-half short buffer stores
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 20:55:50 +02:00
4843d8d942
shader: support packed D16 XYZW formatted buffer stores
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 19:35:08 +02:00
e0586cc85a
shader: decode unsigned byte loads into preserved low halves
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 18:21:58 +02:00
8d18be71db
shader: decode upper-half byte stores through shared operand selection
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 04:20:02 +02:00
6abfe3bbe4
shader: share formatted loads and support packed D16 XYZW buffers
...
Co-authored-by: fxpw <fxpw@outlook.com >
2026-10-14 04:09:57 +02:00
9e41d8320a
shader: support returning 64-bit LDS max and compare-exchange
2026-10-13 21:33:50 +00:00
56738aa4e1
shader: sample packed normalized images with one bilinear gather
2026-10-13 21:27:07 +00:00
679be25c37
shader: recognize remaining disabled debug branches
2026-10-10 04:31:55 +02:00
fa56c5eae9
shader: add scalar zero-bit count and search operations
2026-10-10 04:31:55 +02:00
d247d3d60c
shader: complete signed 64-bit integer comparisons
2026-10-10 03:36:25 +02:00
59183dbfa8
shader: add missing F64 VOPC compares
...
Co-authored-by: Hector Mödinger S. <hectormodinger@gmail.com >
2026-10-09 21:01:51 +02:00
3e9f88bf79
shader: isolate SWAPPC work from ordinary shader paths
2026-10-09 17:27:07 +02:00
bb5edbd490
shader: expose graphics compute queue fields to GETREG
2026-10-09 15:06:39 +00:00
1818aae562
shader: link scalar leaf calls only for SWAPPC programs
...
Co-authored-by: Behzad <behzadkhan1736@gmail.com >
2026-10-09 15:06:39 +00:00
a31e2cd361
shader: BUFFER_LOAD_SHORT_D16_HI
2026-10-09 12:57:04 +02:00
1bd282ec0a
shader: BUFFER_LOAD_SHORT_D16
2026-10-09 12:57:04 +02:00
7881c69a54
shader: decode v_cmp_class_f16
2026-10-08 01:10:49 +04:00
9e666e4dd2
shader: support scalar byte sign extension
2026-10-08 01:10:49 +04:00
96eb681b90
shader: add V_MIN3_U16 opcode
2026-10-07 16:22:30 +04:00
26cce9909a
shader: add BUFFER_LOAD_FORMAT_D16_X opcode
2026-10-07 16:22:30 +04:00
5af370c257
shader: add BUFFER_STORE_FORMAT_D16_X opcode
2026-10-07 16:22:30 +04:00
bb98f26433
shader: add missing I64/U64 compare variants
2026-10-07 05:03:09 +04:00
7492cb9577
shader: emulate DS_ORDERED_COUNT as a GDS atomic ( #1117 )
...
* feat(shader): emulate DS_ORDERED_COUNT as a GDS atomic
* fix(shader): issue one ordered-count atomic per wave
* shader: correct ordered-count addressing and wave results
Use the M0 base and pixel packer offset for the GDS counter. Broadcast the
previous value to every lane and preserve the counter when EXEC is empty.
Add GPU regressions for add/exchange with full, partial, and empty EXEC in
wave32 and wave64. The targeted DS and buffer atomic suite passes 63 cases.
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-07 01:45:37 +04:00
1195af2510
decoder: add V_CMPX_U_F32 ( #1120 )
...
feat(decoder): add V_CMPX_U_F32
2026-10-07 01:16:23 +04:00
5601861d67
shader: implement RDNA2 scalar 16-bit sign extension
2026-10-06 14:53:17 +04:00
7a0e1dafd7
shader: classify native half values with shared operand decoding
2026-10-05 18:39:31 +04:00
1d55272467
shader: support V_CMPX_NE_U16
2026-10-05 09:25:19 +04:00
2b1b7ed0e4
shader: FLAT opcode=0x24
2026-10-05 08:48:20 +04:00
d8be245c22
shader: separate legacy FP32 MAD rounding from fused FMA
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-05 04:11:48 +04:00
8274e517b2
shader: add FP64 min, max and rounding
...
Co-authored-by: Çağatay Güçlü <33038942+defektu@users.noreply.github.com >
2026-10-05 02:24:51 +04:00
98557a83b6
shader: implement RDNA2 DS masked OR through shared atomic updates
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
c17fa5b936
shader: implement RDNA2 DS forward lane permute
...
Co-authored-by: shadowbeat070 <70843316+shadowbeat070@users.noreply.github.com >
2026-10-04 18:39:34 +04:00
b8946fef94
shader: translate RDNA2 signed 64-bit not-equal comparisons
2026-10-04 18:39:34 +04:00
284d58d1d5
shader: implement RDNA2 double-precision fractional part
2026-10-04 18:39:34 +04:00
f58014ff0e
shader: preserve wave-wide vector-store completion before publication
2026-10-04 18:39:34 +04:00
b3e419ff11
shader: implement 32-bit RDNA2 IMAGE_ATOMIC_CMPSWAP ( #952 )
...
* shader: implement 32-bit RDNA2 image atomic compare-and-swap
* shader: share atomic emission and correct image barriers
---------
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-10-02 01:15:53 +04:00
0d0b215fab
shader: port 64-bit ALU and atomic opcodes
2026-10-02 00:51:15 +04:00
337f432016
shader: execute PS5 BVH intersections and local FLAT stacks
...
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Jean-Philippe <github@meunier.jp >
2026-10-02 00:51:15 +04:00
581dad7dd3
shader: implement RDNA2 FP64 equality comparisons
...
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: Ali Almohaya <AliAlmohaya@gmail.com >
2026-10-02 00:51:15 +04:00
64dcbe0ea1
shader: decode the combined conditional-debug branch
...
Co-authored-by: Mac <me@itsmemac.com >
Co-authored-by: Senaxx <michelbeld@gmail.com >
Co-authored-by: BlackCAT <52720489+psnwd@users.noreply.github.com >
2026-10-02 00:51:15 +04:00
bc193f5272
shader: V_CMPX_LT_I16 + fix SDWA with SEXT
2026-09-30 20:49:20 +04:00
6799ecbc5b
shader: add native 64-bit LDS OR with shared typed storage views
2026-09-29 19:13:33 +04:00
35c4dca2ce
shader: add V_CMPX_NLE_F16 opcode
2026-09-29 19:13:33 +04:00
0a5774be7b
shader: support FP64 conversions used by FighterZ ( #884 )
...
shader: support float and unsigned widening to FP64
Co-authored-by: nmzik <Nmzik@mail.ru >
2026-09-28 17:39:31 +04:00
16b83a034c
Shader: execute RDNA2 FP64 shadow arithmetic and log denorm limits
...
Shader: disable FP64 denorm preservation controls for now
2026-09-26 15:15:35 +04:00
cf268af839
Shader: implement RDNA2 image atomic float maximum
...
Shader: implement RDNA2 image atomic float minimum
Co-authored-by: foufouadi <attar.foued@gmail.com >
Co-authored-by: frans <francois.att@gmail.com >
Co-authored-by: fxpw <fxpw@outlook.com >
Co-authored-by: Matthew Hurley <171001439+theantipopau@users.noreply.github.com >
2026-09-26 15:15:35 +04:00
Nawid3333