mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-22 03:46:53 +02:00
nmzik
336 lines
15 KiB
C++
336 lines
15 KiB
C++
#include "graphics/shader/recompiler/backend/spirv/spirvEmitterInstructions.h"
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#include <array>
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namespace Libs::Graphics::ShaderRecompiler::Spirv::Emitter {
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namespace {
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uint32_t EmitMinMaxF64(EmitterState& state, uint32_t lhs, uint32_t rhs, bool max_value) {
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const auto bits_type = TypeU32Vector(state, 2);
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const auto lhs_bits = Unary(state, spv::OpBitcast, bits_type, lhs);
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const auto rhs_bits = Unary(state, spv::OpBitcast, bits_type, rhs);
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const auto ordered = Binary(state, max_value ? spv::OpFOrdGreaterThan : spv::OpFOrdLessThan,
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TypeBool(state), lhs, rhs);
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auto result = Select(state, TypeF64(state), ordered, lhs, rhs);
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// Equal values have identical bits except signed zero: min chooses -0, max chooses +0.
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const auto equal = Binary(state, spv::OpFOrdEqual, TypeBool(state), lhs, rhs);
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const auto equal_bits = Binary(state, max_value ? spv::OpBitwiseAnd : spv::OpBitwiseOr,
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bits_type, lhs_bits, rhs_bits);
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result = Select(state, TypeF64(state), equal,
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Unary(state, spv::OpBitcast, TypeF64(state), equal_bits), result);
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// Non-IEEE mode selects the other operand for NaN, including rhs when both are NaN.
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result = Select(state, TypeF64(state), Unary(state, spv::OpIsNan, TypeBool(state), rhs),
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lhs, result);
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return Select(state, TypeF64(state), Unary(state, spv::OpIsNan, TypeBool(state), lhs),
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rhs, result);
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}
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uint32_t EmitMulHigh(EmitterState& state, uint32_t lhs, uint32_t rhs, bool signed_value) {
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const auto operand_type = signed_value ? TypeI32(state) : TypeU32(state);
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const auto pair_type = signed_value ? TypeI32Pair(state) : TypeU32Pair(state);
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uint32_t lhs_operand = lhs;
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uint32_t rhs_operand = rhs;
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if (signed_value) {
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lhs_operand = Unary(state, spv::OpBitcast, TypeI32(state), lhs);
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rhs_operand = Unary(state, spv::OpBitcast, TypeI32(state), rhs);
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}
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const auto extended = state.builder.AllocateId();
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state.builder.AddFunction(signed_value ? spv::OpSMulExtended : spv::OpUMulExtended, pair_type,
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extended, lhs_operand, rhs_operand);
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const auto high = state.builder.AllocateId();
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state.builder.AddFunction(spv::OpCompositeExtract, operand_type, high, extended, 1);
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return signed_value ? Unary(state, spv::OpBitcast, TypeU32(state), high) : high;
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}
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uint32_t EmitFMinMax3(EmitterState& state, uint32_t a, uint32_t b, uint32_t c, bool max_value) {
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return EmitMinMaxF32Value(state, EmitMinMaxF32Value(state, a, b, max_value), c, max_value);
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}
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uint32_t EmitExt(EmitterState& state, uint32_t type, uint32_t opcode,
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std::initializer_list<uint32_t> args) {
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction(spv::OpExtInst, type, result, GlslStd450(state), opcode, args);
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return result;
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}
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uint32_t EmitF32ToF16RtzBits(EmitterState& state, uint32_t value) {
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// Native half conversion causes regressions; use compact integer RTZ conversion.
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const auto bits = EmitBitcastF32ToU32(state, value);
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const auto abs = EmitAndConstant(state, bits, 0x7fffffffu);
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const auto sign = EmitAndConstant(
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state, Binary(state, spv::OpShiftRightLogical, TypeU32(state), bits, ConstantU32(state, 16)),
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0x8000u);
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const auto exp = Binary(state, spv::OpShiftRightLogical, TypeU32(state), abs,
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ConstantU32(state, 23));
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const auto mant = EmitAndConstant(state, abs, 0x007fffffu);
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// Align the hidden bit to the half subnormal mantissa. Even unused shifts must be < 32.
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const auto shift = EmitUMin32(
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state, Binary(state, spv::OpISub, TypeU32(state), ConstantU32(state, 126), exp),
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ConstantU32(state, 31));
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const auto sub = Binary(state, spv::OpShiftRightLogical, TypeU32(state),
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EmitOrU32(state, mant, ConstantU32(state, 0x00800000u)), shift);
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// Drop 13 mantissa bits and rebias the exponent; finite overflow saturates to max half.
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const auto truncated = Binary(state, spv::OpShiftRightLogical, TypeU32(state), abs,
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ConstantU32(state, 13));
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const auto normal = EmitUMin32(
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state, Binary(state, spv::OpISub, TypeU32(state), truncated, ConstantU32(state, 0x1c000u)),
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ConstantU32(state, 0x7bffu));
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const auto finite = Select(state, TypeU32(state),
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EmitCompareU32Constant(state, spv::OpULessThan, abs, 0x38800000u),
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sub, normal);
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const auto nan = EmitOrU32(state, EmitAndConstant(state, truncated, 0x03ffu),
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ConstantU32(state, 0x7e00u));
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const auto special = Select(state, TypeU32(state),
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EmitCompareU32Constant(state, spv::OpIEqual, mant, 0),
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ConstantU32(state, 0x7c00u), nan);
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const auto magnitude = Select(
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state, TypeU32(state),
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EmitCompareU32Constant(state, spv::OpUGreaterThanEqual, abs, 0x7f800000u), special, finite);
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return EmitOrU32(state, sign, magnitude);
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}
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uint32_t EmitF32ToU32(EmitterState& state, uint32_t src, bool signed_value) {
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const auto trunc = EmitTruncF32Value(state, src);
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const auto converted_raw = state.builder.AllocateId();
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if (signed_value) {
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const auto converted_i = state.builder.AllocateId();
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state.builder.AddFunction(spv::OpConvertFToS, TypeI32(state), converted_i, trunc);
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state.builder.AddFunction(spv::OpBitcast, TypeU32(state), converted_raw, converted_i);
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} else {
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state.builder.AddFunction(spv::OpConvertFToU, TypeU32(state), converted_raw, trunc);
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}
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const auto nan = Unary(state, spv::OpIsNan, TypeBool(state), src);
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if (signed_value) {
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const auto below = Binary(state, spv::OpFOrdLessThanEqual, TypeBool(state), src,
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ConstantF32(state, 0xcf000000u));
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const auto above = Binary(state, spv::OpFOrdGreaterThanEqual, TypeBool(state), src,
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ConstantF32(state, 0x4f000000u));
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const auto high =
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Select(state, TypeU32(state), above, ConstantU32(state, 0x7fffffffu), converted_raw);
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const auto low =
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Select(state, TypeU32(state), below, ConstantU32(state, 0x80000000u), high);
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return Select(state, TypeU32(state), nan, ConstantU32(state, 0), low);
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}
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const auto below =
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Binary(state, spv::OpFOrdLessThanEqual, TypeBool(state), src, ConstantF32(state, 0));
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const auto above = Binary(state, spv::OpFOrdGreaterThanEqual, TypeBool(state), src,
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ConstantF32(state, 0x4f800000u));
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const auto zero = Binary(state, spv::OpLogicalOr, TypeBool(state), nan, below);
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const auto high =
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Select(state, TypeU32(state), above, ConstantU32(state, 0xffffffffu), converted_raw);
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return Select(state, TypeU32(state), zero, ConstantU32(state, 0), high);
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}
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} // namespace
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uint32_t EmitFPFma32(EmitterState& state, uint32_t a, uint32_t b, uint32_t c) {
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const auto result = EmitGlsl<GLSLstd450Fma, IR::Type::F32>(state, a, b, c);
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state.builder.AddAnnotation(spv::OpDecorate, result, spv::DecorationNoContraction);
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return result;
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}
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uint32_t EmitFPMad32(EmitterState& state, uint32_t a, uint32_t b, uint32_t c) {
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// Explicit denormal checks typically drop 3DMiniGolf menu FPS from 28-29 to 21-24
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// on NVIDIA RTX 5080 Laptop GPU, so leave them disabled for this experiment.
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// a = EmitFlushF32DenormToSignedZero(state, a);
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// b = EmitFlushF32DenormToSignedZero(state, b);
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// c = EmitFlushF32DenormToSignedZero(state, c);
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const auto product = EmitFPMul32(state, a, b);
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state.builder.AddAnnotation(spv::OpDecorate, product, spv::DecorationNoContraction);
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// const auto sum = EmitFPAdd32(state, EmitFlushF32DenormToSignedZero(state, product), c);
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const auto sum = EmitFPAdd32(state, product, c);
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state.builder.AddAnnotation(spv::OpDecorate, sum, spv::DecorationNoContraction);
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// return EmitFlushF32DenormToSignedZero(state, sum);
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return sum;
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}
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uint32_t EmitConvertU16U32(EmitterState& state, uint32_t arg0) {
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return EmitNative<spv::OpBitwiseAnd, IR::Type::U16>(state, arg0, ConstantU32(state, 0xffffu));
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}
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uint32_t EmitConvertU8U32(EmitterState& state, uint32_t arg0) {
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return EmitNative<spv::OpBitwiseAnd, IR::Type::U8>(state, arg0, ConstantU32(state, 0xffu));
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}
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uint32_t EmitConvertF16F32(EmitterState& state, uint32_t arg0) {
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const auto pair = state.builder.AllocateId();
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state.builder.AddFunction(spv::OpCompositeConstruct, TypeF32Vector(state, 2), pair, arg0,
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ConstantF32(state, 0));
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return EmitPackHalf2x16(state, pair);
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}
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uint32_t EmitConvertS32F32(EmitterState& state, uint32_t arg0) {
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return EmitF32ToU32(state, arg0, true);
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}
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uint32_t EmitConvertU32F32(EmitterState& state, uint32_t arg0) {
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return EmitF32ToU32(state, arg0, false);
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}
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uint32_t EmitConvertF32F64(EmitterState& state, uint32_t arg0) {
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const auto converted = Unary(state, spv::OpFConvert, TypeF32(state), arg0);
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const auto source = EmitNative<spv::OpCompositeExtract, IR::Type::U32>(
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state, Unary(state, spv::OpBitcast, TypeU32Vector(state, 2), arg0), 1u);
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const auto exponent = EmitAndConstant(state, source, 0x7ff00000u);
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const auto overflow =
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Binary(state, spv::OpLogicalAnd, TypeBool(state),
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EmitCompareU32Constant(state, spv::OpUGreaterThan, exponent, 0x47e00000u),
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EmitCompareU32Constant(state, spv::OpULessThan, exponent, 0x7ff00000u));
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const auto clamped = EmitOrU32(state, EmitAndConstant(state, source, 0x80000000u),
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ConstantU32(state, 0x7f7fffffu));
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return EmitFlushF32DenormToSignedZero(
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state, Select(state, TypeF32(state), overflow,
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Unary(state, spv::OpBitcast, TypeF32(state), clamped), converted));
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}
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uint32_t EmitConvertF64F32(EmitterState& state, uint32_t arg0) {
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return EmitNative<spv::OpFConvert, IR::Type::F64>(state,
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EmitFlushF32DenormToSignedZero(state, arg0));
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}
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uint32_t EmitCompositeConstructU64(ValueEmitContext& ctx, uint32_t arg0, IR::Value arg1) {
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arg1 = arg1.Resolve();
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return arg1.IsImmediate() && arg1.U32() == 0u
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? Unary(ctx.state, spv::OpUConvert, TypeU64(ctx.state), arg0)
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: PackU64(ctx.state, arg0, ctx.Def(arg1));
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}
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uint32_t EmitCompositeExtractU64(EmitterState& state, uint32_t arg0, IR::Value arg1) {
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const auto value = arg1.U32() == 0u ? arg0
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: Binary(state, spv::OpShiftRightLogical, TypeU64(state),
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arg0, ConstantU32(state, 32));
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return Unary(state, spv::OpUConvert, TypeU32(state), value);
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}
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uint32_t EmitCompositeExtractU32x2(EmitterState& state, uint32_t arg0, IR::Value arg1) {
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return EmitNative<spv::OpCompositeExtract, IR::Type::U32>(state, arg0, arg1.U32());
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}
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uint32_t EmitPackFloat2x16Rtz(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitNative<spv::OpBitFieldInsert, IR::Type::U32>(
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state, EmitF32ToF16RtzBits(state, arg0), EmitF32ToF16RtzBits(state, arg1),
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ConstantU32(state, 16), ConstantU32(state, 16));
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}
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uint32_t EmitFPSaturate32(EmitterState& state, uint32_t arg0) {
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// The clamp modifier runs in DX10 clamp mode: NaN becomes 0, as NClamp's NMax step does.
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return EmitExt(state, TypeF32(state), GLSLstd450NClamp,
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{arg0, ConstantF32(state, 0), ConstantF32(state, 0x3f800000u)});
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}
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uint32_t EmitSMulHi(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMulHigh(state, arg0, arg1, true);
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}
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uint32_t EmitUMulHi(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMulHigh(state, arg0, arg1, false);
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}
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uint32_t EmitSMinTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitSMin32(state, arg0, EmitSMin32(state, arg1, arg2));
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}
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uint32_t EmitSMaxTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitSMax32(state, arg0, EmitSMax32(state, arg1, arg2));
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}
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uint32_t EmitUMinTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitUMin32(state, arg0, EmitUMin32(state, arg1, arg2));
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}
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uint32_t EmitUMaxTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitUMax32(state, arg0, EmitUMax32(state, arg1, arg2));
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}
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uint32_t EmitSMedTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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const auto high_min = EmitSMin32(state, EmitSMax32(state, arg0, arg1), arg2);
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return EmitSMax32(state, EmitSMin32(state, arg0, arg1), high_min);
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}
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uint32_t EmitUMedTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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const auto high_min = EmitUMin32(state, EmitUMax32(state, arg0, arg1), arg2);
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return EmitUMax32(state, EmitUMin32(state, arg0, arg1), high_min);
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}
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uint32_t EmitFPMin32(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMinMaxF32Value(state, arg0, arg1, false);
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}
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uint32_t EmitFPMax32(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMinMaxF32Value(state, arg0, arg1, true);
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}
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uint32_t EmitFPMin64(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMinMaxF64(state, arg0, arg1, false);
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}
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uint32_t EmitFPMax64(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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return EmitMinMaxF64(state, arg0, arg1, true);
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}
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uint32_t EmitFPMinTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitFMinMax3(state, arg0, arg1, arg2, false);
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}
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uint32_t EmitFPMaxTri32(EmitterState& state, uint32_t arg0, uint32_t arg1, uint32_t arg2) {
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return EmitFMinMax3(state, arg0, arg1, arg2, true);
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}
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uint32_t EmitFPRecip32(EmitterState& state, uint32_t arg0) {
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const auto source = EmitFlushF32DenormToSignedZero(state, arg0);
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return Binary(state, spv::OpFDiv, TypeF32(state), ConstantF32(state, 0x3f800000u), source);
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}
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uint32_t EmitFPRecip64(EmitterState& state, uint32_t arg0) {
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const auto one = state.builder.Constant(spv::OpConstant, TypeF64(state), 0u, 0x3ff00000u);
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return EmitNative<spv::OpFDiv, IR::Type::F64>(state, one, arg0);
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}
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uint32_t EmitFPRecipIFlag32(EmitterState& state, uint32_t arg0) {
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// Integer-to-float inputs used by IFLAG cannot be denormal.
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return Binary(state, spv::OpFDiv, TypeF32(state), ConstantF32(state, 0x3f800000u), arg0);
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}
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uint32_t EmitFPRecipSqrt32(EmitterState& state, uint32_t arg0) {
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return EmitExt(state, TypeF32(state), GLSLstd450InverseSqrt,
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{EmitFlushF32DenormToSignedZero(state, arg0)});
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}
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uint32_t EmitFPSqrt(EmitterState& state, uint32_t arg0) {
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return EmitExt(state, TypeF32(state), GLSLstd450Sqrt,
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{EmitFlushF32DenormToSignedZero(state, arg0)});
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}
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uint32_t EmitFPExp2(EmitterState& state, uint32_t arg0) {
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return EmitExt(state, TypeF32(state), GLSLstd450Exp2,
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{EmitFlushF32DenormToSignedZero(state, arg0)});
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}
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uint32_t EmitFPLog2(EmitterState& state, uint32_t arg0) {
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return EmitExt(state, TypeF32(state), GLSLstd450Log2,
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{EmitFlushF32DenormToSignedZero(state, arg0)});
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}
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uint32_t EmitFPLdexp(EmitterState& state, uint32_t arg0, uint32_t arg1) {
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const auto exponent = Unary(state, spv::OpBitcast, TypeI32(state), arg1);
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return EmitExt(state, TypeF32(state), GLSLstd450Ldexp, {arg0, exponent});
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}
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uint32_t EmitFPSin(EmitterState& state, uint32_t arg0) {
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auto source = EmitTrigCycleF32(state, arg0, true);
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source = Binary(state, spv::OpFMul, TypeF32(state), source, ConstantF32(state, 0x40c90fdbu));
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return EmitExt(state, TypeF32(state), GLSLstd450Sin, {source});
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}
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uint32_t EmitFPCos(EmitterState& state, uint32_t arg0) {
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auto source = EmitTrigCycleF32(state, arg0, false);
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source = Binary(state, spv::OpFMul, TypeF32(state), source, ConstantF32(state, 0x40c90fdbu));
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return EmitExt(state, TypeF32(state), GLSLstd450Cos, {source});
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Spirv::Emitter
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