mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 02:47:02 +02:00
nmzik
362 lines
15 KiB
C++
362 lines
15 KiB
C++
#include "common/assert.h"
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#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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namespace Libs::Graphics::ShaderRecompiler::Frontend {
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namespace {
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bool IsExecOrVcc(const Decoder::Operand& operand) {
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switch (operand.kind) {
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case Decoder::OperandKind::ExecLo:
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case Decoder::OperandKind::ExecHi:
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case Decoder::OperandKind::VccLo:
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case Decoder::OperandKind::VccHi: return true;
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default: return false;
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}
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}
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Decoder::Operand ConditionOperand(Decoder::OperandKind kind) {
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Decoder::Operand operand;
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operand.kind = kind;
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return operand;
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}
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} // namespace
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void Translator::S_SAVEEXEC(const Decoder::Instruction& inst, IR::ValueOpcode operation,
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bool negate_exec, bool negate_source, bool write_64) {
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const auto old = ir.GetExec();
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const auto src = ReadMask(inst.src0);
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const auto lhs = negate_exec ? ir.LogicalNot(old) : old;
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const auto rhs = negate_source ? ir.LogicalNot(src) : src;
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auto result = IR::U1(ir.Emit(operation, {lhs, rhs}));
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if (write_64) {
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WriteMask(inst.dst, old, true);
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} else {
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WriteRawU32(inst.dst, ir.GetExecLo());
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if (current_wave_size == 64u) {
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const auto low_half =
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ir.ULessThan(IR::U32(ir.Emit(IR::ValueOpcode::LaneId)), IR::U32(IR::Value(32u)));
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result = IR::U1(ir.Emit(IR::ValueOpcode::SelectU1, {low_half, result, old}));
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}
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}
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const auto mask = BallotMask(result);
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ir.SetExec(result);
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ir.SetExecLo(mask[0]);
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ir.SetExecHi(mask[1]);
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ir.SetScc(
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ir.INotEqual(write_64 ? ir.BitwiseOr(mask[0], mask[1]) : mask[0], IR::U32(IR::Value(0u))));
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}
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void Translator::ADD_U32(const Decoder::Instruction& inst, bool vector, bool use_carry_in) {
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const auto zero = IR::U32(IR::Value(0u));
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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const auto carry_in = !use_carry_in ? zero
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: vector ? ConditionBit(inst.src2)
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: ConditionBit(ConditionOperand(Decoder::OperandKind::Scc));
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const auto add0 = ir.Emit(IR::ValueOpcode::IAddCarry32, {lhs, rhs});
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const auto partial = ir.CompositeExtract(add0, 0);
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const auto carry0 = ir.CompositeExtract(add0, 1);
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const auto add1 = ir.Emit(IR::ValueOpcode::IAddCarry32, {partial, carry_in});
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const auto result = ir.CompositeExtract(add1, 0);
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const auto carry1 = ir.CompositeExtract(add1, 1);
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const auto carry = ir.INotEqual(ir.BitwiseOr(carry0, carry1), zero);
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WriteOperand(DestinationOperand(inst), result);
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if (vector) {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), carry));
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} else {
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ir.SetScc(carry);
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}
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}
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void Translator::SUB_U32(const Decoder::Instruction& inst, bool vector, bool reverse) {
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const auto lhs = ReadU32(reverse ? inst.src1 : inst.src0);
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const auto rhs = ReadU32(reverse ? inst.src0 : inst.src1);
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const auto result = ir.ISub(lhs, rhs);
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const auto borrow = ir.UGreaterThan(rhs, lhs);
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WriteOperand(DestinationOperand(inst), result);
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if (vector) {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), borrow));
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} else {
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ir.SetScc(borrow);
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}
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}
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void Translator::SUBB_U32(const Decoder::Instruction& inst, bool vector, bool reverse) {
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const auto lhs = ReadU32(reverse ? inst.src1 : inst.src0);
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const auto rhs = ReadU32(reverse ? inst.src0 : inst.src1);
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const auto borrow_in = vector ? ConditionBit(inst.src2)
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: ConditionBit(ConditionOperand(Decoder::OperandKind::Scc));
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const auto partial = ir.ISub(lhs, rhs);
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const auto result = ir.ISub(partial, borrow_in);
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const auto borrow0 = ir.UGreaterThan(rhs, lhs);
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const auto borrow1 = ir.UGreaterThan(borrow_in, partial);
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const auto borrow = ir.LogicalOr(borrow0, borrow1);
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WriteOperand(DestinationOperand(inst), result);
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if (vector) {
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WriteMask(inst.dst2, ir.LogicalAnd(ir.GetExec(), borrow));
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} else {
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ir.SetScc(borrow);
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}
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}
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void Translator::S_ABSDIFF_I32(const Decoder::Instruction& inst) {
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const auto difference = ir.ISub(ReadU32(inst.src0), ReadU32(inst.src1));
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const auto result = IR::U32(ir.Emit(IR::ValueOpcode::IAbs32, {difference}));
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WriteOperand(DestinationOperand(inst), result);
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ir.SetScc(ir.INotEqual(result, IR::U32(IR::Value(0u))));
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}
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void Translator::S_ADD_SUB_I32(const Decoder::Instruction& inst, bool subtract) {
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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const auto result = subtract ? ir.ISub(lhs, rhs) : ir.IAdd(lhs, rhs);
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const auto shift = IR::U32(IR::Value(31u));
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const auto lhs_sign = ir.ShiftRightLogical(lhs, shift);
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const auto rhs_sign = ir.ShiftRightLogical(rhs, shift);
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const auto out_sign = ir.ShiftRightLogical(result, shift);
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const auto inputs = subtract ? ir.INotEqual(lhs_sign, rhs_sign) : ir.IEqual(lhs_sign, rhs_sign);
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const auto changed = ir.INotEqual(lhs_sign, out_sign);
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WriteOperand(DestinationOperand(inst), result);
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ir.SetScc(ir.LogicalAnd(inputs, changed));
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}
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void Translator::S_LSHL_ADD_U32(const Decoder::Instruction& inst, uint32_t shift_amount) {
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const auto lhs = ReadU32(inst.src0);
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const auto shift = IR::U32(IR::Value(shift_amount));
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const auto rhs = ReadU32(inst.src1);
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const auto shifted = ir.ShiftLeftLogical(lhs, shift);
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const auto result = ir.IAdd(shifted, rhs);
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const auto add_carry = ir.ULessThan(result, shifted);
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const auto inverse_shift = ir.ISub(IR::U32(IR::Value(32u)), shift);
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const auto shifted_out = ir.ShiftRightLogical(lhs, inverse_shift);
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const auto shift_carry = ir.INotEqual(shifted_out, IR::U32(IR::Value(0u)));
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WriteOperand(DestinationOperand(inst), result);
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ir.SetScc(ir.LogicalOr(add_carry, shift_carry));
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}
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void Translator::ScalarMinMax32(const Decoder::Instruction& inst, IR::ValueOpcode value_opcode,
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IR::ValueOpcode compare_opcode) {
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const auto lhs = ReadU32(inst.src0);
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const auto rhs = ReadU32(inst.src1);
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WriteOperand(DestinationOperand(inst), ir.Emit(value_opcode, {lhs, rhs}));
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ir.SetScc(IR::U1(ir.Emit(compare_opcode, {lhs, rhs})));
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}
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void Translator::EmitControlNop() {
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ir.Emit(IR::ValueOpcode::ControlNop);
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}
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void Translator::EmitWaitcnt() {
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ir.Emit(IR::ValueOpcode::Waitcnt);
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}
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void Translator::S_BARRIER() {
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ir.Emit(IR::ValueOpcode::Barrier);
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}
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void Translator::S_SENDMSG(const Decoder::Instruction& inst) {
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if (program.stage == ShaderType::Mesh) {
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EXIT_NOT_IMPLEMENTED(inst.src0.value != 9u); // MSG_GS_ALLOC_REQ
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ir.Emit(IR::ValueOpcode::MeshAllocate, {ir.GetM0()});
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} else {
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ir.Emit(IR::ValueOpcode::Sendmsg);
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}
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}
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void Translator::S_TTRACEDATA() {
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ir.Emit(IR::ValueOpcode::TtraceData);
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}
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void Translator::S_INST_PREFETCH() {
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ir.Emit(IR::ValueOpcode::InstPrefetch);
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}
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void Translator::S_GETPC_B64(const Decoder::Instruction& inst) {
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const auto base = IR::U64(ir.Emit(IR::ValueOpcode::GetShaderBase));
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const auto address = IR::U64(
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ir.Emit(IR::ValueOpcode::IAdd64, {base, IR::Value(static_cast<uint64_t>(inst.pc) + 4u)}));
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if (inst.dst.kind == Decoder::OperandKind::Null) {
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return;
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}
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auto high = PlainOperand(inst.dst);
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switch (inst.dst.kind) {
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case Decoder::OperandKind::Sgpr:
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if (inst.dst.reg < 105u) {
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high.reg++;
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} else if (inst.dst.reg == 105u) {
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high.kind = Decoder::OperandKind::VccLo;
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high.reg = 0u;
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} else {
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EXIT("S_GETPC_B64 destination does not name a valid scalar pair at pc 0x%08x",
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inst.pc);
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}
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break;
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case Decoder::OperandKind::VccLo: high.kind = Decoder::OperandKind::VccHi; break;
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case Decoder::OperandKind::M0: high.kind = Decoder::OperandKind::Null; break;
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case Decoder::OperandKind::ExecLo: high.kind = Decoder::OperandKind::ExecHi; break;
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default:
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EXIT("S_GETPC_B64 destination does not name a valid scalar pair at pc 0x%08x", inst.pc);
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}
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const auto words = ExtractU64(address);
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WriteOperand(inst.dst, words[0]);
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WriteOperand(high, words[1]);
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}
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void Translator::S_CSELECT_B32(const Decoder::Instruction& inst) {
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const auto result = ir.Select(ir.GetScc(), ReadU32(inst.src0), ReadU32(inst.src1));
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WriteOperand(DestinationOperand(inst), result);
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}
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void Translator::ScalarSelect64(const Decoder::Instruction& inst,
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const Decoder::Operand& false_source) {
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const auto condition = ir.GetScc();
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const auto lhs = ReadU32Pair(inst.src0);
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const auto rhs = ReadU32Pair(false_source);
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const auto selected_mask = IR::U1(
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ir.Emit(IR::ValueOpcode::SelectU1, {condition, ReadMask(inst.src0), ReadMask(false_source)}));
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const auto selected_mask_valid =
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IR::U1(ir.Emit(IR::ValueOpcode::SelectU1,
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{condition, ReadMaskValid(inst.src0), ReadMaskValid(false_source)}));
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if (IsExecOrVcc(inst.dst)) {
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WriteMask(inst.dst, selected_mask, true);
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return;
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}
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WriteU32Pair(inst.dst,
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{ir.Select(condition, lhs[0], rhs[0]), ir.Select(condition, lhs[1], rhs[1])});
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if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
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const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg);
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ir.SetThreadBitScalarReg(dst, selected_mask);
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ir.SetScalarMaskTag(dst, selected_mask_valid);
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}
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}
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void Translator::MOV_B32(const Decoder::Instruction& inst, bool apply_float_modifiers) {
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if (apply_float_modifiers && (inst.src0.negate || inst.src0.absolute)) {
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WriteOperand(DestinationOperand(inst), ReadOperand(inst.src0, IR::Type::F32));
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} else {
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WriteOperand(DestinationOperand(inst), ReadOperand(inst.src0, IR::Type::U32));
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}
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}
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void Translator::S_MOV_B64(const Decoder::Instruction& inst) {
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if (IsExecOrVcc(inst.dst) || IsExecOrVcc(inst.src0)) {
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WriteMask(inst.dst, ReadMask(inst.src0), true);
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return;
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}
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const bool scalar_copy =
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inst.dst.kind == Decoder::OperandKind::Sgpr && inst.src0.kind == Decoder::OperandKind::Sgpr;
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IR::U1 source_mask;
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IR::U1 source_mask_valid;
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if (scalar_copy) {
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source_mask = ir.GetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.src0.reg));
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source_mask_valid = ir.GetScalarMaskTag(static_cast<IR::ScalarReg>(inst.src0.reg));
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}
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WriteU32Pair(inst.dst, ReadU32Pair(inst.src0));
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if (scalar_copy) {
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ir.SetThreadBitScalarReg(static_cast<IR::ScalarReg>(inst.dst.reg), source_mask);
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ir.SetScalarMaskTag(static_cast<IR::ScalarReg>(inst.dst.reg), source_mask_valid);
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}
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}
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void Translator::S_WQM_B64(const Decoder::Instruction& inst) {
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const auto source_mask = ReadMask(inst.src0);
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const auto mask_valid = ReadMaskValid(inst.src0);
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const auto result =
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IR::U64(ir.Emit(IR::ValueOpcode::WqmU64, {ReadOperand(inst.src0, IR::Type::U64)}));
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// WQM activates whole quads and cannot clear an already active lane.
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const auto widened_mask = ir.LogicalOr(source_mask, ThreadBit(ExtractU64(result)));
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WriteOperand(DestinationOperand(inst), result);
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if (inst.dst.kind == Decoder::OperandKind::ExecLo) {
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ir.SetExec(widened_mask);
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} else if (inst.dst.kind == Decoder::OperandKind::VccLo) {
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ir.SetVcc(widened_mask);
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} else if (inst.dst.kind == Decoder::OperandKind::Sgpr) {
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const auto dst = static_cast<IR::ScalarReg>(inst.dst.reg);
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ir.SetThreadBitScalarReg(dst, widened_mask);
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ir.SetScalarMaskTag(dst, mask_valid);
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}
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ir.SetScc(IR::U1(ir.Emit(IR::ValueOpcode::INotEqual64, {result, IR::Value(uint64_t {0})})));
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}
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void Translator::V_MOVRELS_B32(const Decoder::Instruction& inst) {
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if (inst.dst.kind != Decoder::OperandKind::Vgpr ||
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inst.src0.kind != Decoder::OperandKind::Vgpr) {
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EXIT("V_MOVRELS_B32 requires VGPR source and destination at pc 0x%08x", inst.pc);
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}
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if (inst.dst.sdwa_sel != 6u || inst.dst.omod != 0u || inst.dst.clamp ||
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inst.src0.sdwa_sel != 6u || inst.src0.sdwa_sext || inst.src0.negate || inst.src0.absolute ||
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inst.src0.dpp) {
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EXIT("V_MOVRELS_B32 modifiers are not implemented at pc 0x%08x", inst.pc);
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}
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const auto base = inst.src0.reg;
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const auto m0 = ir.BitwiseAnd(ReadU32(ConditionOperand(Decoder::OperandKind::M0)),
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IR::U32(IR::Value(0xffu)));
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auto selected = ir.GetVectorReg(static_cast<IR::VectorReg>(base));
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for (uint32_t index = base + 1u; index < current_vector_limit; index++) {
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const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
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selected = ir.Select(match, ir.GetVectorReg(static_cast<IR::VectorReg>(index)), selected);
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}
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WriteOperand(DestinationOperand(inst), selected);
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}
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void Translator::V_MOVRELD_B32(const Decoder::Instruction& inst) {
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if (inst.dst.kind != Decoder::OperandKind::Vgpr) {
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EXIT("V_MOVRELD_B32 requires VGPR destination at pc 0x%08x", inst.pc);
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}
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if (inst.dst.sdwa_sel != 6u || inst.dst.omod != 0u || inst.dst.clamp ||
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inst.src0.sdwa_sel != 6u || inst.src0.sdwa_sext || inst.src0.negate || inst.src0.absolute ||
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inst.src0.dpp) {
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EXIT("V_MOVRELD_B32 modifiers are not implemented at pc 0x%08x", inst.pc);
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}
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const auto base = inst.dst.reg;
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const auto value = ReadU32(inst.src0);
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const auto m0 = ir.BitwiseAnd(ReadU32(ConditionOperand(Decoder::OperandKind::M0)),
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IR::U32(IR::Value(0xffu)));
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for (uint32_t index = base; index < current_vector_limit; index++) {
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const auto reg = static_cast<IR::VectorReg>(index);
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const auto match = ir.IEqual(m0, IR::U32(IR::Value(index - base)));
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const auto write = ir.LogicalAnd(ir.GetExec(), match);
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ir.SetVectorReg(reg, ir.Select(write, value, ir.GetVectorReg(reg)));
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}
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}
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void Translator::V_READFIRSTLANE_B32(const Decoder::Instruction& inst) {
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const auto result = ir.Emit(IR::ValueOpcode::ReadFirstLane, {ReadU32(inst.src0), ir.GetExec()});
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WriteOperand(DestinationOperand(inst), result);
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}
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void Translator::V_READLANE_B32(const Decoder::Instruction& inst) {
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const auto lane_mask = IR::U32(IR::Value(current_wave_size == 32u ? 31u : 63u));
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const auto lane = ir.BitwiseAnd(ReadU32(inst.src1), lane_mask);
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WriteOperand(DestinationOperand(inst),
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ir.Emit(IR::ValueOpcode::ReadLane, {ReadU32(inst.src0), lane}));
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}
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void Translator::V_WRITELANE_B32(const Decoder::Instruction& inst) {
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EXIT_IF(inst.dst.kind != Decoder::OperandKind::Vgpr);
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const auto lane_mask = IR::U32(IR::Value(current_wave_size == 32u ? 31u : 63u));
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const auto reg = static_cast<IR::VectorReg>(inst.dst.reg);
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const auto lane = ir.BitwiseAnd(ReadU32(inst.src1), lane_mask);
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const auto result = IR::U32(
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ir.Emit(IR::ValueOpcode::WriteLane, {ir.GetVectorReg(reg), ReadU32(inst.src0), lane}));
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ir.SetVectorReg(reg, result);
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}
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void Translator::V_PERMLANE16_B32(const Decoder::Instruction& inst, bool x16) {
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const IR::PermlaneFlags flags {
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.x16 = x16,
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.fetch_inactive = inst.dst.op_sel,
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.bound_control = inst.dst.op_sel_hi,
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};
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const auto result =
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ir.Emit(IR::ValueOpcode::Permlane16U32,
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{ReadU32(inst.src0), ReadU32(inst.src1), ReadU32(inst.src2), ir.GetExec()}, flags);
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auto dst = DestinationOperand(inst);
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dst.op_sel = false;
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dst.op_sel_hi = false;
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WriteOperand(dst, result);
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Frontend
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