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https://github.com/KytyPS5/KytyPS5.git
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Nawid3333
ba8b0c85b8
V_PK_MIN_F16 and V_PK_MAX_F16 return the quieted NaN for a signaling NaN operand and the other operand for a quiet one (per half, as V_MIN_F16 and V_MAX_F16 do). The signaling test masked the half with 0x7c00 and checked for a nonzero payload, so a quiet NaN with payload bits such as 0x7e01 was taken as signaling and returned. Mask with 0x7e00 so the quiet bit must be clear. Two more vectors in PackedMinMaxF16NanAndSignedZeroEdges cover it. Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
238 lines
11 KiB
C++
238 lines
11 KiB
C++
#include "graphics/shader/recompiler/frontend/translate/Translator.h"
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#include <array>
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#include <utility>
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namespace Libs::Graphics::ShaderRecompiler::Frontend {
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void Translator::PackedFloat16(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool quiet_snan) {
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const auto translate_lane = [&](bool high) {
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const auto lhs = ReadF16LaneAsF32(inst.src0, high);
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const auto rhs = ReadF16LaneAsF32(inst.src1, high);
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IR::F32 result;
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if (accumulator) {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs, ReadF16LaneAsF32(inst.dst, high)}));
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} else if (inst.src_count == 3u) {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs, ReadF16LaneAsF32(inst.src2, high)}));
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} else {
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result = IR::F32(ir.Emit(opcode, {lhs, rhs}));
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}
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return ApplyF32ResultModifiers(inst.dst, result);
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};
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auto raw = DestinationOperand(inst);
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raw.omod = 0u;
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raw.clamp = false;
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auto result = PackHalf2x16(translate_lane(false), translate_lane(true));
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if (quiet_snan) {
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const auto quiet_snan_lane = [&](const Decoder::Operand& operand, bool high) {
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const auto bits = ReadU16LaneAsU32(operand, high, false);
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const auto exponent = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x7e00u)));
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const auto payload = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x01ffu)));
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const auto snan = ir.LogicalAnd(ir.IEqual(exponent, IR::U32(IR::Value(0x7c00u))),
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ir.INotEqual(payload, IR::U32(IR::Value(0u))));
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return std::pair {snan, ir.BitwiseOr(bits, IR::U32(IR::Value(0x0200u)))};
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};
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const auto override_lane = [&](bool high) {
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const auto [lhs_snan, lhs_quiet] = quiet_snan_lane(inst.src0, high);
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const auto [rhs_snan, rhs_quiet] = quiet_snan_lane(inst.src1, high);
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const auto normal = high ? ir.ShiftRightLogical(result, IR::U32(IR::Value(16u)))
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: ir.BitwiseAnd(result, IR::U32(IR::Value(0xffffu)));
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return ir.Select(lhs_snan, lhs_quiet, ir.Select(rhs_snan, rhs_quiet, normal));
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};
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result = PackU16Lanes(override_lane(false), override_lane(true));
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}
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WriteOperand(raw, result);
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}
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void Translator::Float16Unary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool invalid_negative) {
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const auto argument = ReadF16AsF32(inst.src0);
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auto result = IR::F32(ir.Emit(opcode, {argument}));
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if (!invalid_negative) {
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WriteF16(DestinationOperand(inst), result);
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return;
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}
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const auto negative =
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IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {argument, IR::Value::F32(0.0f)}));
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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Write16Bits(DestinationOperand(inst), ir.Select(negative, invalid, bits));
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}
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void Translator::Float16Trig(const Decoder::Instruction& inst, IR::ValueOpcode opcode) {
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const auto argument = ReadF16AsF32(inst.src0);
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const auto magnitude =
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ir.BitwiseAnd(ir.BitCastU32(argument), IR::U32(IR::Value(0x7fffffffu)));
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auto result = IR::F32(ir.Emit(opcode, {argument}));
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if (opcode == IR::ValueOpcode::FPSin) {
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const auto fraction = IR::F32(ir.Emit(IR::ValueOpcode::FPFract32, {argument}));
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const auto whole = IR::U1(
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ir.Emit(IR::ValueOpcode::FPOrdEqual32, {fraction, IR::Value::F32(0.0f)}));
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const auto half = IR::U1(
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ir.Emit(IR::ValueOpcode::FPOrdEqual32, {fraction, IR::Value::F32(0.5f)}));
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const auto nonzero = ir.INotEqual(magnitude, IR::U32(IR::Value(0u)));
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const auto cardinal = ir.LogicalOr(ir.LogicalAnd(whole, nonzero), half);
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result = IR::F32(ir.Emit(
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IR::ValueOpcode::SelectF32, {cardinal, IR::Value::F32(0.0f), result}));
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} else {
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// The architectural quarter-cycle result is exactly zero. Evaluating cos(pi/2) with a
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// rounded F32 PI can otherwise produce a half-precision subnormal instead.
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const auto fraction = IR::F32(ir.Emit(IR::ValueOpcode::FPFract32, {argument}));
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const auto quarter = IR::U1(
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ir.Emit(IR::ValueOpcode::FPOrdEqual32, {fraction, IR::Value::F32(0.25f)}));
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const auto three_quarters = IR::U1(
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ir.Emit(IR::ValueOpcode::FPOrdEqual32, {fraction, IR::Value::F32(0.75f)}));
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result = IR::F32(
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ir.Emit(IR::ValueOpcode::SelectF32,
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{ir.LogicalOr(quarter, three_quarters), IR::Value::F32(0.0f), result}));
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}
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const auto infinite = ir.IEqual(magnitude, IR::U32(IR::Value(0x7f800000u)));
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result = ApplyF32ResultModifiers(inst.dst, result);
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const auto bits = PackHalf2x16(result, IR::F32(IR::Value::F32(0.0f)));
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const auto invalid = IR::U32(IR::Value(inst.dst.clamp ? 0u : 0xfe00u));
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Write16Bits(DestinationOperand(inst), ir.Select(infinite, invalid, bits));
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}
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void Translator::Float16Binary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool reverse) {
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const auto lhs = ReadF16AsF32(reverse ? inst.src1 : inst.src0);
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const auto rhs = ReadF16AsF32(reverse ? inst.src0 : inst.src1);
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WriteF16(DestinationOperand(inst), IR::F32(ir.Emit(opcode, {lhs, rhs})));
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}
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void Translator::Float16Ternary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto& operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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args[index] = mix ? IR::Value(ReadMixF32(operand)) : IR::Value(ReadF16AsF32(operand));
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}
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WriteF16(DestinationOperand(inst), IR::F32(ir.Emit(opcode, {args[0], args[1], args[2]})));
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}
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void Translator::FloatUnary(const Decoder::Instruction& inst, IR::ValueOpcode opcode) {
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const auto type = IR::ArgTypeOf(opcode, 0);
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {ReadOperand(inst.src0, type)}));
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}
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void Translator::FloatBinary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool reverse) {
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std::array<IR::Value, 2> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto& operand = SourceAt(inst, reverse ? 1u - index : index);
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args[index] = ReadOperand(operand, IR::ArgTypeOf(opcode, index));
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {args[0], args[1]}));
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}
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void Translator::FloatTernary(const Decoder::Instruction& inst, IR::ValueOpcode opcode,
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bool accumulator, bool mix) {
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std::array<IR::Value, 3> args;
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for (uint32_t index = 0; index < args.size(); index++) {
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const auto& operand = accumulator && index == 2u ? inst.dst : SourceAt(inst, index);
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const auto type = IR::ArgTypeOf(opcode, index);
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args[index] = type == IR::Type::F32 && mix ? IR::Value(ReadMixF32(operand))
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: ReadOperand(operand, type);
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}
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WriteOperand(DestinationOperand(inst), ir.Emit(opcode, {args[0], args[1], args[2]}));
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}
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void Translator::V_FREXP_MANT_F32(const Decoder::Instruction& inst) {
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const auto bits = ReadU32(inst.src0);
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const auto exponent =
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IR::U32(ir.Emit(IR::ValueOpcode::BitFieldUExtract, {bits, IR::Value(23u), IR::Value(8u)}));
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const auto mantissa = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x007fffffu)));
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const auto sign = ir.BitwiseAnd(bits, IR::U32(IR::Value(0x80000000u)));
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const auto base = ir.BitwiseOr(sign, IR::U32(IR::Value(0x3f000000u)));
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const auto normal = ir.BitwiseOr(base, mantissa);
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const auto msb = IR::U32(ir.Emit(IR::ValueOpcode::FindUMsb32, {mantissa}));
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const auto shift = ir.ISub(IR::U32(IR::Value(23u)), msb);
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const auto fraction =
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ir.BitwiseAnd(ir.ShiftLeftLogical(mantissa, shift), IR::U32(IR::Value(0x007fffffu)));
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const auto subnormal = ir.BitwiseOr(base, fraction);
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const auto zero = ir.IEqual(mantissa, IR::U32(IR::Value(0u)));
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const auto finite = ir.Select(ir.INotEqual(exponent, IR::U32(IR::Value(0u))), normal,
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ir.Select(zero, bits, subnormal));
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const auto result = ir.Select(ir.IEqual(exponent, IR::U32(IR::Value(0xffu))), bits, finite);
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WriteOperand(DestinationOperand(inst), ir.BitCastF32(result));
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}
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void Translator::V_DOT2C_F32_F16(const Decoder::Instruction& inst) {
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auto a = inst.src0;
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a.op_sel = false;
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a.op_sel_hi = true;
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auto b = inst.src1;
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b.op_sel = false;
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b.op_sel_hi = true;
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const auto a_lo = ReadF16LaneAsF32(a, false);
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const auto a_hi = ReadF16LaneAsF32(a, true);
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const auto b_lo = ReadF16LaneAsF32(b, false);
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const auto b_hi = ReadF16LaneAsF32(b, true);
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const auto acc = ReadMixF32(inst.dst);
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const auto lo = IR::F32(ir.Emit(IR::ValueOpcode::FPFma32, {a_lo, b_lo, acc}));
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WriteOperand(DestinationOperand(inst), ir.Emit(IR::ValueOpcode::FPFma32, {a_hi, b_hi, lo}));
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}
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void Translator::V_CUBEID_F32(const Decoder::Instruction& inst) {
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return FloatCube(inst, 0u);
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}
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void Translator::V_CUBESC_F32(const Decoder::Instruction& inst) {
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return FloatCube(inst, 1u);
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}
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void Translator::V_CUBETC_F32(const Decoder::Instruction& inst) {
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return FloatCube(inst, 2u);
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}
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void Translator::V_CUBEMA_F32(const Decoder::Instruction& inst) {
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return FloatCube(inst, 3u);
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}
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void Translator::FloatCube(const Decoder::Instruction& inst, uint32_t result_kind) {
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const auto x = ReadMixF32(inst.src0);
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const auto y = ReadMixF32(inst.src1);
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const auto z = ReadMixF32(inst.src2);
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const auto nx = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {x}));
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const auto ny = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {y}));
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const auto nz = IR::F32(ir.Emit(IR::ValueOpcode::FPNeg32, {z}));
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const auto ax = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {x}));
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const auto ay = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {y}));
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const auto az = IR::F32(ir.Emit(IR::ValueOpcode::FPAbs32, {z}));
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const auto z_face =
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ir.LogicalAnd(IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {az, ax})),
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IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {az, ay})));
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const auto y_face = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdGreaterThanEqual32, {ay, ax}));
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const auto x_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {x, IR::Value::F32(0.0f)}));
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const auto y_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {y, IR::Value::F32(0.0f)}));
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const auto z_neg = IR::U1(ir.Emit(IR::ValueOpcode::FPOrdLessThan32, {z, IR::Value::F32(0.0f)}));
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const auto select_face = [&](IR::F32 x_value, IR::F32 y_value, IR::F32 z_value) {
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return SelectF32(z_face, z_value, SelectF32(y_face, y_value, x_value));
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};
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IR::F32 result;
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switch (result_kind) {
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case 0u:
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result = select_face(
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SelectF32(x_neg, IR::F32(IR::Value::F32(1.0f)), IR::F32(IR::Value::F32(0.0f))),
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SelectF32(y_neg, IR::F32(IR::Value::F32(3.0f)), IR::F32(IR::Value::F32(2.0f))),
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SelectF32(z_neg, IR::F32(IR::Value::F32(5.0f)), IR::F32(IR::Value::F32(4.0f))));
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break;
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case 1u: result = select_face(SelectF32(x_neg, z, nz), x, SelectF32(z_neg, nx, x)); break;
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case 2u: result = select_face(ny, SelectF32(y_neg, nz, z), ny); break;
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case 3u: {
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const auto two = IR::F32(IR::Value::F32(2.0f));
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result = select_face(IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {x, two})),
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IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {y, two})),
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IR::F32(ir.Emit(IR::ValueOpcode::FPMul32, {z, two})));
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break;
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}
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default: EXIT("invalid cube result kind");
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}
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WriteOperand(DestinationOperand(inst), result);
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}
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} // namespace Libs::Graphics::ShaderRecompiler::Frontend
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