mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-20 19:07:01 +02:00
nmzik
665 lines
29 KiB
C++
665 lines
29 KiB
C++
#include "graphics/shader/recompiler/backend/spirv/spirvEmitterInternal.h"
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#include <algorithm>
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namespace Libs::Graphics::ShaderRecompiler::Spirv::Emitter {
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namespace {
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bool UserDataDwordIndex(const EmitterState& state, IR::Register reg, uint32_t& dword_index) {
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if (reg.file != IR::RegisterFile::Scalar) {
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return false;
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}
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const auto& registers = state.program.bindings.user_data_registers;
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const auto found = std::lower_bound(registers.begin(), registers.end(), reg.index);
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if (found == registers.end() || *found != reg.index) {
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return false;
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}
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dword_index = static_cast<uint32_t>(found - registers.begin());
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return true;
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}
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uint32_t EmitWqmWordU32(EmitterState& state, uint32_t value) {
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const auto shifted_one = state.builder.AllocateId();
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const auto merged_one = state.builder.AllocateId();
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const auto shifted_two = state.builder.AllocateId();
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const auto merged_two = state.builder.AllocateId();
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const auto quad_bits = state.builder.AllocateId();
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpShiftRightLogical, TypeU32(state), shifted_one, value, ConstantU32(state, 1)});
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state.builder.AddFunction({OpBitwiseOr, TypeU32(state), merged_one, value, shifted_one});
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state.builder.AddFunction(
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{OpShiftRightLogical, TypeU32(state), shifted_two, merged_one, ConstantU32(state, 2)});
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state.builder.AddFunction({OpBitwiseOr, TypeU32(state), merged_two, merged_one, shifted_two});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), quad_bits, merged_two, ConstantU32(state, 0x11111111u)});
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state.builder.AddFunction(
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{OpIMul, TypeU32(state), result, quad_bits, ConstantU32(state, 0x0fu)});
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return result;
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}
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uint32_t EmitWqmU64(EmitterState& state, uint32_t value) {
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const auto shifted_one = state.builder.AllocateId();
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const auto merged_one = state.builder.AllocateId();
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const auto shifted_two = state.builder.AllocateId();
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const auto merged_two = state.builder.AllocateId();
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const auto quad_bits = state.builder.AllocateId();
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction({OpShiftRightLogical, TypeU64(state), shifted_one, value,
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ConstantU64(state, 0x0000000100000001ull)});
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state.builder.AddFunction({OpBitwiseOr, TypeU64(state), merged_one, value, shifted_one});
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state.builder.AddFunction({OpShiftRightLogical, TypeU64(state), shifted_two, merged_one,
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ConstantU64(state, 0x0000000200000002ull)});
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state.builder.AddFunction({OpBitwiseOr, TypeU64(state), merged_two, merged_one, shifted_two});
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state.builder.AddFunction({OpBitwiseAnd, TypeU64(state), quad_bits, merged_two,
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ConstantU64(state, 0x1111111111111111ull)});
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state.builder.AddFunction(
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{OpIMul, TypeU64(state), result, quad_bits, ConstantU64(state, 0x0000000f0000000full)});
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return result;
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}
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uint32_t EmitBuiltinU32(ValueEmitContext& ctx, IR::StageInputKind kind, uint32_t component) {
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auto& state = ctx.state;
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if (kind == IR::StageInputKind::LocalInvocationIndex) {
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return EmitLocalInvocationIndex(state);
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}
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const auto variable = InputVariableForKind(state, kind);
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if (variable == 0) {
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return ConstantU32(state, 0);
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}
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if (kind == IR::StageInputKind::FrontFacing) {
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const auto value = state.builder.AllocateId();
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpLoad, TypeBool(state), value, variable});
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state.builder.AddFunction(
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{OpSelect, TypeU32(state), bits, value, ConstantU32(state, 1), ConstantU32(state, 0)});
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return bits;
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}
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if (kind == IR::StageInputKind::VertexIndex || kind == IR::StageInputKind::InstanceIndex) {
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const auto value = state.builder.AllocateId();
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpLoad, TypeI32(state), value, variable});
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, value});
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return bits;
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}
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if (kind == IR::StageInputKind::FragCoord) {
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const auto pointer = state.builder.AllocateId();
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const auto value = state.builder.AllocateId();
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpAccessChain,
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TypePointer(state, StorageClassInput, TypeF32(state)), pointer,
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variable, ConstantU32(state, component)});
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state.builder.AddFunction({OpLoad, TypeF32(state), value, pointer});
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, value});
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return bits;
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}
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if (kind == IR::StageInputKind::BaryCoordSmooth ||
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kind == IR::StageInputKind::BaryCoordNoPerspective) {
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const auto pointer = state.builder.AllocateId();
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const auto value = state.builder.AllocateId();
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpAccessChain,
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TypePointer(state, StorageClassInput, TypeF32(state)), pointer,
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variable, ConstantU32(state, component + 1u)});
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state.builder.AddFunction({OpLoad, TypeF32(state), value, pointer});
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, value});
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return bits;
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}
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return EmitInputComponentU32(state, kind, component);
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}
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uint32_t EmitWqm(ValueEmitContext& ctx, uint32_t active) {
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auto& state = ctx.state;
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const auto ballot = state.builder.AllocateId();
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state.builder.AddFunction({OpGroupNonUniformBallot, TypeU32Vector(state, 4), ballot,
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ConstantU32(state, ScopeSubgroup), active});
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const auto low = state.builder.AllocateId();
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state.builder.AddFunction({OpCompositeExtract, TypeU32(state), low, ballot, 0});
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const auto wqm_low = EmitWqmWordU32(state, low);
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const auto lane = EmitSubgroupLocalInvocationId(state);
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uint32_t mask = wqm_low;
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uint32_t bit_lane = lane;
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if (state.wave_size == 64u) {
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const auto high = state.builder.AllocateId();
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state.builder.AddFunction({OpCompositeExtract, TypeU32(state), high, ballot, 1});
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const auto wqm_high = EmitWqmWordU32(state, high);
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const auto upper = state.builder.AllocateId();
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mask = state.builder.AllocateId();
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bit_lane = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpUGreaterThanEqual, TypeBool(state), upper, lane, ConstantU32(state, 32)});
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state.builder.AddFunction({OpSelect, TypeU32(state), mask, upper, wqm_high, wqm_low});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), bit_lane, lane, ConstantU32(state, 31)});
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}
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const auto bit = state.builder.AllocateId();
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const auto hit = state.builder.AllocateId();
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpShiftLeftLogical, TypeU32(state), bit, ConstantU32(state, 1), bit_lane});
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state.builder.AddFunction({OpBitwiseAnd, TypeU32(state), hit, mask, bit});
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state.builder.AddFunction({OpINotEqual, TypeBool(state), result, hit, ConstantU32(state, 0)});
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return result;
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}
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uint32_t EmitDppWriteCondition(ValueEmitContext& ctx, const IR::DppMoveFlags& flags,
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uint32_t exec) {
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auto& state = ctx.state;
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const auto lane = EmitSubgroupLocalInvocationId(state);
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const auto bank_shift = state.builder.AllocateId();
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const auto row_shift = state.builder.AllocateId();
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const auto bank = state.builder.AllocateId();
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const auto row = state.builder.AllocateId();
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const auto bank_bit = state.builder.AllocateId();
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const auto row_bit = state.builder.AllocateId();
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const auto bank_hit = state.builder.AllocateId();
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const auto row_hit = state.builder.AllocateId();
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const auto bank_ok = state.builder.AllocateId();
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const auto row_ok = state.builder.AllocateId();
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const auto masks_ok = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpShiftRightLogical, TypeU32(state), bank_shift, lane, ConstantU32(state, 2)});
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state.builder.AddFunction(
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{OpShiftRightLogical, TypeU32(state), row_shift, lane, ConstantU32(state, 4)});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), bank, bank_shift, ConstantU32(state, 3)});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), row, row_shift, ConstantU32(state, 3)});
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state.builder.AddFunction(
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{OpShiftLeftLogical, TypeU32(state), bank_bit, ConstantU32(state, 1), bank});
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state.builder.AddFunction(
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{OpShiftLeftLogical, TypeU32(state), row_bit, ConstantU32(state, 1), row});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), bank_hit, ConstantU32(state, flags.bank_mask), bank_bit});
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state.builder.AddFunction(
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{OpBitwiseAnd, TypeU32(state), row_hit, ConstantU32(state, flags.row_mask), row_bit});
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state.builder.AddFunction(
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{OpINotEqual, TypeBool(state), bank_ok, bank_hit, ConstantU32(state, 0)});
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state.builder.AddFunction(
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{OpINotEqual, TypeBool(state), row_ok, row_hit, ConstantU32(state, 0)});
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state.builder.AddFunction({OpLogicalAnd, TypeBool(state), masks_ok, bank_ok, row_ok});
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uint32_t writable = masks_ok;
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if (!flags.bound_control) {
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const auto target = EmitDppTargetLane(state, flags.control);
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const auto bounded = state.builder.AllocateId();
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state.builder.AddFunction({OpLogicalAnd, TypeBool(state), bounded, writable, target.valid});
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writable = bounded;
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}
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const auto result = state.builder.AllocateId();
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state.builder.AddFunction({OpLogicalAnd, TypeBool(state), result, exec, writable});
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return result;
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}
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uint32_t EmitAttribute(ValueEmitContext& ctx, uint32_t attr, uint32_t chan) {
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auto& state = ctx.state;
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const auto* input = InputBindingForParameter(state, attr);
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if (input == nullptr || input->variable_id == 0) {
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return ConstantU32(state, 0);
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}
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if (state.stage == ShaderType::Vertex) {
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return EmitVertexParameterComponentU32(state, *input, chan & 3u);
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}
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const auto load_per_vertex = [&](uint32_t vertex) {
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const auto pointer = state.builder.AllocateId();
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const auto value = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpAccessChain, TypePointer(state, StorageClassInput, TypeF32(state)), pointer,
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input->variable_id, ConstantU32(state, vertex), ConstantU32(state, chan & 3u)});
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state.builder.AddFunction({OpLoad, TypeF32(state), value, pointer});
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return value;
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};
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if (input->per_vertex) {
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const auto barycentric_kind = state.input_info.pixel->ps_no_perspective
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? IR::StageInputKind::BaryCoordNoPerspective
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: IR::StageInputKind::BaryCoordSmooth;
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const auto barycentric = InputVariableForKind(state, barycentric_kind);
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uint32_t sum = 0;
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for (uint32_t vertex = 0; vertex < 3u; vertex++) {
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const auto pointer = state.builder.AllocateId();
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const auto weight = state.builder.AllocateId();
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const auto product = state.builder.AllocateId();
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state.builder.AddFunction({OpAccessChain,
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TypePointer(state, StorageClassInput, TypeF32(state)),
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pointer, barycentric, ConstantU32(state, vertex)});
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state.builder.AddFunction({OpLoad, TypeF32(state), weight, pointer});
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state.builder.AddFunction(
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{OpFMul, TypeF32(state), product, load_per_vertex(vertex), weight});
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if (vertex == 0u) {
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sum = product;
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} else {
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const auto next = state.builder.AllocateId();
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state.builder.AddFunction({OpFAdd, TypeF32(state), next, sum, product});
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sum = next;
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}
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}
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, sum});
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return bits;
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}
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const auto vector = state.builder.AllocateId();
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const auto component = state.builder.AllocateId();
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpLoad, TypeF32Vector(state, 4), vector, input->variable_id});
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state.builder.AddFunction({OpCompositeExtract, TypeF32(state), component, vector, chan & 3u});
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, component});
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return bits;
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}
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uint32_t EmitInterpolationParameter(ValueEmitContext& ctx, uint32_t attr, uint32_t chan,
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uint32_t mode) {
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auto& state = ctx.state;
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const auto* input = InputBindingForParameter(state, attr);
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if (!input->per_vertex) {
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return EmitAttribute(ctx, attr, chan);
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}
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const auto load_vertex = [&](uint32_t vertex) {
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const auto pointer = state.builder.AllocateId();
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const auto value = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpAccessChain, TypePointer(state, StorageClassInput, TypeF32(state)), pointer,
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input->variable_id, ConstantU32(state, vertex), ConstantU32(state, chan & 3u)});
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state.builder.AddFunction({OpLoad, TypeF32(state), value, pointer});
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return value;
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};
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const auto selected_vertex = (mode + 1u) % 3u;
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uint32_t value = load_vertex(selected_vertex);
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if (!PixelParameterIsCustom(state, attr) && mode < 2u) {
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const auto delta = state.builder.AllocateId();
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state.builder.AddFunction({OpFSub, TypeF32(state), delta, value, load_vertex(0)});
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value = delta;
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}
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const auto bits = state.builder.AllocateId();
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state.builder.AddFunction({OpBitcast, TypeU32(state), bits, value});
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return bits;
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}
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uint32_t MrtOutputMode(const EmitterState& state, const IR::ExportInfo& exp) {
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if (state.stage != ShaderType::Pixel || exp.kind != IR::ExportTargetKind::Mrt ||
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exp.index >= std::size(state.input_info.pixel->target_output_mode)) {
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return 0;
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}
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return state.input_info.pixel->target_output_mode[exp.index];
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}
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uint32_t ExportRawComponent(ValueEmitContext& ctx, uint32_t vector, uint32_t component) {
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const auto value = ctx.state.builder.AllocateId();
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ctx.state.builder.AddFunction(
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{OpCompositeExtract, TypeU32(ctx.state), value, vector, component});
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return value;
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}
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uint32_t ExportVector(ValueEmitContext& ctx, uint32_t data, const IR::ExportInfo& exp,
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bool uint_output) {
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auto& state = ctx.state;
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if (exp.compr && !uint_output) {
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const auto unpack =
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MrtOutputMode(state, exp) == 5u ? GlslUnpackUnorm2x16 : GlslUnpackHalf2x16;
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uint32_t f32[4] = {ConstantF32(state, 0), ConstantF32(state, 0), ConstantF32(state, 0),
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ConstantF32(state, 0x3f800000u)};
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for (uint32_t pair = 0; pair < 2u; pair++) {
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if ((exp.en & (3u << (pair * 2u))) == 0u) {
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continue;
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}
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const auto packed = state.builder.AllocateId();
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const auto unpacked = state.builder.AllocateId();
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state.builder.AddFunction({OpCompositeExtract, TypeU32(state), packed, data, pair});
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state.builder.AddFunction(
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{OpExtInst, TypeF32Vector(state, 2), unpacked, GlslStd450(state), unpack, packed});
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for (uint32_t lane = 0; lane < 2u; lane++) {
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const auto component = pair * 2u + lane;
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if (((exp.en >> component) & 1u) != 0u) {
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f32[component] = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpCompositeExtract, TypeF32(state), f32[component], unpacked, lane});
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}
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}
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}
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const auto vector = state.builder.AllocateId();
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state.builder.AddFunction({OpCompositeConstruct, TypeF32Vector(state, 4), vector, f32[0],
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f32[1], f32[2], f32[3]});
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return vector;
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}
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uint32_t raw[4] = {
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ConstantU32(state, 0),
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ConstantU32(state, 0),
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ConstantU32(state, 0),
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ConstantU32(state, uint_output ? 1u : 0x3f800000u),
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};
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if (exp.compr) {
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for (uint32_t pair = 0; pair < 2u; pair++) {
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if ((exp.en & (3u << (pair * 2u))) == 0u) {
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continue;
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}
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const auto packed = ExportRawComponent(ctx, data, pair);
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for (uint32_t lane = 0; lane < 2u; lane++) {
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const auto component = pair * 2u + lane;
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if (((exp.en >> component) & 1u) == 0u) {
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continue;
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}
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raw[component] = state.builder.AllocateId();
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state.builder.AddFunction({OpBitFieldUExtract, TypeU32(state), raw[component],
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packed, ConstantU32(state, lane * 16u),
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ConstantU32(state, 16)});
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}
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}
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} else {
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for (uint32_t component = 0; component < 4u; component++) {
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if (((exp.en >> component) & 1u) != 0u) {
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raw[component] = ExportRawComponent(ctx, data, component);
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}
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}
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}
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if (uint_output) {
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const auto vector = state.builder.AllocateId();
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state.builder.AddFunction({OpCompositeConstruct, TypeU32Vector(state, 4), vector, raw[0],
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raw[1], raw[2], raw[3]});
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return vector;
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}
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uint32_t f32[4] {};
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for (uint32_t component = 0; component < 4u; component++) {
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f32[component] = state.builder.AllocateId();
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state.builder.AddFunction({OpBitcast, TypeF32(state), f32[component], raw[component]});
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}
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const auto vector = state.builder.AllocateId();
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state.builder.AddFunction(
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{OpCompositeConstruct, TypeF32Vector(state, 4), vector, f32[0], f32[1], f32[2], f32[3]});
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return vector;
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}
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void EmitAuxPositionExport(ValueEmitContext& ctx, uint32_t data, const IR::ExportInfo& exp) {
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auto& state = ctx.state;
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for (uint32_t component = 0; component < 4; component++) {
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if ((exp.en & (1u << component)) == 0) {
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continue;
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}
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const auto output = IR::DecodePositionExportComponent(
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state.input_info.vertex->pa_cl_vs_out_cntl, exp.index, component);
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if (output.layer) {
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const auto raw = ExportRawComponent(ctx, data, component);
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const auto layer = state.builder.AllocateId();
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state.builder.AddFunction({OpBitwiseAnd, TypeU32(state), layer, raw,
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ConstantU32(state, 0x7ffu)});
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state.builder.AddFunction({OpStore, state.layer_variable, layer});
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continue;
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}
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if (!output.point_size && output.clip_distance == UINT32_MAX &&
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output.cull_distance == UINT32_MAX) {
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continue;
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}
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const auto raw = ExportRawComponent(ctx, data, component);
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const auto f32 = state.builder.AllocateId();
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state.builder.AddFunction({OpBitcast, TypeF32(state), f32, raw});
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if (output.point_size) {
|
|
state.builder.AddFunction({OpStore, state.point_size_variable, f32});
|
|
continue;
|
|
}
|
|
auto StoreDistance = [&](uint32_t variable, uint32_t index) {
|
|
if (index == UINT32_MAX) {
|
|
return;
|
|
}
|
|
const auto pointer = state.builder.AllocateId();
|
|
state.builder.AddFunction(
|
|
{OpAccessChain, TypePointer(state, StorageClassOutput, TypeF32(state)), pointer,
|
|
variable, ConstantU32(state, index)});
|
|
state.builder.AddFunction({OpStore, pointer, f32});
|
|
};
|
|
StoreDistance(state.clip_distance_variable, output.clip_distance);
|
|
StoreDistance(state.cull_distance_variable, output.cull_distance);
|
|
}
|
|
}
|
|
|
|
void EmitExport(ValueEmitContext& ctx, const IR::Inst& inst) {
|
|
auto& state = ctx.state;
|
|
const auto& exp = ctx.Export(inst);
|
|
const auto exec = ctx.Arg(inst, 1);
|
|
if (state.stage == ShaderType::Pixel && exp.vm && state.requirements.pixel_valid_mask &&
|
|
state.pixel_valid_mask_variable != 0) {
|
|
const auto value = state.builder.AllocateId();
|
|
state.builder.AddFunction(
|
|
{OpSelect, TypeU32(state), value, exec, ConstantU32(state, 1), ConstantU32(state, 0)});
|
|
state.builder.AddFunction({OpStore, state.pixel_valid_mask_variable, value});
|
|
}
|
|
if (exp.kind == IR::ExportTargetKind::Null || exp.kind == IR::ExportTargetKind::Primitive ||
|
|
exp.en == 0u) {
|
|
return;
|
|
}
|
|
EmitIfCondition(state, exec, [&]() {
|
|
const auto data = ctx.Arg(inst, 0);
|
|
if (exp.kind == IR::ExportTargetKind::Position && exp.index != 0) {
|
|
EmitAuxPositionExport(ctx, data, exp);
|
|
return;
|
|
}
|
|
if (exp.kind == IR::ExportTargetKind::MrtZ) {
|
|
if ((exp.en & 1u) != 0u && state.depth_variable != 0) {
|
|
const auto raw = ExportRawComponent(ctx, data, 0);
|
|
const auto f32 = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpBitcast, TypeF32(state), f32, raw});
|
|
state.builder.AddFunction({OpStore, state.depth_variable, f32});
|
|
}
|
|
if ((exp.en & 4u) != 0u && state.sample_mask_variable != 0) {
|
|
const auto raw = ExportRawComponent(ctx, data, 2);
|
|
const auto value = state.builder.AllocateId();
|
|
const auto pointer = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpBitcast, TypeI32(state), value, raw});
|
|
state.builder.AddFunction(
|
|
{OpAccessChain, TypePointer(state, StorageClassOutput, TypeI32(state)), pointer,
|
|
state.sample_mask_variable, ConstantU32(state, 0)});
|
|
state.builder.AddFunction({OpStore, pointer, value});
|
|
}
|
|
return;
|
|
}
|
|
const auto variable = OutputVariableForExport(state, exp);
|
|
if (variable == 0) {
|
|
return;
|
|
}
|
|
const bool uint_output = MrtOutputMode(state, exp) == 7u;
|
|
const auto vector_type = uint_output ? TypeU32Vector(state, 4) : TypeF32Vector(state, 4);
|
|
auto value = ExportVector(ctx, data, exp, uint_output);
|
|
if (state.stage == ShaderType::Pixel && exp.kind == IR::ExportTargetKind::Mrt &&
|
|
exp.index < state.input_info.pixel->target_export_mapping.size()) {
|
|
const auto mapping = state.input_info.pixel->target_export_mapping[exp.index];
|
|
if (!mapping.IsIdentity()) {
|
|
const auto mapped = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpVectorShuffle, vector_type, mapped, value, value,
|
|
mapping.Map(0), mapping.Map(1), mapping.Map(2),
|
|
mapping.Map(3)});
|
|
value = mapped;
|
|
}
|
|
}
|
|
if (exp.kind == IR::ExportTargetKind::Position) {
|
|
const auto pointer = state.builder.AllocateId();
|
|
state.builder.AddFunction(
|
|
{OpAccessChain, TypePointer(state, StorageClassOutput, TypeF32Vector(state, 4)),
|
|
pointer, variable, ConstantU32(state, 0)});
|
|
state.builder.AddFunction({OpStore, pointer, value});
|
|
} else {
|
|
state.builder.AddFunction({OpStore, variable, value});
|
|
}
|
|
});
|
|
}
|
|
|
|
} // namespace
|
|
|
|
bool EmitValueFlow(ValueEmitContext& ctx, const IR::Inst& inst) {
|
|
auto& state = ctx.state;
|
|
switch (inst.GetOpcode()) {
|
|
case IR::ValueOpcode::Identity: ctx.Define(inst, ctx.Arg(inst, 0)); return true;
|
|
case IR::ValueOpcode::Void:
|
|
case IR::ValueOpcode::Reference:
|
|
case IR::ValueOpcode::ReferenceU32:
|
|
case IR::ValueOpcode::ControlNop:
|
|
case IR::ValueOpcode::Waitcnt:
|
|
case IR::ValueOpcode::Sendmsg:
|
|
case IR::ValueOpcode::TtraceData:
|
|
case IR::ValueOpcode::InstPrefetch: return true;
|
|
case IR::ValueOpcode::Barrier: {
|
|
const auto semantics = MemorySemanticsAcquireRelease | MemorySemanticsWorkgroupMemory;
|
|
state.builder.AddFunction({OpControlBarrier, ConstantU32(state, ScopeWorkgroup),
|
|
ConstantU32(state, ScopeWorkgroup),
|
|
ConstantU32(state, semantics)});
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::GetUserData: {
|
|
const auto reg = inst.Arg(0).ScalarRegister();
|
|
uint32_t dword = 0;
|
|
if (!UserDataDwordIndex(state, {IR::RegisterFile::Scalar, IR::RegIndex(reg)}, dword)) {
|
|
ctx.Define(inst, ConstantU32(state, 0));
|
|
} else {
|
|
ctx.Define(inst, EmitShaderDataDwordLoad(state, dword));
|
|
}
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::GetBuiltin:
|
|
ctx.Define(inst, EmitBuiltinU32(ctx, static_cast<IR::StageInputKind>(inst.Arg(0).U32()),
|
|
inst.Arg(1).U32()));
|
|
return true;
|
|
case IR::ValueOpcode::UndefU1:
|
|
case IR::ValueOpcode::UndefU8:
|
|
case IR::ValueOpcode::UndefU16:
|
|
case IR::ValueOpcode::UndefU32:
|
|
case IR::ValueOpcode::UndefU64:
|
|
state.builder.AddFunction({OpUndef, ctx.TypeId(inst.GetType()), ctx.Result(inst)});
|
|
return true;
|
|
case IR::ValueOpcode::DppMoveU32: {
|
|
const auto flags = inst.Flags<IR::DppMoveFlags>();
|
|
const auto target = EmitDppTargetLane(state, flags.control);
|
|
const auto shuffled = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpGroupNonUniformShuffle, TypeU32(state), shuffled,
|
|
ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 0),
|
|
target.lane});
|
|
if (flags.fetch_inactive) {
|
|
ctx.Define(inst, shuffled);
|
|
return true;
|
|
}
|
|
const auto ballot = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpGroupNonUniformBallot, TypeU32Vector(state, 4), ballot,
|
|
ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 1)});
|
|
const auto source_active = EmitBallotLaneActiveBool(state, ballot, target.lane);
|
|
const auto can_fetch = state.builder.AllocateId();
|
|
state.builder.AddFunction(
|
|
{OpLogicalAnd, TypeBool(state), can_fetch, target.valid, source_active});
|
|
ctx.Emit(inst, OpSelect, IR::Type::U32, {can_fetch, shuffled, ConstantU32(state, 0)});
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::DppUpdateU32: {
|
|
const auto flags = inst.Flags<IR::DppMoveFlags>();
|
|
const auto write = EmitDppWriteCondition(ctx, flags, ctx.Arg(inst, 2));
|
|
ctx.Emit(inst, OpSelect, IR::Type::U32, {write, ctx.Arg(inst, 0), ctx.Arg(inst, 1)});
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::WqmU64:
|
|
ctx.Define(inst, EmitWqmU64(ctx.state, ctx.Arg(inst, 0)));
|
|
return true;
|
|
case IR::ValueOpcode::WqmMask:
|
|
ctx.Define(inst, EmitWqm(ctx, ctx.Arg(inst, 0)));
|
|
return true;
|
|
case IR::ValueOpcode::LaneId:
|
|
ctx.Define(inst, EmitSubgroupLocalInvocationId(state));
|
|
return true;
|
|
case IR::ValueOpcode::Ballot:
|
|
ctx.Emit(inst, OpGroupNonUniformBallot, IR::Type::U32x4,
|
|
{ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 0)});
|
|
return true;
|
|
case IR::ValueOpcode::ReadFirstLane: {
|
|
const auto ballot = state.builder.AllocateId();
|
|
const auto lane = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpGroupNonUniformBallot, TypeU32Vector(state, 4), ballot,
|
|
ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 1)});
|
|
state.builder.AddFunction({OpGroupNonUniformBallotFindLSB, TypeU32(state), lane,
|
|
ConstantU32(state, ScopeSubgroup), ballot});
|
|
ctx.Emit(inst, OpGroupNonUniformShuffle, IR::Type::U32,
|
|
{ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 0), lane});
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::ReadLane:
|
|
ctx.Emit(inst, OpGroupNonUniformShuffle, IR::Type::U32,
|
|
{ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 0), ctx.Arg(inst, 1)});
|
|
return true;
|
|
case IR::ValueOpcode::WriteLane: {
|
|
const auto hit = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpIEqual, TypeBool(state), hit,
|
|
EmitSubgroupLocalInvocationId(state), ctx.Arg(inst, 2)});
|
|
ctx.Emit(inst, OpSelect, IR::Type::U32, {hit, ctx.Arg(inst, 1), ctx.Arg(inst, 0)});
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::Permlane16U32: {
|
|
const auto flags = inst.Flags<IR::PermlaneFlags>();
|
|
const auto subid = EmitSubgroupLocalInvocationId(state);
|
|
const auto row = state.builder.AllocateId();
|
|
const auto row_value = state.builder.AllocateId();
|
|
const auto lane = state.builder.AllocateId();
|
|
const auto lane8 = state.builder.AllocateId();
|
|
const auto shift = state.builder.AllocateId();
|
|
const auto upper = state.builder.AllocateId();
|
|
const auto selected = state.builder.AllocateId();
|
|
const auto shifted = state.builder.AllocateId();
|
|
const auto index = state.builder.AllocateId();
|
|
const auto target = state.builder.AllocateId();
|
|
state.builder.AddFunction(
|
|
{OpBitwiseAnd, TypeU32(state), row, subid, ConstantU32(state, 0xfffffff0u)});
|
|
if (flags.x16) {
|
|
state.builder.AddFunction(
|
|
{OpBitwiseXor, TypeU32(state), row_value, row, ConstantU32(state, 16)});
|
|
} else {
|
|
state.builder.AddFunction({OpCopyObject, TypeU32(state), row_value, row});
|
|
}
|
|
state.builder.AddFunction(
|
|
{OpBitwiseAnd, TypeU32(state), lane, subid, ConstantU32(state, 15)});
|
|
state.builder.AddFunction(
|
|
{OpBitwiseAnd, TypeU32(state), lane8, lane, ConstantU32(state, 7)});
|
|
state.builder.AddFunction(
|
|
{OpShiftLeftLogical, TypeU32(state), shift, lane8, ConstantU32(state, 2)});
|
|
state.builder.AddFunction(
|
|
{OpUGreaterThanEqual, TypeBool(state), upper, lane, ConstantU32(state, 8)});
|
|
state.builder.AddFunction(
|
|
{OpSelect, TypeU32(state), selected, upper, ctx.Arg(inst, 2), ctx.Arg(inst, 1)});
|
|
state.builder.AddFunction(
|
|
{OpShiftRightLogical, TypeU32(state), shifted, selected, shift});
|
|
state.builder.AddFunction(
|
|
{OpBitwiseAnd, TypeU32(state), index, shifted, ConstantU32(state, 15)});
|
|
state.builder.AddFunction({OpBitwiseOr, TypeU32(state), target, row_value, index});
|
|
const auto shuffled = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpGroupNonUniformShuffle, TypeU32(state), shuffled,
|
|
ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 0),
|
|
target});
|
|
uint32_t result = shuffled;
|
|
if (!flags.fetch_inactive) {
|
|
const auto source_exec = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpGroupNonUniformShuffle, TypeBool(state), source_exec,
|
|
ConstantU32(state, ScopeSubgroup), ctx.Arg(inst, 3),
|
|
target});
|
|
result = state.builder.AllocateId();
|
|
state.builder.AddFunction({OpSelect, TypeU32(state), result, source_exec, shuffled,
|
|
ConstantU32(state, 0)});
|
|
}
|
|
ctx.Define(inst, result);
|
|
return true;
|
|
}
|
|
case IR::ValueOpcode::GetAttribute:
|
|
ctx.Define(inst, EmitAttribute(ctx, inst.Arg(0).U32(), inst.Arg(1).U32()));
|
|
return true;
|
|
case IR::ValueOpcode::GetInterpolationParameter:
|
|
ctx.Define(inst, EmitInterpolationParameter(ctx, inst.Arg(0).U32(), inst.Arg(1).U32(),
|
|
inst.Arg(2).U32()));
|
|
return true;
|
|
case IR::ValueOpcode::SetAttribute: EmitExport(ctx, inst); return true;
|
|
case IR::ValueOpcode::GetShaderBase:
|
|
// Guest S_GETPC values stay shader-relative in SPIR-V, matching the runtime ABI. The
|
|
// runtime descriptor evaluator supplies the mapped shader base for host-side planning.
|
|
ctx.Define(inst, ctx.Def(IR::Value(uint64_t {0})));
|
|
return true;
|
|
case IR::ValueOpcode::GetSrtResource:
|
|
case IR::ValueOpcode::GetBufferResource:
|
|
case IR::ValueOpcode::GetAddressResource:
|
|
case IR::ValueOpcode::GetScratchResource:
|
|
case IR::ValueOpcode::GetImageResource:
|
|
case IR::ValueOpcode::GetSamplerResource:
|
|
case IR::ValueOpcode::MakeImageAddress: return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
} // namespace Libs::Graphics::ShaderRecompiler::Spirv::Emitter
|