mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-21 03:16:54 +02:00
shader: use ISA-style decoder opcode names
This commit is contained in:
nmzik
@@ -14,7 +14,7 @@ void DecodeExp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
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inst.word_count = 2;
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inst.family = Family::EXP;
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inst.opcode_id = target;
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inst.opcode = Opcode::Exp;
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inst.opcode = Opcode::EXP;
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inst.exp.target = target;
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inst.exp.en = en;
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inst.exp.compr = ((word0 >> 10u) & 1u) != 0;
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@@ -17,7 +17,7 @@ struct MimgSampleInfo {
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struct MimgGatherInfo {
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uint32_t encoding = 0;
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const char* name = nullptr;
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Opcode decoded = Opcode::Unsupported;
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Opcode decoded = Opcode::UNSUPPORTED;
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uint32_t flags = 0;
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uint32_t address_components = 3;
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};
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@@ -25,7 +25,7 @@ struct MimgGatherInfo {
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struct MimgAtomicInfo {
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uint32_t encoding = 0;
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const char* name = nullptr;
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Opcode decoded = Opcode::Unsupported;
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Opcode decoded = Opcode::UNSUPPORTED;
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};
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constexpr ImageDimension DecodeImageDimension(uint32_t dim) {
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@@ -178,26 +178,26 @@ constexpr MimgSampleInfo MIMG_SAMPLE_OPCODE_LIST[] = {
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};
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constexpr MimgGatherInfo MIMG_GATHER_OPCODE_LIST[] = {
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{0x47u, "image_gather4_lz", Opcode::ImageGather4Lz, ImageSampleFlagLevelZero, 2u},
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{0x48u, "image_gather4_c", Opcode::ImageGather4C, ImageSampleFlagCompare, 3u},
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{0x4fu, "image_gather4_c_lz", Opcode::ImageGather4CLz,
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{0x47u, "image_gather4_lz", Opcode::IMAGE_GATHER4_LZ, ImageSampleFlagLevelZero, 2u},
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{0x48u, "image_gather4_c", Opcode::IMAGE_GATHER4_C, ImageSampleFlagCompare, 3u},
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{0x4fu, "image_gather4_c_lz", Opcode::IMAGE_GATHER4_C_LZ,
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ImageSampleFlagCompare | ImageSampleFlagLevelZero, 3u},
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{0x57u, "image_gather4_lz_o", Opcode::ImageGather4LzO,
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{0x57u, "image_gather4_lz_o", Opcode::IMAGE_GATHER4_LZ_O,
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ImageSampleFlagLevelZero | ImageSampleFlagOffset, 3u},
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{0x58u, "image_gather4_c_o", Opcode::ImageGather4CO,
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{0x58u, "image_gather4_c_o", Opcode::IMAGE_GATHER4_C_O,
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ImageSampleFlagCompare | ImageSampleFlagOffset, 4u},
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{0x5fu, "image_gather4_c_lz_o", Opcode::ImageGather4CLzO,
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{0x5fu, "image_gather4_c_lz_o", Opcode::IMAGE_GATHER4_C_LZ_O,
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ImageSampleFlagCompare | ImageSampleFlagLevelZero | ImageSampleFlagOffset, 4u},
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{0x61u, "image_gather4h", Opcode::ImageGather4H, ImageSampleFlagGatherHorizontal, 2u},
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{0x61u, "image_gather4h", Opcode::IMAGE_GATHER4H, ImageSampleFlagGatherHorizontal, 2u},
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};
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constexpr MimgAtomicInfo MIMG_ATOMIC_OPCODE_LIST[] = {
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{0x11u, "image_atomic_add", Opcode::ImageAtomicAdd},
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{0x15u, "image_atomic_umin", Opcode::ImageAtomicUMin},
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{0x17u, "image_atomic_umax", Opcode::ImageAtomicUMax},
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{0x18u, "image_atomic_and", Opcode::ImageAtomicAnd},
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{0x19u, "image_atomic_or", Opcode::ImageAtomicOr},
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{0x1au, "image_atomic_xor", Opcode::ImageAtomicXor},
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{0x11u, "image_atomic_add", Opcode::IMAGE_ATOMIC_ADD},
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{0x15u, "image_atomic_umin", Opcode::IMAGE_ATOMIC_UMIN},
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{0x17u, "image_atomic_umax", Opcode::IMAGE_ATOMIC_UMAX},
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{0x18u, "image_atomic_and", Opcode::IMAGE_ATOMIC_AND},
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{0x19u, "image_atomic_or", Opcode::IMAGE_ATOMIC_OR},
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{0x1au, "image_atomic_xor", Opcode::IMAGE_ATOMIC_XOR},
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};
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constexpr auto MIMG_SAMPLE_OPS = Detail::MakeOpcodeTable<0x100>(MIMG_SAMPLE_OPCODE_LIST);
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@@ -219,7 +219,7 @@ const MimgAtomicInfo* LookupAtomic(uint32_t opcode) {
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Opcode DecodeMimgOpcode(uint32_t opcode, const MimgSampleInfo* sample, const MimgGatherInfo* gather,
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const MimgAtomicInfo* atomic) {
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if (sample != nullptr) {
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return Opcode::ImageSample;
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return Opcode::IMAGE_SAMPLE;
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}
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if (gather != nullptr) {
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return gather->decoded;
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@@ -229,13 +229,13 @@ Opcode DecodeMimgOpcode(uint32_t opcode, const MimgSampleInfo* sample, const Mim
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}
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switch (opcode) {
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case 0x00u: return Opcode::ImageLoad;
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case 0x01u: return Opcode::ImageLoadMip;
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case 0x08u: return Opcode::ImageStore;
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case 0x09u: return Opcode::ImageStoreMip;
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case 0x0eu: return Opcode::ImageGetResinfo;
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case 0x60u: return Opcode::ImageGetLod;
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default: return Opcode::Unsupported;
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case 0x00u: return Opcode::IMAGE_LOAD;
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case 0x01u: return Opcode::IMAGE_LOAD_MIP;
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case 0x08u: return Opcode::IMAGE_STORE;
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case 0x09u: return Opcode::IMAGE_STORE_MIP;
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case 0x0eu: return Opcode::IMAGE_GET_RESINFO;
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case 0x60u: return Opcode::IMAGE_GET_LOD;
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default: return Opcode::UNSUPPORTED;
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}
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}
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@@ -327,7 +327,7 @@ void DecodeMimg(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
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DecodeMimgAddressComponents(opcode, dimension, sample, gather, atomic);
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SetRawWords(inst, code, word_index, word_count);
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if (inst.opcode == Opcode::Unsupported) {
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if (inst.opcode == Opcode::UNSUPPORTED) {
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SetUnsupported(inst, Family::MIMG, opcode, "MIMG opcode is not implemented");
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}
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if (gather != nullptr && !IsSingleDmaskBit(inst.dmask)) {
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@@ -7,7 +7,7 @@ namespace {
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struct MemoryOpcodeInfo {
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uint32_t encoding = 0;
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Opcode decoded = Opcode::Unsupported;
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Opcode decoded = Opcode::UNSUPPORTED;
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uint32_t data_dwords = 1;
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uint32_t data_bits = 32;
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bool data_signed = false;
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@@ -16,96 +16,96 @@ struct MemoryOpcodeInfo {
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};
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constexpr MemoryOpcodeInfo SMEM_OPCODE_LIST[] = {
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{0x00u, Opcode::SLoadDword, 1, 32}, {0x01u, Opcode::SLoadDwordx2, 2, 32},
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{0x02u, Opcode::SLoadDwordx4, 4, 32}, {0x03u, Opcode::SLoadDwordx8, 8, 32},
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{0x04u, Opcode::SLoadDwordx16, 16, 32}, {0x08u, Opcode::SBufferLoadDword, 1, 32},
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{0x09u, Opcode::SBufferLoadDwordx2, 2, 32}, {0x0au, Opcode::SBufferLoadDwordx4, 4, 32},
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{0x0bu, Opcode::SBufferLoadDwordx8, 8, 32}, {0x0cu, Opcode::SBufferLoadDwordx16, 16, 32},
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{0x00u, Opcode::S_LOAD_DWORD, 1, 32}, {0x01u, Opcode::S_LOAD_DWORDX2, 2, 32},
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{0x02u, Opcode::S_LOAD_DWORDX4, 4, 32}, {0x03u, Opcode::S_LOAD_DWORDX8, 8, 32},
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{0x04u, Opcode::S_LOAD_DWORDX16, 16, 32}, {0x08u, Opcode::S_BUFFER_LOAD_DWORD, 1, 32},
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{0x09u, Opcode::S_BUFFER_LOAD_DWORDX2, 2, 32}, {0x0au, Opcode::S_BUFFER_LOAD_DWORDX4, 4, 32},
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{0x0bu, Opcode::S_BUFFER_LOAD_DWORDX8, 8, 32}, {0x0cu, Opcode::S_BUFFER_LOAD_DWORDX16, 16, 32},
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};
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constexpr MemoryOpcodeInfo MUBUF_OPCODE_LIST[] = {
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{0x00u, Opcode::BufferLoadFormatX, 1, 32, false, false, true},
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{0x01u, Opcode::BufferLoadFormatXy, 2, 32, false, false, true},
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{0x02u, Opcode::BufferLoadFormatXyz, 3, 32, false, false, true},
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{0x03u, Opcode::BufferLoadFormatXyzw, 4, 32, false, false, true},
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{0x04u, Opcode::BufferStoreFormatX, 1, 32, false, false, true},
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{0x05u, Opcode::BufferStoreFormatXy, 2, 32, false, false, true},
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{0x06u, Opcode::BufferStoreFormatXyz, 3, 32, false, false, true},
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{0x07u, Opcode::BufferStoreFormatXyzw, 4, 32, false, false, true},
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{0x08u, Opcode::BufferLoadUbyte, 1, 8},
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{0x09u, Opcode::BufferLoadSbyte, 1, 8, true},
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{0x0au, Opcode::BufferLoadUshort, 1, 16},
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{0x0bu, Opcode::BufferLoadSshort, 1, 16, true},
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{0x0cu, Opcode::BufferLoadDword, 1, 32},
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{0x0du, Opcode::BufferLoadDwordx2, 2, 32},
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{0x0eu, Opcode::BufferLoadDwordx4, 4, 32},
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{0x0fu, Opcode::BufferLoadDwordx3, 3, 32},
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{0x18u, Opcode::BufferStoreByte, 1, 8},
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{0x1au, Opcode::BufferStoreShort, 1, 16},
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{0x1cu, Opcode::BufferStoreDword, 1, 32},
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{0x1du, Opcode::BufferStoreDwordx2, 2, 32},
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{0x1eu, Opcode::BufferStoreDwordx4, 4, 32},
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{0x1fu, Opcode::BufferStoreDwordx3, 3, 32},
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{0x30u, Opcode::BufferAtomicSwap, 1, 32},
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{0x32u, Opcode::BufferAtomicAdd, 1, 32},
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{0x33u, Opcode::BufferAtomicSub, 1, 32},
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{0x35u, Opcode::BufferAtomicSMin, 1, 32},
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{0x36u, Opcode::BufferAtomicUMin, 1, 32},
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{0x37u, Opcode::BufferAtomicSMax, 1, 32},
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{0x38u, Opcode::BufferAtomicUMax, 1, 32},
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{0x39u, Opcode::BufferAtomicAnd, 1, 32},
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{0x3au, Opcode::BufferAtomicOr, 1, 32},
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{0x3bu, Opcode::BufferAtomicXor, 1, 32},
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{0x3fu, Opcode::BufferAtomicFMin, 1, 32},
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{0x40u, Opcode::BufferAtomicFMax, 1, 32},
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{0x00u, Opcode::BUFFER_LOAD_FORMAT_X, 1, 32, false, false, true},
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{0x01u, Opcode::BUFFER_LOAD_FORMAT_XY, 2, 32, false, false, true},
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{0x02u, Opcode::BUFFER_LOAD_FORMAT_XYZ, 3, 32, false, false, true},
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{0x03u, Opcode::BUFFER_LOAD_FORMAT_XYZW, 4, 32, false, false, true},
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{0x04u, Opcode::BUFFER_STORE_FORMAT_X, 1, 32, false, false, true},
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{0x05u, Opcode::BUFFER_STORE_FORMAT_XY, 2, 32, false, false, true},
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{0x06u, Opcode::BUFFER_STORE_FORMAT_XYZ, 3, 32, false, false, true},
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{0x07u, Opcode::BUFFER_STORE_FORMAT_XYZW, 4, 32, false, false, true},
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{0x08u, Opcode::BUFFER_LOAD_UBYTE, 1, 8},
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{0x09u, Opcode::BUFFER_LOAD_SBYTE, 1, 8, true},
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{0x0au, Opcode::BUFFER_LOAD_USHORT, 1, 16},
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{0x0bu, Opcode::BUFFER_LOAD_SSHORT, 1, 16, true},
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{0x0cu, Opcode::BUFFER_LOAD_DWORD, 1, 32},
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{0x0du, Opcode::BUFFER_LOAD_DWORDX2, 2, 32},
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{0x0eu, Opcode::BUFFER_LOAD_DWORDX4, 4, 32},
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{0x0fu, Opcode::BUFFER_LOAD_DWORDX3, 3, 32},
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{0x18u, Opcode::BUFFER_STORE_BYTE, 1, 8},
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{0x1au, Opcode::BUFFER_STORE_SHORT, 1, 16},
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{0x1cu, Opcode::BUFFER_STORE_DWORD, 1, 32},
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{0x1du, Opcode::BUFFER_STORE_DWORDX2, 2, 32},
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{0x1eu, Opcode::BUFFER_STORE_DWORDX4, 4, 32},
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{0x1fu, Opcode::BUFFER_STORE_DWORDX3, 3, 32},
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{0x30u, Opcode::BUFFER_ATOMIC_SWAP, 1, 32},
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{0x32u, Opcode::BUFFER_ATOMIC_ADD, 1, 32},
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{0x33u, Opcode::BUFFER_ATOMIC_SUB, 1, 32},
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{0x35u, Opcode::BUFFER_ATOMIC_SMIN, 1, 32},
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{0x36u, Opcode::BUFFER_ATOMIC_UMIN, 1, 32},
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{0x37u, Opcode::BUFFER_ATOMIC_SMAX, 1, 32},
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{0x38u, Opcode::BUFFER_ATOMIC_UMAX, 1, 32},
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{0x39u, Opcode::BUFFER_ATOMIC_AND, 1, 32},
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{0x3au, Opcode::BUFFER_ATOMIC_OR, 1, 32},
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{0x3bu, Opcode::BUFFER_ATOMIC_XOR, 1, 32},
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{0x3fu, Opcode::BUFFER_ATOMIC_FMIN, 1, 32},
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{0x40u, Opcode::BUFFER_ATOMIC_FMAX, 1, 32},
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};
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constexpr MemoryOpcodeInfo MTBUF_OPCODE_LIST[] = {
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{0x00u, Opcode::TBufferLoadFormatX, 1, 32, false, true, true},
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{0x01u, Opcode::TBufferLoadFormatXy, 2, 32, false, true, true},
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{0x02u, Opcode::TBufferLoadFormatXyz, 3, 32, false, true, true},
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{0x03u, Opcode::TBufferLoadFormatXyzw, 4, 32, false, true, true},
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{0x04u, Opcode::TBufferStoreFormatX, 1, 32, false, true, true},
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{0x05u, Opcode::TBufferStoreFormatXy, 2, 32, false, true, true},
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{0x06u, Opcode::TBufferStoreFormatXyz, 3, 32, false, true, true},
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{0x07u, Opcode::TBufferStoreFormatXyzw, 4, 32, false, true, true},
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{0x00u, Opcode::TBUFFER_LOAD_FORMAT_X, 1, 32, false, true, true},
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{0x01u, Opcode::TBUFFER_LOAD_FORMAT_XY, 2, 32, false, true, true},
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{0x02u, Opcode::TBUFFER_LOAD_FORMAT_XYZ, 3, 32, false, true, true},
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{0x03u, Opcode::TBUFFER_LOAD_FORMAT_XYZW, 4, 32, false, true, true},
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{0x04u, Opcode::TBUFFER_STORE_FORMAT_X, 1, 32, false, true, true},
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{0x05u, Opcode::TBUFFER_STORE_FORMAT_XY, 2, 32, false, true, true},
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{0x06u, Opcode::TBUFFER_STORE_FORMAT_XYZ, 3, 32, false, true, true},
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{0x07u, Opcode::TBUFFER_STORE_FORMAT_XYZW, 4, 32, false, true, true},
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};
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constexpr MemoryOpcodeInfo FLAT_OPCODE_LIST[] = {
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{0x08u, Opcode::FlatLoadUbyte, 1, 8}, {0x09u, Opcode::FlatLoadSbyte, 1, 8, true},
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{0x0au, Opcode::FlatLoadUshort, 1, 16}, {0x0bu, Opcode::FlatLoadSshort, 1, 16, true},
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{0x0cu, Opcode::FlatLoadDword, 1, 32}, {0x0du, Opcode::FlatLoadDwordx2, 2, 32},
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{0x0eu, Opcode::FlatLoadDwordx4, 4, 32}, {0x0fu, Opcode::FlatLoadDwordx3, 3, 32},
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{0x18u, Opcode::FlatStoreByte, 1, 8}, {0x1au, Opcode::FlatStoreShort, 1, 16},
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{0x1cu, Opcode::FlatStoreDword, 1, 32}, {0x1du, Opcode::FlatStoreDwordx2, 2, 32},
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{0x1eu, Opcode::FlatStoreDwordx4, 4, 32}, {0x1fu, Opcode::FlatStoreDwordx3, 3, 32},
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{0x08u, Opcode::FLAT_LOAD_UBYTE, 1, 8}, {0x09u, Opcode::FLAT_LOAD_SBYTE, 1, 8, true},
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{0x0au, Opcode::FLAT_LOAD_USHORT, 1, 16}, {0x0bu, Opcode::FLAT_LOAD_SSHORT, 1, 16, true},
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{0x0cu, Opcode::FLAT_LOAD_DWORD, 1, 32}, {0x0du, Opcode::FLAT_LOAD_DWORDX2, 2, 32},
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{0x0eu, Opcode::FLAT_LOAD_DWORDX4, 4, 32}, {0x0fu, Opcode::FLAT_LOAD_DWORDX3, 3, 32},
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{0x18u, Opcode::FLAT_STORE_BYTE, 1, 8}, {0x1au, Opcode::FLAT_STORE_SHORT, 1, 16},
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{0x1cu, Opcode::FLAT_STORE_DWORD, 1, 32}, {0x1du, Opcode::FLAT_STORE_DWORDX2, 2, 32},
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{0x1eu, Opcode::FLAT_STORE_DWORDX4, 4, 32}, {0x1fu, Opcode::FLAT_STORE_DWORDX3, 3, 32},
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};
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constexpr MemoryOpcodeInfo DS_OPCODE_LIST[] = {
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{0x00u, Opcode::DsAddU32, 1, 32}, {0x01u, Opcode::DsSubU32, 1, 32},
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{0x05u, Opcode::DsMinI32, 1, 32}, {0x06u, Opcode::DsMaxI32, 1, 32},
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{0x07u, Opcode::DsMinU32, 1, 32}, {0x08u, Opcode::DsMaxU32, 1, 32},
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{0x09u, Opcode::DsAndB32, 1, 32}, {0x0au, Opcode::DsOrB32, 1, 32},
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{0x0bu, Opcode::DsXorB32, 1, 32}, {0x0du, Opcode::DsWriteB32, 1, 32},
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{0x0eu, Opcode::DsWrite2B32, 2, 32}, {0x0fu, Opcode::DsWrite2St64B32, 2, 32},
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{0x12u, Opcode::DsMinF32, 1, 32}, {0x13u, Opcode::DsMaxF32, 1, 32},
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{0x1eu, Opcode::DsWriteByte, 1, 8}, {0x1fu, Opcode::DsWriteShort, 1, 16},
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{0x20u, Opcode::DsAddRtnU32, 1, 32}, {0x21u, Opcode::DsSubRtnU32, 1, 32},
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{0x25u, Opcode::DsMinRtnI32, 1, 32}, {0x26u, Opcode::DsMaxRtnI32, 1, 32},
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{0x27u, Opcode::DsMinRtnU32, 1, 32}, {0x28u, Opcode::DsMaxRtnU32, 1, 32},
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{0x29u, Opcode::DsAndRtnB32, 1, 32}, {0x2au, Opcode::DsOrRtnB32, 1, 32},
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{0x2bu, Opcode::DsXorRtnB32, 1, 32}, {0x2du, Opcode::DsWrxchgRtnB32, 1, 32},
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{0x35u, Opcode::DsSwizzleB32, 1, 32}, {0x36u, Opcode::DsReadB32, 1, 32},
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{0x37u, Opcode::DsRead2B32, 2, 32}, {0x38u, Opcode::DsRead2B32, 2, 32},
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{0x39u, Opcode::DsReadSbyte, 1, 8, true}, {0x3au, Opcode::DsReadUbyte, 1, 8},
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{0x3bu, Opcode::DsReadSshort, 1, 16, true}, {0x3cu, Opcode::DsReadUshort, 1, 16},
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{0x3du, Opcode::DsConsume, 1, 32}, {0x3eu, Opcode::DsAppend, 1, 32},
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{0x4du, Opcode::DsWriteB64, 2, 32}, {0x4eu, Opcode::DsWrite2B64, 4, 32},
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{0x4fu, Opcode::DsWrite2St64B64, 4, 32}, {0x76u, Opcode::DsReadB64, 2, 32},
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{0x77u, Opcode::DsRead2B64, 4, 32}, {0x78u, Opcode::DsRead2St64B64, 4, 32},
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{0xb0u, Opcode::DsWriteAddtidB32, 1, 32}, {0xb1u, Opcode::DsReadAddtidB32, 1, 32},
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{0xdeu, Opcode::DsWriteB96, 3, 32}, {0xdfu, Opcode::DsWriteB128, 4, 32},
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{0xfeu, Opcode::DsReadB96, 3, 32}, {0xffu, Opcode::DsReadB128, 4, 32},
|
||||
{0x00u, Opcode::DS_ADD_U32, 1, 32}, {0x01u, Opcode::DS_SUB_U32, 1, 32},
|
||||
{0x05u, Opcode::DS_MIN_I32, 1, 32}, {0x06u, Opcode::DS_MAX_I32, 1, 32},
|
||||
{0x07u, Opcode::DS_MIN_U32, 1, 32}, {0x08u, Opcode::DS_MAX_U32, 1, 32},
|
||||
{0x09u, Opcode::DS_AND_B32, 1, 32}, {0x0au, Opcode::DS_OR_B32, 1, 32},
|
||||
{0x0bu, Opcode::DS_XOR_B32, 1, 32}, {0x0du, Opcode::DS_WRITE_B32, 1, 32},
|
||||
{0x0eu, Opcode::DS_WRITE2_B32, 2, 32}, {0x0fu, Opcode::DS_WRITE2ST64_B32, 2, 32},
|
||||
{0x12u, Opcode::DS_MIN_F32, 1, 32}, {0x13u, Opcode::DS_MAX_F32, 1, 32},
|
||||
{0x1eu, Opcode::DS_WRITE_B8, 1, 8}, {0x1fu, Opcode::DS_WRITE_B16, 1, 16},
|
||||
{0x20u, Opcode::DS_ADD_RTN_U32, 1, 32}, {0x21u, Opcode::DS_SUB_RTN_U32, 1, 32},
|
||||
{0x25u, Opcode::DS_MIN_RTN_I32, 1, 32}, {0x26u, Opcode::DS_MAX_RTN_I32, 1, 32},
|
||||
{0x27u, Opcode::DS_MIN_RTN_U32, 1, 32}, {0x28u, Opcode::DS_MAX_RTN_U32, 1, 32},
|
||||
{0x29u, Opcode::DS_AND_RTN_B32, 1, 32}, {0x2au, Opcode::DS_OR_RTN_B32, 1, 32},
|
||||
{0x2bu, Opcode::DS_XOR_RTN_B32, 1, 32}, {0x2du, Opcode::DS_WRXCHG_RTN_B32, 1, 32},
|
||||
{0x35u, Opcode::DS_SWIZZLE_B32, 1, 32}, {0x36u, Opcode::DS_READ_B32, 1, 32},
|
||||
{0x37u, Opcode::DS_READ2_B32, 2, 32}, {0x38u, Opcode::DS_READ2_B32, 2, 32},
|
||||
{0x39u, Opcode::DS_READ_I8, 1, 8, true}, {0x3au, Opcode::DS_READ_U8, 1, 8},
|
||||
{0x3bu, Opcode::DS_READ_I16, 1, 16, true}, {0x3cu, Opcode::DS_READ_U16, 1, 16},
|
||||
{0x3du, Opcode::DS_CONSUME, 1, 32}, {0x3eu, Opcode::DS_APPEND, 1, 32},
|
||||
{0x4du, Opcode::DS_WRITE_B64, 2, 32}, {0x4eu, Opcode::DS_WRITE2_B64, 4, 32},
|
||||
{0x4fu, Opcode::DS_WRITE2ST64_B64, 4, 32}, {0x76u, Opcode::DS_READ_B64, 2, 32},
|
||||
{0x77u, Opcode::DS_READ2_B64, 4, 32}, {0x78u, Opcode::DS_READ2ST64_B64, 4, 32},
|
||||
{0xb0u, Opcode::DS_WRITE_ADDTID_B32, 1, 32}, {0xb1u, Opcode::DS_READ_ADDTID_B32, 1, 32},
|
||||
{0xdeu, Opcode::DS_WRITE_B96, 3, 32}, {0xdfu, Opcode::DS_WRITE_B128, 4, 32},
|
||||
{0xfeu, Opcode::DS_READ_B96, 3, 32}, {0xffu, Opcode::DS_READ_B128, 4, 32},
|
||||
};
|
||||
|
||||
constexpr auto SMEM_OPS = Detail::MakeOpcodeTable<0x100>(SMEM_OPCODE_LIST);
|
||||
@@ -125,13 +125,13 @@ uint32_t SignExtendU32(uint32_t value, uint32_t bits) {
|
||||
void MarkMemoryUnsupported(Instruction& inst, Family family, uint32_t opcode, const char* reason) {
|
||||
inst.family = family;
|
||||
inst.opcode_id = opcode;
|
||||
inst.opcode = Opcode::Unsupported;
|
||||
inst.opcode = Opcode::UNSUPPORTED;
|
||||
SetUnsupported(inst, family, opcode, reason);
|
||||
}
|
||||
|
||||
void ApplyMemoryInfo(Instruction& inst, const MemoryOpcodeInfo* info) {
|
||||
if (info == nullptr) {
|
||||
inst.opcode = Opcode::Unsupported;
|
||||
inst.opcode = Opcode::UNSUPPORTED;
|
||||
return;
|
||||
}
|
||||
inst.opcode = info->decoded;
|
||||
@@ -144,68 +144,68 @@ void ApplyMemoryInfo(Instruction& inst, const MemoryOpcodeInfo* info) {
|
||||
|
||||
bool IsDsWriteOpcode(Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Opcode::DsWriteByte:
|
||||
case Opcode::DsWriteShort:
|
||||
case Opcode::DsWrite2B32:
|
||||
case Opcode::DsWrite2St64B32:
|
||||
case Opcode::DsWrite2B64:
|
||||
case Opcode::DsWrite2St64B64:
|
||||
case Opcode::DsWriteB32:
|
||||
case Opcode::DsWriteB64:
|
||||
case Opcode::DsWriteB96:
|
||||
case Opcode::DsWriteB128: return true;
|
||||
case Opcode::DS_WRITE_B8:
|
||||
case Opcode::DS_WRITE_B16:
|
||||
case Opcode::DS_WRITE2_B32:
|
||||
case Opcode::DS_WRITE2ST64_B32:
|
||||
case Opcode::DS_WRITE2_B64:
|
||||
case Opcode::DS_WRITE2ST64_B64:
|
||||
case Opcode::DS_WRITE_B32:
|
||||
case Opcode::DS_WRITE_B64:
|
||||
case Opcode::DS_WRITE_B96:
|
||||
case Opcode::DS_WRITE_B128: return true;
|
||||
default: return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsDsAtomicOpcode(Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Opcode::DsAddU32:
|
||||
case Opcode::DsAddRtnU32:
|
||||
case Opcode::DsSubU32:
|
||||
case Opcode::DsSubRtnU32:
|
||||
case Opcode::DsMinI32:
|
||||
case Opcode::DsMinRtnI32:
|
||||
case Opcode::DsMaxI32:
|
||||
case Opcode::DsMaxRtnI32:
|
||||
case Opcode::DsMinU32:
|
||||
case Opcode::DsMinRtnU32:
|
||||
case Opcode::DsMaxU32:
|
||||
case Opcode::DsMaxRtnU32:
|
||||
case Opcode::DsAndB32:
|
||||
case Opcode::DsAndRtnB32:
|
||||
case Opcode::DsOrB32:
|
||||
case Opcode::DsOrRtnB32:
|
||||
case Opcode::DsXorB32:
|
||||
case Opcode::DsXorRtnB32:
|
||||
case Opcode::DsWrxchgRtnB32: return true;
|
||||
case Opcode::DS_ADD_U32:
|
||||
case Opcode::DS_ADD_RTN_U32:
|
||||
case Opcode::DS_SUB_U32:
|
||||
case Opcode::DS_SUB_RTN_U32:
|
||||
case Opcode::DS_MIN_I32:
|
||||
case Opcode::DS_MIN_RTN_I32:
|
||||
case Opcode::DS_MAX_I32:
|
||||
case Opcode::DS_MAX_RTN_I32:
|
||||
case Opcode::DS_MIN_U32:
|
||||
case Opcode::DS_MIN_RTN_U32:
|
||||
case Opcode::DS_MAX_U32:
|
||||
case Opcode::DS_MAX_RTN_U32:
|
||||
case Opcode::DS_AND_B32:
|
||||
case Opcode::DS_AND_RTN_B32:
|
||||
case Opcode::DS_OR_B32:
|
||||
case Opcode::DS_OR_RTN_B32:
|
||||
case Opcode::DS_XOR_B32:
|
||||
case Opcode::DS_XOR_RTN_B32:
|
||||
case Opcode::DS_WRXCHG_RTN_B32: return true;
|
||||
default: return false;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t DsSourceCount(Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Opcode::DsWrite2B32:
|
||||
case Opcode::DsWrite2St64B32:
|
||||
case Opcode::DsWrite2B64:
|
||||
case Opcode::DsWrite2St64B64:
|
||||
case Opcode::DsMinF32:
|
||||
case Opcode::DsMaxF32: return 3u;
|
||||
case Opcode::DsReadAddtidB32:
|
||||
case Opcode::DsConsume:
|
||||
case Opcode::DsAppend: return 0u;
|
||||
case Opcode::DS_WRITE2_B32:
|
||||
case Opcode::DS_WRITE2ST64_B32:
|
||||
case Opcode::DS_WRITE2_B64:
|
||||
case Opcode::DS_WRITE2ST64_B64:
|
||||
case Opcode::DS_MIN_F32:
|
||||
case Opcode::DS_MAX_F32: return 3u;
|
||||
case Opcode::DS_READ_ADDTID_B32:
|
||||
case Opcode::DS_CONSUME:
|
||||
case Opcode::DS_APPEND: return 0u;
|
||||
default: return IsDsWriteOpcode(opcode) || IsDsAtomicOpcode(opcode) ? 2u : 1u;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsFlatStoreOpcode(Opcode opcode) {
|
||||
switch (opcode) {
|
||||
case Opcode::FlatStoreByte:
|
||||
case Opcode::FlatStoreShort:
|
||||
case Opcode::FlatStoreDword:
|
||||
case Opcode::FlatStoreDwordx2:
|
||||
case Opcode::FlatStoreDwordx3:
|
||||
case Opcode::FlatStoreDwordx4: return true;
|
||||
case Opcode::FLAT_STORE_BYTE:
|
||||
case Opcode::FLAT_STORE_SHORT:
|
||||
case Opcode::FLAT_STORE_DWORD:
|
||||
case Opcode::FLAT_STORE_DWORDX2:
|
||||
case Opcode::FLAT_STORE_DWORDX3:
|
||||
case Opcode::FLAT_STORE_DWORDX4: return true;
|
||||
default: return false;
|
||||
}
|
||||
}
|
||||
@@ -231,7 +231,7 @@ void DecodeSmem(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
const auto* info = Detail::FindOpcode(SMEM_OPS, opcode);
|
||||
ApplyMemoryInfo(inst, info);
|
||||
SetRawWords(inst, code, word_index, 2);
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
MarkMemoryUnsupported(inst, Family::SMEM, opcode, "SMEM opcode is not implemented");
|
||||
}
|
||||
|
||||
@@ -266,7 +266,7 @@ void DecodeMubuf(uint32_t pc, std::span<const uint32_t> code, uint32_t word_inde
|
||||
const auto* info = Detail::FindOpcode(MUBUF_OPS, opcode);
|
||||
ApplyMemoryInfo(inst, info);
|
||||
SetRawWords(inst, code, word_index, 2);
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
MarkMemoryUnsupported(inst, Family::MUBUF, opcode, "MUBUF opcode is not implemented");
|
||||
}
|
||||
|
||||
@@ -304,7 +304,7 @@ void DecodeMtbuf(uint32_t pc, std::span<const uint32_t> code, uint32_t word_inde
|
||||
const auto* info = Detail::FindOpcode(MTBUF_OPS, opcode);
|
||||
ApplyMemoryInfo(inst, info);
|
||||
SetRawWords(inst, code, word_index, 2);
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
MarkMemoryUnsupported(inst, Family::MTBUF, opcode, "MTBUF opcode is not implemented");
|
||||
}
|
||||
|
||||
@@ -346,7 +346,7 @@ void DecodeFlat(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
SetUnsupported(inst, Family::FLAT, opcode, "FLAT modifiers or segment are not implemented");
|
||||
return;
|
||||
}
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
MarkMemoryUnsupported(inst, Family::FLAT, opcode, "FLAT opcode is not implemented");
|
||||
return;
|
||||
}
|
||||
@@ -384,35 +384,36 @@ void DecodeDs(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
|
||||
const auto* info = Detail::FindOpcode(DS_OPS, opcode);
|
||||
ApplyMemoryInfo(inst, info);
|
||||
SetRawWords(inst, code, word_index, 2);
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
MarkMemoryUnsupported(inst, Family::DS, opcode, "DS opcode is not implemented");
|
||||
}
|
||||
if (inst.opcode == Opcode::DsSwizzleB32 && inst.offset >= 0xe000u) {
|
||||
if (inst.opcode == Opcode::DS_SWIZZLE_B32 && inst.offset >= 0xe000u) {
|
||||
SetUnsupported(inst, Family::DS, opcode, "DS swizzle FFT mode is not implemented");
|
||||
}
|
||||
if (inst.gds &&
|
||||
(inst.opcode == Opcode::DsSwizzleB32 || inst.opcode == Opcode::DsWriteAddtidB32 ||
|
||||
inst.opcode == Opcode::DsReadAddtidB32)) {
|
||||
(inst.opcode == Opcode::DS_SWIZZLE_B32 || inst.opcode == Opcode::DS_WRITE_ADDTID_B32 ||
|
||||
inst.opcode == Opcode::DS_READ_ADDTID_B32)) {
|
||||
SetUnsupported(inst, Family::DS, opcode, "DS swizzle/addtid is available only for LDS");
|
||||
}
|
||||
if (inst.opcode == Opcode::DsWriteAddtidB32 && data1 != 0u) {
|
||||
if (inst.opcode == Opcode::DS_WRITE_ADDTID_B32 && data1 != 0u) {
|
||||
SetUnsupported(inst, Family::DS, opcode,
|
||||
"DS write addtid data1 operand is not implemented");
|
||||
}
|
||||
if (inst.opcode == Opcode::DsReadAddtidB32 && (data0 != 0u || data1 != 0u)) {
|
||||
if (inst.opcode == Opcode::DS_READ_ADDTID_B32 && (data0 != 0u || data1 != 0u)) {
|
||||
SetUnsupported(inst, Family::DS, opcode,
|
||||
"DS read addtid data operands are not implemented");
|
||||
}
|
||||
if (inst.opcode == Opcode::DsWrite2B32 || opcode == 0x37u) {
|
||||
if (inst.opcode == Opcode::DS_WRITE2_B32 || opcode == 0x37u) {
|
||||
inst.offset = offset0 * 4u;
|
||||
inst.secondary_offset = offset1 * 4u;
|
||||
} else if (inst.opcode == Opcode::DsWrite2St64B32 || opcode == 0x38u) {
|
||||
} else if (inst.opcode == Opcode::DS_WRITE2ST64_B32 || opcode == 0x38u) {
|
||||
inst.offset = offset0 * 256u;
|
||||
inst.secondary_offset = offset1 * 256u;
|
||||
} else if (inst.opcode == Opcode::DsWrite2B64 || inst.opcode == Opcode::DsRead2B64) {
|
||||
} else if (inst.opcode == Opcode::DS_WRITE2_B64 || inst.opcode == Opcode::DS_READ2_B64) {
|
||||
inst.offset = offset0 * 8u;
|
||||
inst.secondary_offset = offset1 * 8u;
|
||||
} else if (inst.opcode == Opcode::DsWrite2St64B64 || inst.opcode == Opcode::DsRead2St64B64) {
|
||||
} else if (inst.opcode == Opcode::DS_WRITE2ST64_B64 ||
|
||||
inst.opcode == Opcode::DS_READ2ST64_B64) {
|
||||
inst.offset = offset0 * 512u;
|
||||
inst.secondary_offset = offset1 * 512u;
|
||||
}
|
||||
|
||||
@@ -11,7 +11,7 @@ namespace Libs::Graphics::ShaderRecompiler::Decoder::Detail {
|
||||
|
||||
struct OpcodeMap {
|
||||
uint32_t encoding = 0;
|
||||
Opcode decoded = Opcode::Unknown;
|
||||
Opcode decoded = Opcode::UNKNOWN;
|
||||
};
|
||||
|
||||
template <typename Entry, size_t EncodingCount, size_t EntryCount>
|
||||
@@ -48,7 +48,7 @@ template <typename Entry, size_t EncodingCount, size_t EntryCount>
|
||||
constexpr Opcode LookupOpcode(const OpcodeTable<Entry, EncodingCount, EntryCount>& table,
|
||||
uint32_t encoding) {
|
||||
const auto* entry = FindOpcode(table, encoding);
|
||||
return entry != nullptr ? entry->decoded : Opcode::Unsupported;
|
||||
return entry != nullptr ? entry->decoded : Opcode::UNSUPPORTED;
|
||||
}
|
||||
|
||||
} // namespace Libs::Graphics::ShaderRecompiler::Decoder::Detail
|
||||
|
||||
@@ -8,67 +8,94 @@ namespace {
|
||||
using Detail::OpcodeMap;
|
||||
|
||||
constexpr OpcodeMap SOP2_OPCODE_LIST[] = {
|
||||
{0x00u, Opcode::SAddU32}, {0x01u, Opcode::SSubU32}, {0x02u, Opcode::SAddI32},
|
||||
{0x03u, Opcode::SSubI32}, {0x04u, Opcode::SAddcU32}, {0x05u, Opcode::SSubbU32},
|
||||
{0x06u, Opcode::SMinI32}, {0x07u, Opcode::SMinU32}, {0x08u, Opcode::SMaxI32},
|
||||
{0x09u, Opcode::SMaxU32}, {0x0au, Opcode::SCselectB32}, {0x0bu, Opcode::SCselectB64},
|
||||
{0x0eu, Opcode::SAndB32}, {0x0fu, Opcode::SAndB64}, {0x10u, Opcode::SOrB32},
|
||||
{0x11u, Opcode::SOrB64}, {0x12u, Opcode::SXorB32}, {0x13u, Opcode::SXorB64},
|
||||
{0x14u, Opcode::SAndn2B32}, {0x15u, Opcode::SAndn2B64}, {0x16u, Opcode::SOrn2B32},
|
||||
{0x17u, Opcode::SOrn2B64}, {0x18u, Opcode::SNandB32}, {0x19u, Opcode::SNandB64},
|
||||
{0x1au, Opcode::SNorB32}, {0x1bu, Opcode::SNorB64}, {0x1cu, Opcode::SXnorB32},
|
||||
{0x1du, Opcode::SXnorB64}, {0x1eu, Opcode::SLshlB32}, {0x1fu, Opcode::SLshlB64},
|
||||
{0x20u, Opcode::SLshrB32}, {0x21u, Opcode::SLshrB64}, {0x22u, Opcode::SAshrI32},
|
||||
{0x24u, Opcode::SBfmB32}, {0x25u, Opcode::SBfmB64}, {0x26u, Opcode::SMulI32},
|
||||
{0x27u, Opcode::SBfeU32}, {0x28u, Opcode::SBfeI32}, {0x29u, Opcode::SBfeU64},
|
||||
{0x2eu, Opcode::SLshl1AddU32}, {0x2fu, Opcode::SLshl2AddU32}, {0x30u, Opcode::SLshl3AddU32},
|
||||
{0x31u, Opcode::SLshl4AddU32}, {0x32u, Opcode::SPackLlB32B16}, {0x33u, Opcode::SPackLhB32B16},
|
||||
{0x34u, Opcode::SPackHhB32B16}, {0x35u, Opcode::SMulHiU32},
|
||||
{0x00u, Opcode::S_ADD_U32}, {0x01u, Opcode::S_SUB_U32},
|
||||
{0x02u, Opcode::S_ADD_I32}, {0x03u, Opcode::S_SUB_I32},
|
||||
{0x04u, Opcode::S_ADDC_U32}, {0x05u, Opcode::S_SUBB_U32},
|
||||
{0x06u, Opcode::S_MIN_I32}, {0x07u, Opcode::S_MIN_U32},
|
||||
{0x08u, Opcode::S_MAX_I32}, {0x09u, Opcode::S_MAX_U32},
|
||||
{0x0au, Opcode::S_CSELECT_B32}, {0x0bu, Opcode::S_CSELECT_B64},
|
||||
{0x0eu, Opcode::S_AND_B32}, {0x0fu, Opcode::S_AND_B64},
|
||||
{0x10u, Opcode::S_OR_B32}, {0x11u, Opcode::S_OR_B64},
|
||||
{0x12u, Opcode::S_XOR_B32}, {0x13u, Opcode::S_XOR_B64},
|
||||
{0x14u, Opcode::S_ANDN2_B32}, {0x15u, Opcode::S_ANDN2_B64},
|
||||
{0x16u, Opcode::S_ORN2_B32}, {0x17u, Opcode::S_ORN2_B64},
|
||||
{0x18u, Opcode::S_NAND_B32}, {0x19u, Opcode::S_NAND_B64},
|
||||
{0x1au, Opcode::S_NOR_B32}, {0x1bu, Opcode::S_NOR_B64},
|
||||
{0x1cu, Opcode::S_XNOR_B32}, {0x1du, Opcode::S_XNOR_B64},
|
||||
{0x1eu, Opcode::S_LSHL_B32}, {0x1fu, Opcode::S_LSHL_B64},
|
||||
{0x20u, Opcode::S_LSHR_B32}, {0x21u, Opcode::S_LSHR_B64},
|
||||
{0x22u, Opcode::S_ASHR_I32}, {0x24u, Opcode::S_BFM_B32},
|
||||
{0x25u, Opcode::S_BFM_B64}, {0x26u, Opcode::S_MUL_I32},
|
||||
{0x27u, Opcode::S_BFE_U32}, {0x28u, Opcode::S_BFE_I32},
|
||||
{0x29u, Opcode::S_BFE_U64}, {0x2eu, Opcode::S_LSHL1_ADD_U32},
|
||||
{0x2fu, Opcode::S_LSHL2_ADD_U32}, {0x30u, Opcode::S_LSHL3_ADD_U32},
|
||||
{0x31u, Opcode::S_LSHL4_ADD_U32}, {0x32u, Opcode::S_PACK_LL_B32_B16},
|
||||
{0x33u, Opcode::S_PACK_LH_B32_B16}, {0x34u, Opcode::S_PACK_HH_B32_B16},
|
||||
{0x35u, Opcode::S_MUL_HI_U32},
|
||||
};
|
||||
|
||||
constexpr OpcodeMap SOP1_OPCODE_LIST[] = {
|
||||
{0x03u, Opcode::SMovB32}, {0x04u, Opcode::SMovB64},
|
||||
{0x07u, Opcode::SNotB32}, {0x08u, Opcode::SNotB64},
|
||||
{0x0au, Opcode::SWqmB64}, {0x0bu, Opcode::SBrevB32},
|
||||
{0x0fu, Opcode::SBcnt1I32B32}, {0x10u, Opcode::SBcnt1I32B64},
|
||||
{0x13u, Opcode::SFf1I32B32}, {0x14u, Opcode::SFf1I32B64},
|
||||
{0x16u, Opcode::SFlbitI32B64}, {0x1bu, Opcode::SBitset0B32},
|
||||
{0x1du, Opcode::SBitset1B32}, {0x1fu, Opcode::SGetpcB64},
|
||||
{0x20u, Opcode::SSetpcB64}, {0x24u, Opcode::SAndSaveexecB64},
|
||||
{0x28u, Opcode::SOrn2SaveexecB64}, {0x34u, Opcode::SAbsI32},
|
||||
{0x37u, Opcode::SAndn1SaveexecB64}, {0x3bu, Opcode::SBitreplicateB64B32},
|
||||
{0x3cu, Opcode::SAndSaveexecB32}, {0x44u, Opcode::SAndn1SaveexecB32},
|
||||
{0x03u, Opcode::S_MOV_B32},
|
||||
{0x04u, Opcode::S_MOV_B64},
|
||||
{0x07u, Opcode::S_NOT_B32},
|
||||
{0x08u, Opcode::S_NOT_B64},
|
||||
{0x0au, Opcode::S_WQM_B64},
|
||||
{0x0bu, Opcode::S_BREV_B32},
|
||||
{0x0fu, Opcode::S_BCNT1_I32_B32},
|
||||
{0x10u, Opcode::S_BCNT1_I32_B64},
|
||||
{0x13u, Opcode::S_FF1_I32_B32},
|
||||
{0x14u, Opcode::S_FF1_I32_B64},
|
||||
{0x16u, Opcode::S_FLBIT_I32_B64},
|
||||
{0x1bu, Opcode::S_BITSET0_B32},
|
||||
{0x1du, Opcode::S_BITSET1_B32},
|
||||
{0x1fu, Opcode::S_GETPC_B64},
|
||||
{0x20u, Opcode::S_SETPC_B64},
|
||||
{0x24u, Opcode::S_AND_SAVEEXEC_B64},
|
||||
{0x28u, Opcode::S_ORN2_SAVEEXEC_B64},
|
||||
{0x34u, Opcode::S_ABS_I32},
|
||||
{0x37u, Opcode::S_ANDN1_SAVEEXEC_B64},
|
||||
{0x3bu, Opcode::S_BITREPLICATE_B64_B32},
|
||||
{0x3cu, Opcode::S_AND_SAVEEXEC_B32},
|
||||
{0x44u, Opcode::S_ANDN1_SAVEEXEC_B32},
|
||||
};
|
||||
|
||||
constexpr OpcodeMap SOPC_OPCODE_LIST[] = {
|
||||
{0x00u, Opcode::SCmpEqI32}, {0x01u, Opcode::SCmpLgI32}, {0x02u, Opcode::SCmpGtI32},
|
||||
{0x03u, Opcode::SCmpGeI32}, {0x04u, Opcode::SCmpLtI32}, {0x05u, Opcode::SCmpLeI32},
|
||||
{0x06u, Opcode::SCmpEqU32}, {0x07u, Opcode::SCmpLgU32}, {0x08u, Opcode::SCmpGtU32},
|
||||
{0x09u, Opcode::SCmpGeU32}, {0x0au, Opcode::SCmpLtU32}, {0x0bu, Opcode::SCmpLeU32},
|
||||
{0x0cu, Opcode::SBitcmp0B32}, {0x0du, Opcode::SBitcmp1B32}, {0x12u, Opcode::SCmpEqU64},
|
||||
{0x13u, Opcode::SCmpLgU64},
|
||||
{0x00u, Opcode::S_CMP_EQ_I32}, {0x01u, Opcode::S_CMP_LG_I32}, {0x02u, Opcode::S_CMP_GT_I32},
|
||||
{0x03u, Opcode::S_CMP_GE_I32}, {0x04u, Opcode::S_CMP_LT_I32}, {0x05u, Opcode::S_CMP_LE_I32},
|
||||
{0x06u, Opcode::S_CMP_EQ_U32}, {0x07u, Opcode::S_CMP_LG_U32}, {0x08u, Opcode::S_CMP_GT_U32},
|
||||
{0x09u, Opcode::S_CMP_GE_U32}, {0x0au, Opcode::S_CMP_LT_U32}, {0x0bu, Opcode::S_CMP_LE_U32},
|
||||
{0x0cu, Opcode::S_BITCMP0_B32}, {0x0du, Opcode::S_BITCMP1_B32}, {0x12u, Opcode::S_CMP_EQ_U64},
|
||||
{0x13u, Opcode::S_CMP_LG_U64},
|
||||
};
|
||||
|
||||
constexpr OpcodeMap SOPK_OPCODE_LIST[] = {
|
||||
{0x00u, Opcode::SMovkI32}, {0x03u, Opcode::SCmpEqI32}, {0x04u, Opcode::SCmpLgI32},
|
||||
{0x05u, Opcode::SCmpGtI32}, {0x06u, Opcode::SCmpGeI32}, {0x07u, Opcode::SCmpLtI32},
|
||||
{0x08u, Opcode::SCmpLeI32}, {0x09u, Opcode::SCmpEqU32}, {0x0au, Opcode::SCmpLgU32},
|
||||
{0x0bu, Opcode::SCmpGtU32}, {0x0cu, Opcode::SCmpGeU32}, {0x0du, Opcode::SCmpLtU32},
|
||||
{0x0eu, Opcode::SCmpLeU32}, {0x0fu, Opcode::SAddI32}, {0x10u, Opcode::SMulkI32},
|
||||
{0x13u, Opcode::SSetregB32}, {0x17u, Opcode::SWaitcnt}, {0x18u, Opcode::SWaitcnt},
|
||||
{0x19u, Opcode::SWaitcnt}, {0x1au, Opcode::SWaitcnt},
|
||||
{0x00u, Opcode::S_MOVK_I32}, {0x03u, Opcode::S_CMP_EQ_I32}, {0x04u, Opcode::S_CMP_LG_I32},
|
||||
{0x05u, Opcode::S_CMP_GT_I32}, {0x06u, Opcode::S_CMP_GE_I32}, {0x07u, Opcode::S_CMP_LT_I32},
|
||||
{0x08u, Opcode::S_CMP_LE_I32}, {0x09u, Opcode::S_CMP_EQ_U32}, {0x0au, Opcode::S_CMP_LG_U32},
|
||||
{0x0bu, Opcode::S_CMP_GT_U32}, {0x0cu, Opcode::S_CMP_GE_U32}, {0x0du, Opcode::S_CMP_LT_U32},
|
||||
{0x0eu, Opcode::S_CMP_LE_U32}, {0x0fu, Opcode::S_ADD_I32}, {0x10u, Opcode::S_MULK_I32},
|
||||
{0x13u, Opcode::S_SETREG_B32}, {0x17u, Opcode::S_WAITCNT}, {0x18u, Opcode::S_WAITCNT},
|
||||
{0x19u, Opcode::S_WAITCNT}, {0x1au, Opcode::S_WAITCNT},
|
||||
};
|
||||
|
||||
constexpr OpcodeMap SOPP_OPCODE_LIST[] = {
|
||||
{0x00u, Opcode::SNop}, {0x01u, Opcode::SEndpgm},
|
||||
{0x02u, Opcode::SBranch}, {0x04u, Opcode::SCbranchScc0},
|
||||
{0x05u, Opcode::SCbranchScc1}, {0x06u, Opcode::SCbranchVccz},
|
||||
{0x07u, Opcode::SCbranchVccnz}, {0x08u, Opcode::SCbranchExecz},
|
||||
{0x09u, Opcode::SCbranchExecnz}, {0x0au, Opcode::SBarrier},
|
||||
{0x0cu, Opcode::SWaitcnt}, {0x0eu, Opcode::SSleep},
|
||||
{0x10u, Opcode::SSendmsg}, {0x12u, Opcode::STrap},
|
||||
{0x16u, Opcode::STtraceData}, {0x20u, Opcode::SInstPrefetch},
|
||||
{0x23u, Opcode::SWaitcntDepctr},
|
||||
{0x00u, Opcode::S_NOP},
|
||||
{0x01u, Opcode::S_ENDPGM},
|
||||
{0x02u, Opcode::S_BRANCH},
|
||||
{0x04u, Opcode::S_CBRANCH_SCC0},
|
||||
{0x05u, Opcode::S_CBRANCH_SCC1},
|
||||
{0x06u, Opcode::S_CBRANCH_VCCZ},
|
||||
{0x07u, Opcode::S_CBRANCH_VCCNZ},
|
||||
{0x08u, Opcode::S_CBRANCH_EXECZ},
|
||||
{0x09u, Opcode::S_CBRANCH_EXECNZ},
|
||||
{0x0au, Opcode::S_BARRIER},
|
||||
{0x0cu, Opcode::S_WAITCNT},
|
||||
{0x0eu, Opcode::S_SLEEP},
|
||||
{0x10u, Opcode::S_SENDMSG},
|
||||
{0x12u, Opcode::S_TRAP},
|
||||
{0x16u, Opcode::S_TTRACEDATA},
|
||||
{0x20u, Opcode::S_INST_PREFETCH},
|
||||
{0x23u, Opcode::S_WAITCNT_DEPCTR},
|
||||
};
|
||||
|
||||
constexpr auto SOP1_OPS = Detail::MakeOpcodeTable<0x100>(SOP1_OPCODE_LIST);
|
||||
@@ -104,16 +131,16 @@ bool DecodeSop1(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.opcode = Detail::LookupOpcode(SOP1_OPS, opcode);
|
||||
SetRawWords(inst, code, word_index, 1);
|
||||
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
SetUnsupported(inst, Family::SOP1, opcode, "SOP1 opcode is not implemented");
|
||||
return true;
|
||||
}
|
||||
|
||||
switch (inst.opcode) {
|
||||
case Opcode::SGetpcB64:
|
||||
case Opcode::S_GETPC_B64:
|
||||
inst.src_count = 0;
|
||||
return DecodeScalarDestination(sdst, pc, inst.dst, error);
|
||||
case Opcode::SSetpcB64:
|
||||
case Opcode::S_SETPC_B64:
|
||||
inst.src_count = 1;
|
||||
inst.dst.kind = OperandKind::Null;
|
||||
if (!DecodeScalarSource(ssrc0, pc, inst.src0, error)) {
|
||||
@@ -148,7 +175,7 @@ bool DecodeSop2(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.opcode = Detail::LookupOpcode(SOP2_OPS, opcode);
|
||||
SetRawWords(inst, code, word_index, 1);
|
||||
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
SetUnsupported(inst, Family::SOP2, opcode, "SOP2 opcode is not implemented");
|
||||
return true;
|
||||
}
|
||||
@@ -177,14 +204,14 @@ bool DecodeSopk(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.src_count = 1;
|
||||
SetRawWords(inst, code, word_index, 1);
|
||||
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
SetUnsupported(inst, Family::SOPK, opcode, "SOPK opcode is not implemented");
|
||||
return true;
|
||||
}
|
||||
|
||||
switch (inst.opcode) {
|
||||
case Opcode::SMovkI32: return DecodeScalarDestination(sdst, pc, inst.dst, error);
|
||||
case Opcode::SWaitcnt: {
|
||||
case Opcode::S_MOVK_I32: return DecodeScalarDestination(sdst, pc, inst.dst, error);
|
||||
case Opcode::S_WAITCNT: {
|
||||
const uint32_t waitcnt = word & 0xffffu;
|
||||
inst.dst.kind = OperandKind::Null;
|
||||
inst.src0.signed_val = static_cast<int32_t>(waitcnt);
|
||||
@@ -192,7 +219,7 @@ bool DecodeSopk(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.src_count = 1;
|
||||
return true;
|
||||
}
|
||||
case Opcode::SSetregB32:
|
||||
case Opcode::S_SETREG_B32:
|
||||
inst.dst.kind = OperandKind::Null;
|
||||
inst.src1.kind = OperandKind::LiteralConstant;
|
||||
inst.src1.value = word & 0xffffu;
|
||||
@@ -206,7 +233,7 @@ bool DecodeSopk(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
if (!DecodeScalarSource(sdst, pc, inst.src0, error)) {
|
||||
return false;
|
||||
}
|
||||
if (inst.opcode == Opcode::SAddI32 || inst.opcode == Opcode::SMulkI32) {
|
||||
if (inst.opcode == Opcode::S_ADD_I32 || inst.opcode == Opcode::S_MULK_I32) {
|
||||
inst.src_count = 2;
|
||||
return DecodeScalarDestination(sdst, pc, inst.dst, error);
|
||||
}
|
||||
@@ -231,7 +258,7 @@ bool DecodeSopc(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.dst.kind = OperandKind::Scc;
|
||||
SetRawWords(inst, code, word_index, 1);
|
||||
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
SetUnsupported(inst, Family::SOPC, opcode, "SOPC opcode is not implemented");
|
||||
return true;
|
||||
}
|
||||
@@ -251,21 +278,21 @@ void DecodeSopp(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index
|
||||
inst.opcode_id = opcode;
|
||||
inst.opcode = Detail::LookupOpcode(SOPP_OPS, opcode);
|
||||
inst.src0.kind = OperandKind::LiteralConstant;
|
||||
inst.src0.value = inst.opcode == Opcode::STrap ? simm & 0xffu : simm;
|
||||
inst.src0.signed_val = inst.opcode == Opcode::STrap
|
||||
inst.src0.value = inst.opcode == Opcode::S_TRAP ? simm & 0xffu : simm;
|
||||
inst.src0.signed_val = inst.opcode == Opcode::S_TRAP
|
||||
? static_cast<int32_t>(inst.src0.value)
|
||||
: static_cast<int32_t>(static_cast<int16_t>(simm));
|
||||
inst.src_count = (inst.opcode == Opcode::SNop || inst.opcode == Opcode::SWaitcnt ||
|
||||
inst.opcode == Opcode::SWaitcntDepctr || inst.opcode == Opcode::SSleep ||
|
||||
inst.opcode == Opcode::SSendmsg || inst.opcode == Opcode::STrap ||
|
||||
inst.opcode == Opcode::STtraceData || inst.opcode == Opcode::SInstPrefetch)
|
||||
inst.src_count = (inst.opcode == Opcode::S_NOP || inst.opcode == Opcode::S_WAITCNT ||
|
||||
inst.opcode == Opcode::S_WAITCNT_DEPCTR || inst.opcode == Opcode::S_SLEEP ||
|
||||
inst.opcode == Opcode::S_SENDMSG || inst.opcode == Opcode::S_TRAP ||
|
||||
inst.opcode == Opcode::S_TTRACEDATA || inst.opcode == Opcode::S_INST_PREFETCH)
|
||||
? 1
|
||||
: 0;
|
||||
inst.branch_offset = static_cast<int32_t>(static_cast<int16_t>(simm)) * 4;
|
||||
inst.branch_target = pc + 4u + static_cast<uint32_t>(inst.branch_offset);
|
||||
SetRawWords(inst, code, word_index, 1);
|
||||
|
||||
if (inst.opcode == Opcode::Unsupported) {
|
||||
if (inst.opcode == Opcode::UNSUPPORTED) {
|
||||
SetUnsupported(inst, Family::SOPP, opcode, "SOPP control-flow opcode is not implemented");
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user