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https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-21 03:16:54 +02:00
shader: reflect tessellation strides across forward branches, DS write widths, and packed patch masks
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@@ -21,14 +21,17 @@ struct TessellationAddress {
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Kind kind = Kind::Unknown;
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uint32_t coefficient = 0;
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uint32_t constant = 0;
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bool operator==(const TessellationAddress&) const = default;
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};
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uint32_t ReflectTessellationStride(const Decoder::Program& program, bool local,
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uint32_t control_points, uint32_t input_stride) {
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using namespace Decoder;
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using Address = TessellationAddress;
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using Kind = Address::Kind;
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std::array<Address, IR::NumVectorRegs> registers {};
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using Address = TessellationAddress;
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using Kind = Address::Kind;
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using Registers = std::array<Address, IR::NumVectorRegs>;
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Registers registers {};
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registers[local ? 3u : 1u] =
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local ? Address {Kind::Affine, 1u, 0u} : Address {Kind::PackedControlPoint};
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const auto constant = [](uint32_t value) { return Address {Kind::Affine, 0u, value}; };
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@@ -79,14 +82,28 @@ uint32_t ReflectTessellationStride(const Decoder::Program& program, bool local,
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? value
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: Address {};
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};
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// A forward branch joins its target with the fallthrough path. Definitions that
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// differ between the paths are unknown there.
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std::unordered_map<uint32_t, Registers> joins;
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const auto merge = [](Registers& into, const Registers& from) {
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for (uint32_t index = 0; index < into.size(); index++) {
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if (into[index] != from[index]) into[index] = {};
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}
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};
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uint32_t stride = 0;
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for (const auto& inst: program.instructions) {
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// Stage exits preserve the active path's definitions. An internal join
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// would require merging register definitions.
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EXIT_NOT_IMPLEMENTED(IsDirectBranch(inst.opcode) &&
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inst.branch_target != program.instructions.back().pc);
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const bool local_store =
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inst.opcode == Opcode::DS_WRITE_B32 || inst.opcode == Opcode::DS_WRITE2_B32;
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if (const auto join = joins.find(inst.pc); join != joins.end()) {
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merge(registers, join->second);
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joins.erase(join);
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}
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if (IsDirectBranch(inst.opcode)) {
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EXIT_NOT_IMPLEMENTED(inst.branch_target <= inst.pc);
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if (const auto [join, inserted] = joins.try_emplace(inst.branch_target, registers);
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!inserted)
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merge(join->second, registers);
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}
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const bool local_store = IsDsWriteOpcode(inst.opcode);
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const bool buffer_store = inst.opcode == Opcode::BUFFER_STORE_DWORD ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX2 ||
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inst.opcode == Opcode::BUFFER_STORE_DWORDX3 ||
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@@ -123,6 +140,12 @@ uint32_t ReflectTessellationStride(const Decoder::Program& program, bool local,
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if (rhs.constant == 0u && third.constant == 8u) value = constant(0u);
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}
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break;
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case Opcode::V_AND_B32:
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if ((lhs.kind == Kind::PackedControlPoint && rhs == constant(0xffu)) ||
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(rhs.kind == Kind::PackedControlPoint && lhs == constant(0xffu)))
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value = constant(0u);
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break;
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case Opcode::V_MUL_LO_U32: value = multiply(lhs, rhs); break;
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case Opcode::V_MUL_U32_U24: value = multiply(low24(lhs), low24(rhs)); break;
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case Opcode::V_MAD_U32_U24: value = add(multiply(low24(lhs), low24(rhs)), third); break;
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case Opcode::V_LSHL_ADD_U32:
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@@ -149,7 +172,7 @@ uint32_t ReflectTessellationStride(const Decoder::Program& program, bool local,
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}
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registers.at(inst.dst.reg) = value;
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}
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EXIT_NOT_IMPLEMENTED(stride == 0u);
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EXIT_NOT_IMPLEMENTED(!joins.empty() || stride == 0u);
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return stride;
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}
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@@ -166,6 +166,8 @@ void ApplyMemoryInfo(Instruction& inst, const MemoryOpcodeInfo* info) {
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inst.formatted = info->formatted;
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}
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} // namespace
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bool IsDsWriteOpcode(Opcode opcode) {
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switch (opcode) {
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case Opcode::DS_WRITE_B8:
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@@ -184,6 +186,8 @@ bool IsDsWriteOpcode(Opcode opcode) {
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}
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}
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namespace {
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bool IsDsAtomicOpcode(Opcode opcode) {
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switch (opcode) {
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case Opcode::DS_ADD_U32:
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@@ -882,6 +882,7 @@ Program DecodeFrontProgram(std::span<const uint32_t> front);
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void DecodeProgram(std::span<const uint32_t> code, Program& program);
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bool IsConditionalBranch(Opcode opcode);
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bool IsDirectBranch(Opcode opcode);
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bool IsDsWriteOpcode(Opcode opcode);
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void DecodeScalarSource(uint32_t code, uint32_t pc, Operand& operand);
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void DecodeScalarDestination(uint32_t code, uint32_t pc, Operand& operand);
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