mirror of
https://github.com/KytyPS5/KytyPS5.git
synced 2026-10-19 18:36:53 +02:00
shader: DS_READ_U16_D16, V_LSHRREV_B64,
This commit is contained in:
nmzik
@@ -103,6 +103,7 @@ constexpr MemoryOpcodeInfo DS_OPCODE_LIST[] = {
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{0x4du, Opcode::DS_WRITE_B64, 2, 32}, {0x4eu, Opcode::DS_WRITE2_B64, 4, 32},
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{0x4fu, Opcode::DS_WRITE2ST64_B64, 4, 32}, {0x76u, Opcode::DS_READ_B64, 2, 32},
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{0x77u, Opcode::DS_READ2_B64, 4, 32}, {0x78u, Opcode::DS_READ2ST64_B64, 4, 32},
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{0xa6u, Opcode::DS_READ_U16_D16, 1, 16},
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{0xb0u, Opcode::DS_WRITE_ADDTID_B32, 1, 32}, {0xb1u, Opcode::DS_READ_ADDTID_B32, 1, 32},
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{0xdeu, Opcode::DS_WRITE_B96, 3, 32}, {0xdfu, Opcode::DS_WRITE_B128, 4, 32},
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{0xfeu, Opcode::DS_READ_B96, 3, 32}, {0xffu, Opcode::DS_READ_B128, 4, 32},
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@@ -420,6 +421,11 @@ void DecodeDs(uint32_t pc, std::span<const uint32_t> code, uint32_t word_index,
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}
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DecodeVectorGpr(vdst, inst.dst);
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if (inst.opcode == Opcode::DS_READ_U16_D16) {
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// Native D16 reads update only the selected destination half. Reuse the partial
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// destination representation so the typed lowering preserves the upper word.
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inst.dst.sdwa_sel = 4u;
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}
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DecodeVectorGpr(addr, inst.src0);
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DecodeVectorGpr(data0, inst.src1);
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DecodeVectorGpr(data1, inst.src2);
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@@ -299,6 +299,7 @@ enum class Opcode {
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V_LSHRREV_B32,
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V_ASHR_I32,
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V_ASHRREV_I32,
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V_LSHRREV_B64,
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V_LSHLREV_B16,
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V_LSHRREV_B16,
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V_ASHRREV_I16,
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@@ -492,6 +493,7 @@ enum class Opcode {
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DS_READ_U8,
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DS_READ_I16,
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DS_READ_U16,
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DS_READ_U16_D16,
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DS_READ2_B32,
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DS_READ2ST64_B32,
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DS_READ_B32,
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@@ -281,6 +281,7 @@ constexpr OpcodeMap VOP3_OPCODE_LIST[] = {
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{0x16au, Opcode::V_MUL_HI_U32},
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{0x16bu, Opcode::V_MUL_LO_I32},
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{0x16cu, Opcode::V_MUL_HI_I32},
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{0x300u, Opcode::V_LSHRREV_B64},
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{0x303u, Opcode::V_ADD_NC_U16},
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{0x304u, Opcode::V_SUB_NC_U16},
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{0x307u, Opcode::V_LSHRREV_B16},
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@@ -1247,6 +1248,7 @@ uint32_t NativeVop3SourceCount(Opcode opcode) {
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case Opcode::V_MIN_I16:
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case Opcode::V_ADD_NC_I16:
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case Opcode::V_SUB_NC_I16:
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case Opcode::V_LSHRREV_B64:
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case Opcode::V_LSHLREV_B16:
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case Opcode::V_LSHRREV_B16:
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case Opcode::V_ASHRREV_I16:
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@@ -624,6 +624,7 @@ bool LowerMemoryInstruction(const Decoder::Instruction& decoded, BasicBlock& blo
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case Decoder::Opcode::DS_READ_U8:
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case Decoder::Opcode::DS_READ_I16:
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case Decoder::Opcode::DS_READ_U16:
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case Decoder::Opcode::DS_READ_U16_D16:
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case Decoder::Opcode::DS_READ_B32:
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case Decoder::Opcode::DS_READ_B64:
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case Decoder::Opcode::DS_READ_B96:
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@@ -763,6 +764,7 @@ bool IsMemoryOpcode(Decoder::Opcode opcode) {
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case Decoder::Opcode::DS_READ_U8:
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case Decoder::Opcode::DS_READ_I16:
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case Decoder::Opcode::DS_READ_U16:
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case Decoder::Opcode::DS_READ_U16_D16:
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case Decoder::Opcode::DS_READ2_B32:
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case Decoder::Opcode::DS_READ2ST64_B32:
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case Decoder::Opcode::DS_READ_B32:
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@@ -250,6 +250,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::V_LSHLREV_B16, Opcode::ShiftLeftLogicalU16},
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{Decoder::Opcode::V_LSHR_B32, Opcode::ShiftRightLogicalU32},
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{Decoder::Opcode::V_LSHRREV_B32, Opcode::ShiftRightLogicalU32},
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{Decoder::Opcode::V_LSHRREV_B64, Opcode::ShiftRightLogicalU64},
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{Decoder::Opcode::V_LSHRREV_B16, Opcode::ShiftRightLogicalU16},
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{Decoder::Opcode::V_ASHR_I32, Opcode::ShiftRightArithmeticI32},
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{Decoder::Opcode::V_ASHRREV_I32, Opcode::ShiftRightArithmeticI32},
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@@ -395,6 +396,7 @@ constexpr LowerMap LOWER_OPS[] = {
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{Decoder::Opcode::DS_READ_U8, Opcode::DsReadUbyte},
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{Decoder::Opcode::DS_READ_I16, Opcode::DsReadSshort},
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{Decoder::Opcode::DS_READ_U16, Opcode::DsReadUshort},
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{Decoder::Opcode::DS_READ_U16_D16, Opcode::DsReadUshort},
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{Decoder::Opcode::DS_READ2_B32, Opcode::DsRead2B32},
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{Decoder::Opcode::DS_READ2ST64_B32, Opcode::DsRead2B32},
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{Decoder::Opcode::DS_READ_B32, Opcode::DsReadB32},
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@@ -466,6 +468,7 @@ bool IsReversedBinary(Decoder::Opcode opcode) {
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case Decoder::Opcode::V_LSHLREV_B32:
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case Decoder::Opcode::V_LSHRREV_B32:
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case Decoder::Opcode::V_ASHRREV_I32:
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case Decoder::Opcode::V_LSHRREV_B64:
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case Decoder::Opcode::V_LSHLREV_B16:
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case Decoder::Opcode::V_LSHRREV_B16:
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case Decoder::Opcode::V_ASHRREV_I16:
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@@ -11393,6 +11393,7 @@ CoverageClass ClassifyOpcode(ShaderOpcode opcode,
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case Opcode::DS_READ_U8:
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case Opcode::DS_READ_I16:
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case Opcode::DS_READ_U16:
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case Opcode::DS_READ_U16_D16:
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case Opcode::DS_READ2_B32:
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case Opcode::DS_READ_B32:
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case Opcode::DS_READ_B64:
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@@ -12931,6 +12932,30 @@ TestCase VectorShiftCountsMaskLowBits() {
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O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
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}
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TestCase VectorVop3LshrrevB64Captured() {
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using O = ShaderOpcode;
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std::vector<u32> code;
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AppendSMovLiteral(&code, 106, 0x89abcdefu);
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AppendSMovLiteral(&code, 107, 0x01234567u);
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AppendVMovU32(&code, 12, 68);
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code.push_back(0xd7000001u);
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code.push_back(0x0000d50cu); // v_lshrrev_b64 v[1:2], v12, vcc
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AppendStoreVgpr(&code, 1, 0);
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AppendStoreVgpr(&code, 2, 1);
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AppendEnd(&code);
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TestCase test;
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test.name = "VectorVop3LshrrevB64Captured";
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test.code = std::move(code);
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test.expected = {0x789abcdeu, 0x00123456u};
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test.opcodes = {O::S_MOV_B32, O::V_MOV_B32, O::V_LSHRREV_B64,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM};
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test.required_spirv = {"OpShiftRightLogical", "OpSelect"};
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test.forbidden_spirv = {"OpTypeInt 64"};
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return test;
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}
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TestCase VectorVop3IntegerOps() {
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using O = ShaderOpcode;
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@@ -14735,16 +14760,30 @@ TestCase VectorVopcCmpxNeU64CapturedExecMask() {
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AppendVMovU32(&code, 31, 4);
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code.push_back(0x7dea0e80u); // v_cmpx_ne_u64 exec, 0, v[7:8]
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AppendBufferStoreDword(&code, 8, 31);
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AppendVMovU32(&code, 2, 0);
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AppendVMovU32(&code, 3, 0);
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AppendVMovU32(&code, 31, 8);
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code.push_back(0x7dea0480u); // v_cmpx_ne_u64 exec, 0, v[2:3]
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AppendBufferStoreDword(&code, 3, 31);
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code.push_back(EncodeSMovB32(126, InlineU32(1)));
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AppendVMovU32(&code, 3, 1);
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AppendVMovU32(&code, 31, 12);
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code.push_back(0x7dea0480u); // v_cmpx_ne_u64 exec, 0, v[2:3]
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AppendBufferStoreDword(&code, 3, 31);
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AppendEnd(&code);
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TestCase test{"VectorVopcCmpxNeU64CapturedExecMask",
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code,
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{0x11223344u, 0x55667788u},
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{0x11223344u, 1u},
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{0x11223344u, 0x55667788u, 0xaabbccddu, 0xeeff0011u},
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{0x11223344u, 1u, 0xaabbccddu, 1u},
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{O::V_MOV_B32, O::V_CMPX_NE_U64, O::BUFFER_STORE_DWORD,
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O::S_MOV_B32, O::S_ENDPGM}};
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test.decoded_counts = {{"V_CMPX_NE_U64 exec_lo, 0, v7", 2}};
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test.native_ir_counts = {{"CompareNeU64 exec_lo, 0x00000000, v7", 2}};
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test.decoded_counts = {{"V_CMPX_NE_U64 exec_lo, 0, v7", 2},
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{"V_CMPX_NE_U64 exec_lo, 0, v2", 2}};
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test.native_ir_counts = {{"CompareNeU64 exec_lo, 0x00000000, v7", 2},
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{"CompareNeU64 exec_lo, 0x00000000, v2", 2}};
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return test;
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}
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@@ -17197,6 +17236,38 @@ TestCase DsReadWriteVariants() {
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O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
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}
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TestCase DsReadU16D16CapturedPreservesHighHalf() {
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using O = ShaderOpcode;
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std::vector<u32> code;
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AppendVMovU32(&code, 1, 0);
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AppendVMovLiteral(&code, 2, 0x89abcdefu);
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code.push_back(EncodeDs0(0x0d));
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code.push_back(EncodeDs1(0, 2, 1)); // ds_write_b32 v2, v1
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AppendVMovLiteral(&code, 3, 0x12345678u);
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code.push_back(EncodeDs0(0xa6));
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code.push_back(EncodeDs1(3, 0, 1)); // ds_read_u16_d16 v3, v1
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AppendVMovU32(&code, 7, 0);
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code.push_back(0xda980000u);
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code.push_back(0x07000007u); // captured ds_read_u16_d16 v7, v7
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AppendStoreVgpr(&code, 3, 0);
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AppendStoreVgpr(&code, 7, 1);
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AppendEnd(&code);
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TestCase test{"DsReadU16D16CapturedPreservesHighHalf",
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code,
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std::vector<u32>(2, 0),
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{0x1234cdefu, 0x0000cdefu},
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{O::V_MOV_B32, O::DS_WRITE_B32, O::DS_READ_U16_D16,
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O::BUFFER_STORE_DWORD, O::S_ENDPGM}};
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test.decoded_counts = {{"DS_READ_U16_D16", 2}};
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test.native_ir_counts = {{"DsReadUshort", 2}};
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return test;
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}
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TestCase DsReadWrite2Variants() {
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using O = ShaderOpcode;
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@@ -19569,6 +19640,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(Vop3Med3I16Captured);
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AddCase(Vop2SdwaMinU32PreservesWordDestination);
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AddCase(VectorShiftCountsMaskLowBits);
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AddCase(VectorVop3LshrrevB64Captured);
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AddCase(VectorVop3IntegerOps);
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AddCase(VectorBfeI32SignExtendsField);
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AddCase(VectorAlignByteUsesFiveBitByteOffset);
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@@ -19713,6 +19785,7 @@ std::vector<TestCase> MakeCases() {
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AddCase(ScratchIsPrivatePerInvocation);
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AddCase(FlatStoreVariants);
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AddCase(DsReadWriteVariants);
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AddCase(DsReadU16D16CapturedPreservesHighHalf);
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AddCase(DsAppendConsumeUsesEncodedLdsSelector);
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AddCase(DsAppendUsesEncodedGdsSelector);
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AddCase(DsGdsSubdwordAndAtomicWrites);
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@@ -6560,6 +6560,7 @@ void TestNewShaderRecompilerDsSubDwordLowering() {
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EncodeDs0(0x3a, 4), EncodeDs1(43, 0, 1), // ds_read_u8 v43, v1
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EncodeDs0(0x3b, 6), EncodeDs1(44, 0, 1), // ds_read_i16 v44, v1
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EncodeDs0(0x3c, 8), EncodeDs1(45, 0, 1), // ds_read_u16 v45, v1
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0xda980000u, 0x07000007u, // ds_read_u16_d16 v7, v7
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0xbf810000u,
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};
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@@ -6582,6 +6583,8 @@ void TestNewShaderRecompilerDsSubDwordLowering() {
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"new decoder did not decode DS signed short read");
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Check(Common::ContainsStr(result.decoded_dump, "ds_read_u16"),
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"new decoder did not decode DS unsigned short read");
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Check(Common::ContainsStr(result.decoded_dump, "DS_READ_U16_D16 v7.sdwa(sel=4"),
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"new decoder did not decode captured DS masked short read");
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Check(Common::ContainsStr(result.decoded_dump, "dwords=1 bits=8"),
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"DS byte decode did not preserve byte-width metadata");
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Check(Common::ContainsStr(result.decoded_dump, "dwords=1 bits=16"),
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@@ -6598,6 +6601,8 @@ void TestNewShaderRecompilerDsSubDwordLowering() {
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"DS signed short read did not lower to explicit IR");
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Check(Common::ContainsStr(result.ir_dump, "DsReadUshort v45"),
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"DS unsigned short read did not lower to explicit IR");
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Check(Common::ContainsStr(result.ir_dump, "DsReadUshort v7.sdwa(sel=4"),
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"DS masked short read did not preserve its partial destination");
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Check(SpirvContainsOpcode(result.spirv, 61),
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"SPIR-V binary does not contain OpLoad");
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Check(SpirvContainsOpcode(result.spirv, 62),
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@@ -8368,6 +8373,45 @@ void TestNewShaderRecompilerU64PairLowering() {
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CompileResult result;
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std::string error;
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const uint32_t lshrrev_b64_shader[] = {
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0xd7000001u, 0x0000d50cu, // v_lshrrev_b64 v[1:2], v12, vcc
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EncodeSopp(0x01),
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};
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Decoder::Instruction decoded_lshrrev_b64;
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Check(Decoder::DecodeInstruction(lshrrev_b64_shader, 0u,
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decoded_lshrrev_b64, &error),
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error.c_str());
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Check(decoded_lshrrev_b64.opcode == Decoder::Opcode::V_LSHRREV_B64 &&
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decoded_lshrrev_b64.dst.kind == Decoder::OperandKind::Vgpr &&
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decoded_lshrrev_b64.dst.reg == 1u &&
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decoded_lshrrev_b64.src_count == 2u &&
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decoded_lshrrev_b64.src0.kind == Decoder::OperandKind::Vgpr &&
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decoded_lshrrev_b64.src0.reg == 12u &&
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decoded_lshrrev_b64.src1.kind == Decoder::OperandKind::VccLo,
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"decoder rejected captured VOP3 V_LSHRREV_B64 fields");
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Check(TryRecompile(lshrrev_b64_shader, options, result, &error),
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error.c_str());
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Check(Common::ContainsStr(result.decoded_dump,
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"V_LSHRREV_B64 v1, v12, vcc_lo"),
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"captured VOP3 V_LSHRREV_B64 was not present in the decoded dump");
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Decoder::Program decoded_lshrrev_b64_program;
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CFG::Graph graph_lshrrev_b64;
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IR::Program native_lshrrev_b64;
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Check(Decoder::DecodeProgram(lshrrev_b64_shader,
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decoded_lshrrev_b64_program, &error),
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error.c_str());
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Check(CFG::BuildGraph(decoded_lshrrev_b64_program, graph_lshrrev_b64,
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&error) &&
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CFG::Structurize(graph_lshrrev_b64, &error),
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error.c_str());
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Check(IR::LowerProgram(decoded_lshrrev_b64_program, graph_lshrrev_b64,
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ShaderType::Compute, 64u, native_lshrrev_b64, &error),
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error.c_str());
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Check(Common::ContainsStr(IR::ProgramToString(native_lshrrev_b64),
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"ShiftRightLogicalU64 v1, vcc_lo, v12"),
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"V_LSHRREV_B64 did not reverse its encoded operands for pair-U64 IR");
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CheckSpirvBinaryValidates(result.spirv);
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const uint32_t cmpx_i64_shader[] = {
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0xd4b5007eu, 0x00020e80u, // v_cmpx_ne_i64 exec, 0, v[7:8]
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EncodeSopp(0x01),
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@@ -8432,6 +8476,26 @@ void TestNewShaderRecompilerU64PairLowering() {
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"V_CMPX_NE_U64 did not lower to masked 64-bit inequality");
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CheckSpirvBinaryValidates(result.spirv);
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const uint32_t cmpx_v2_shader[] = {
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0x7dea0480u, // v_cmpx_ne_u64 exec, 0, v[2:3]
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EncodeSopp(0x01),
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};
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Decoder::Instruction decoded_cmpx_v2;
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Check(Decoder::DecodeInstruction(cmpx_v2_shader, 0u, decoded_cmpx_v2,
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&error),
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error.c_str());
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Check(decoded_cmpx_v2.opcode == Decoder::Opcode::V_CMPX_NE_U64 &&
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decoded_cmpx_v2.dst.kind == Decoder::OperandKind::ExecLo &&
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decoded_cmpx_v2.src0.value == 0u &&
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decoded_cmpx_v2.src1.kind == Decoder::OperandKind::Vgpr &&
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decoded_cmpx_v2.src1.reg == 2u,
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"decoder rejected reported VOPC V_CMPX_NE_U64 fields");
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Check(TryRecompile(cmpx_v2_shader, options, result, &error), error.c_str());
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Check(Common::ContainsStr(result.decoded_dump,
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"V_CMPX_NE_U64 exec_lo, 0, v2"),
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"reported VOPC V_CMPX_NE_U64 was not present in the decoded dump");
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CheckSpirvBinaryValidates(result.spirv);
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const uint32_t empty_shader[] = {EncodeSopp(0x01)};
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Check(TryRecompile(empty_shader, options, result, &error), error.c_str());
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